From 2ecf17264debe1bc3399fe587690c78d03e8401b Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Tue, 9 Mar 2021 12:01:28 +0100 Subject: hw/misc: Add a basic Aspeed LPC controller model This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater Signed-off-by: Andrew Jeffery Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw/arm/aspeed_soc.h') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 11cfe6e358..42c64bd28b 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -28,6 +28,7 @@ #include "hw/sd/aspeed_sdhci.h" #include "hw/usb/hcd-ehci.h" #include "qom/object.h" +#include "hw/misc/aspeed_lpc.h" #define ASPEED_SPIS_NUM 2 #define ASPEED_EHCIS_NUM 2 @@ -61,6 +62,7 @@ struct AspeedSoCState { AspeedGPIOState gpio_1_8v; AspeedSDHCIState sdhci; AspeedSDHCIState emmc; + AspeedLPCState lpc; }; #define TYPE_ASPEED_SOC "aspeed-soc" -- cgit v1.2.3-55-g7522