From c752bb079beb57a8527e55859ce4c416fb1663c3 Mon Sep 17 00:00:00 2001 From: Havard Skinnemoen Date: Thu, 10 Sep 2020 22:20:55 -0700 Subject: hw/nvram: NPCM7xx OTP device model This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Tested-by: Alexander Bulekov Signed-off-by: Havard Skinnemoen Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell --- include/hw/arm/npcm7xx.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/hw/arm') diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index ba7495869d..5816a07a72 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" +#include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "target/arm/cpu.h" @@ -68,6 +69,8 @@ typedef struct NPCM7xxState { NPCM7xxGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; + NPCM7xxOTPState key_storage; + NPCM7xxOTPState fuse_array; } NPCM7xxState; #define TYPE_NPCM7XX "npcm7xx" -- cgit v1.2.3-55-g7522