From dcc345b61ebe499f8f707de2535c2790c52cc703 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Tue, 11 Dec 2018 23:38:12 +0100 Subject: spapr: introduce a new machine IRQ backend for XIVE The XIVE IRQ backend uses the same layout as the new XICS backend but covers the full range of the IRQ number space. The IRQ numbers for the CPU IPIs are allocated at the bottom of this space, below 4K, to preserve compatibility with XICS which does not use that range. This should be enough given that the maximum number of CPUs is 1024 for the sPAPR machine under QEMU. For the record, the biggest POWER8 or POWER9 system has a maximum of 1536 HW threads (16 sockets, 192 cores, SMT8). Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- include/hw/ppc/spapr_irq.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw/ppc/spapr_irq.h') diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index bd7301e6d9..23cdb51b87 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -13,6 +13,7 @@ /* * IRQ range offsets per device type */ +#define SPAPR_IRQ_IPI 0x0 #define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */ #define SPAPR_IRQ_HOTPLUG 0x1001 #define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */ @@ -42,6 +43,7 @@ typedef struct sPAPRIrq { extern sPAPRIrq spapr_irq_xics; extern sPAPRIrq spapr_irq_xics_legacy; +extern sPAPRIrq spapr_irq_xive; void spapr_irq_init(sPAPRMachineState *spapr, Error **errp); int spapr_irq_claim(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp); -- cgit v1.2.3-55-g7522