From 099be0358ee2cfb1cadf80d14297511215885219 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 13 Oct 2020 17:17:25 -0700 Subject: hw/riscv: sifive_u: Allow specifying the CPU Allow the user to specify the main application CPU for the sifive_u machine. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Palmer Dabbelt Tested-by: Bin Meng Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com --- include/hw/riscv/sifive_u.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/hw/riscv') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 22e7e6efa1..a9f7b4a084 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -48,6 +48,7 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; uint32_t serial; + char *cpu_type; } SiFiveUSoCState; #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") -- cgit v1.2.3-55-g7522