From 9972479faccfe5a4c1e62252c0c70e9daa2f8f1a Mon Sep 17 00:00:00 2001 From: Wilfred Mallawa Date: Thu, 3 Mar 2022 14:54:26 +1000 Subject: riscv: opentitan: Connect opentitan SPI Host Connect spi host[1/0] to opentitan. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) (limited to 'include/hw/riscv') diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 00da9ded43..68892cd8e5 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -23,11 +23,18 @@ #include "hw/intc/sifive_plic.h" #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" +#include "hw/ssi/ibex_spi_host.h" #include "qom/object.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) +enum { + OPENTITAN_SPI_HOST0, + OPENTITAN_SPI_HOST1, + OPENTITAN_NUM_SPI_HOSTS, +}; + struct LowRISCIbexSoCState { /*< private >*/ SysBusDevice parent_obj; @@ -37,6 +44,7 @@ struct LowRISCIbexSoCState { SiFivePLICState plic; IbexUartState uart; IbexTimerState timer; + IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; MemoryRegion flash_mem; MemoryRegion rom; @@ -89,15 +97,19 @@ enum { }; enum { - IBEX_TIMER_TIMEREXPIRED0_0 = 126, - IBEX_UART0_RX_PARITY_ERR_IRQ = 8, - IBEX_UART0_RX_TIMEOUT_IRQ = 7, - IBEX_UART0_RX_BREAK_ERR_IRQ = 6, - IBEX_UART0_RX_FRAME_ERR_IRQ = 5, - IBEX_UART0_RX_OVERFLOW_IRQ = 4, - IBEX_UART0_TX_EMPTY_IRQ = 3, - IBEX_UART0_RX_WATERMARK_IRQ = 2, - IBEX_UART0_TX_WATERMARK_IRQ = 1, + IBEX_UART0_TX_WATERMARK_IRQ = 1, + IBEX_UART0_RX_WATERMARK_IRQ = 2, + IBEX_UART0_TX_EMPTY_IRQ = 3, + IBEX_UART0_RX_OVERFLOW_IRQ = 4, + IBEX_UART0_RX_FRAME_ERR_IRQ = 5, + IBEX_UART0_RX_BREAK_ERR_IRQ = 6, + IBEX_UART0_RX_TIMEOUT_IRQ = 7, + IBEX_UART0_RX_PARITY_ERR_IRQ = 8, + IBEX_TIMER_TIMEREXPIRED0_0 = 126, + IBEX_SPI_HOST0_ERR_IRQ = 150, + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151, + IBEX_SPI_HOST1_ERR_IRQ = 152, + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153, }; #endif -- cgit v1.2.3-55-g7522