From 043715d1e0fbb3e3411be3f898c5b77b7f90327a Mon Sep 17 00:00:00 2001
From: Yongbok Kim
Date: Thu, 3 Jan 2019 16:46:32 +0100
Subject: target/mips: Update ITU to utilize SAARI and SAAR CP0 registers

Update ITU to utilize SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 include/hw/misc/mips_itu.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'include/hw')

diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 45a0c519b7..c44e7672b6 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -70,6 +70,10 @@ typedef struct MIPSITUState {
     /* ITU Control Register */
     uint64_t icr0;
 
+    /* SAAR */
+    bool saar_present;
+    void *saar;
+
 } MIPSITUState;
 
 /* Get ITC Configuration Tag memory region. */
-- 
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