From 5394dbcca8839bfb87bc65594170ba80f45054ec Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Wed, 13 Dec 2017 17:59:21 +0000 Subject: xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency (struct XilinxSPIPS is found there). Also move out a define and remove two double included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Tested-by: Edgar E. Iglesias Message-id: 20171126231634.9531-6-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'include/hw') diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa09629d..7f9e2fc687 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ = 0x3, READ_4 = 0x13, + FAST_READ = 0xb, FAST_READ_4 = 0x0c, + DOR = 0x3b, DOR_4 = 0x3c, + QOR = 0x6b, QOR_4 = 0x6c, + DIOR = 0xbb, DIOR_4 = 0xbc, + QIOR = 0xeb, QIOR_4 = 0xec, + + PP = 0x2, PP_4 = 0x12, + DPP = 0xa2, + QPP = 0x32, QPP_4 = 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" -- cgit v1.2.3-55-g7522 From ef06ca3946e284cb86fa712ba00f1c961e9456db Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Wed, 13 Dec 2017 17:59:21 +0000 Subject: xilinx_spips: Add support for RX discard and RX drain Add support for the RX discard and RX drain functionality. Also transmit one byte per dummy cycle (to the flash memories) with commands that require these. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 20171126231634.9531-8-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 167 +++++++++++++++++++++++++++++++++++++----- include/hw/ssi/xilinx_spips.h | 6 ++ 2 files changed, 155 insertions(+), 18 deletions(-) (limited to 'include/hw') diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 231aa5b6fb..691d48d36f 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -30,6 +30,7 @@ #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" +#include "hw/register.h" #include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG @@ -100,6 +101,14 @@ #define LQSPI_CFG_DUMMY_SHIFT 8 #define LQSPI_CFG_INST_CODE 0xFF +#define R_CMND (0xc0 / 4) + #define R_CMND_RXFIFO_DRAIN (1 << 19) + FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3) +#define R_CMND_EXT_ADD (1 << 15) + FIELD(CMND, RX_DISCARD, 8, 7) + FIELD(CMND, DUMMY_CYCLES, 2, 6) +#define R_CMND_DMA_EN (1 << 1) +#define R_CMND_PUSH_WAIT (1 << 0) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) @@ -116,7 +125,8 @@ #define LQSPI_ADDRESS_BITS 24 #define SNOOP_CHECKING 0xFF -#define SNOOP_NONE 0xFE +#define SNOOP_ADDR 0xF0 +#define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 static inline int num_effective_busses(XilinxSPIPS *s) @@ -146,9 +156,14 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) if (xilinx_spips_cs_is_set(s, i, field) && !found) { DB_PRINT_L(0, "selecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 0); + if (s->cs_lines_state[cs_to_set]) { + s->cs_lines_state[cs_to_set] = false; + s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + } } else { DB_PRINT_L(0, "deselecting slave %d\n", i); qemu_set_irq(s->cs_lines[cs_to_set], 1); + s->cs_lines_state[cs_to_set] = true; } } if (xilinx_spips_cs_is_set(s, i, field)) { @@ -157,6 +172,10 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) } if (!found) { s->snoop_state = SNOOP_CHECKING; + s->cmd_dummies = 0; + s->link_state = 1; + s->link_state_next = 1; + s->link_state_next_when = 0; DB_PRINT_L(1, "moving to snoop check state\n"); } } @@ -203,7 +222,11 @@ static void xilinx_spips_reset(DeviceState *d) /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] = 0x01090106; s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; + s->link_state = 1; + s->link_state_next = 1; + s->link_state_next_when = 0; s->snoop_state = SNOOP_CHECKING; + s->cmd_dummies = 0; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -238,14 +261,69 @@ static inline void stripe8(uint8_t *x, int num, bool dir) memcpy(x, r, sizeof(uint8_t) * num); } +static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) +{ + if (!qs) { + /* The SPI device is not a QSPI device */ + return -1; + } + + switch (command) { /* check for dummies */ + case READ: /* no dummy bytes/cycles */ + case PP: + case DPP: + case QPP: + case READ_4: + case PP_4: + case QPP_4: + return 0; + case FAST_READ: + case DOR: + case QOR: + case DOR_4: + case QOR_4: + return 1; + case DIOR: + case FAST_READ_4: + case DIOR_4: + return 2; + case QIOR: + case QIOR_4: + return 5; + default: + return -1; + } +} + +static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd) +{ + switch (cmd) { + case PP_4: + case QPP_4: + case READ_4: + case QIOR_4: + case FAST_READ_4: + case DOR_4: + case QOR_4: + case DIOR_4: + return 4; + default: + return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3; + } +} + static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) { int debug_level = 0; + XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s), + TYPE_XILINX_QSPIPS); for (;;) { int i; uint8_t tx = 0; uint8_t tx_rx[num_effective_busses(s)]; + uint8_t dummy_cycles = 0; + uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { @@ -258,54 +336,102 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] = fifo8_pop(&s->tx_fifo); } stripe8(tx_rx, num_effective_busses(s), false); - } else { + } else if (s->snoop_state >= SNOOP_ADDR) { tx = fifo8_pop(&s->tx_fifo); for (i = 0; i < num_effective_busses(s); ++i) { tx_rx[i] = tx; } + } else { + /* Extract a dummy byte and generate dummy cycles according to the + * link state */ + tx = fifo8_pop(&s->tx_fifo); + dummy_cycles = 8 / s->link_state; } for (i = 0; i < num_effective_busses(s); ++i) { int bus = num_effective_busses(s) - 1 - i; - DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); - tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); - DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); + if (dummy_cycles) { + int d; + for (d = 0; d < dummy_cycles; ++d) { + tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]); + } + } else { + DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); + tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); + DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); + } } - if (fifo8_is_full(&s->rx_fifo)) { + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + DB_PRINT_L(debug_level, "dircarding drained rx byte\n"); + /* Do nothing */ + } else if (s->rx_discard) { + DB_PRINT_L(debug_level, "dircarding discarded rx byte\n"); + s->rx_discard -= 8 / s->link_state; + } else if (fifo8_is_full(&s->rx_fifo)) { s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW; DB_PRINT_L(0, "rx FIFO overflow"); } else if (s->snoop_state == SNOOP_STRIPING) { stripe8(tx_rx, num_effective_busses(s), true); for (i = 0; i < num_effective_busses(s); ++i) { fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]); + DB_PRINT_L(debug_level, "pushing striped rx byte\n"); } } else { + DB_PRINT_L(debug_level, "pushing unstriped rx byte\n"); fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]); } + if (s->link_state_next_when) { + s->link_state_next_when--; + if (!s->link_state_next_when) { + s->link_state = s->link_state_next; + } + } + DB_PRINT_L(debug_level, "initial snoop state: %x\n", (unsigned)s->snoop_state); switch (s->snoop_state) { case (SNOOP_CHECKING): - switch (tx) { /* new instruction code */ - case READ: /* 3 address bytes, no dummy bytes/cycles */ - case PP: + /* Store the count of dummy bytes in the txfifo */ + s->cmd_dummies = xilinx_spips_num_dummies(q, tx); + addr_length = get_addr_length(s, tx); + if (s->cmd_dummies < 0) { + s->snoop_state = SNOOP_NONE; + } else { + s->snoop_state = SNOOP_ADDR + addr_length - 1; + } + switch (tx) { case DPP: - case QPP: - s->snoop_state = 3; - break; - case FAST_READ: /* 3 address bytes, 1 dummy byte */ case DOR: + case DOR_4: + s->link_state_next = 2; + s->link_state_next_when = addr_length + s->cmd_dummies; + break; + case QPP: + case QPP_4: case QOR: - case DIOR: /* FIXME: these vary between vendor - set to spansion */ - s->snoop_state = 4; + case QOR_4: + s->link_state_next = 4; + s->link_state_next_when = addr_length + s->cmd_dummies; + break; + case DIOR: + case DIOR_4: + s->link_state = 2; break; - case QIOR: /* 3 address bytes, 2 dummy bytes */ - s->snoop_state = 6; + case QIOR: + case QIOR_4: + s->link_state = 4; break; - default: + } + break; + case (SNOOP_ADDR): + /* Address has been transmitted, transmit dummy cycles now if + * needed */ + if (s->cmd_dummies < 0) { s->snoop_state = SNOOP_NONE; + } else { + s->snoop_state = s->cmd_dummies; } break; case (SNOOP_STRIPING): @@ -483,6 +609,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { XilinxQSPIPS *q = XILINX_QSPIPS(opaque); + XilinxSPIPS *s = XILINX_SPIPS(opaque); xilinx_spips_write(opaque, addr, value, size); addr >>= 2; @@ -490,6 +617,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, if (addr == R_LQSPI_CFG) { xilinx_qspips_invalidate_mmio_ptr(q); } + if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { + fifo8_reset(&s->rx_fifo); + } } static const MemoryRegionOps qspips_ops = { @@ -632,6 +762,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) } s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 7f9e2fc687..bac90a53ce 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -61,13 +61,19 @@ struct XilinxSPIPS { uint8_t num_busses; uint8_t snoop_state; + int cmd_dummies; + uint8_t link_state; + uint8_t link_state_next; + uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; Fifo8 rx_fifo; Fifo8 tx_fifo; uint8_t num_txrx_bytes; + uint32_t rx_discard; uint32_t regs[XLNX_SPIPS_R_MAX]; }; -- cgit v1.2.3-55-g7522 From 275e28cccc1a915cc1ac6bdf367aa71555593bb4 Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Wed, 13 Dec 2017 17:59:22 +0000 Subject: xilinx_spips: Add support for zero pumping Add support for zero pumping according to the transfer size register. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 20171126231634.9531-10-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 47 ++++++++++++++++++++++++++++++++++++------- include/hw/ssi/xilinx_spips.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) (limited to 'include/hw') diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 4621dbbaad..878b17ea6b 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ FIELD(CMND, DUMMY_CYCLES, 2, 6) #define R_CMND_DMA_EN (1 << 1) #define R_CMND_PUSH_WAIT (1 << 0) +#define R_TRANSFER_SIZE (0xc4 / 4) #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) @@ -227,6 +228,7 @@ static void xilinx_spips_reset(DeviceState *d) s->link_state_next_when = 0; s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; + s->man_start_com = false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -464,6 +466,41 @@ static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) } } +static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) +{ + if (!s->regs[R_TRANSFER_SIZE]) { + return; + } + if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { + return; + } + /* + * The zero pump must never fill tx fifo such that rx overflow is + * possible + */ + while (s->regs[R_TRANSFER_SIZE] && + s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { + /* endianess just doesn't matter when zero pumping */ + tx_data_bytes(&s->tx_fifo, 0, 4, false); + s->regs[R_TRANSFER_SIZE] &= ~0x03ull; + s->regs[R_TRANSFER_SIZE] -= 4; + } +} + +static void xilinx_spips_check_flush(XilinxSPIPS *s) +{ + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } + if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { + s->man_start_com = false; + } + xilinx_spips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -533,7 +570,6 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { int mask = ~0; - int man_start_com = 0; XilinxSPIPS *s = opaque; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); @@ -541,8 +577,8 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, switch (addr) { case R_CONFIG: mask = ~(R_CONFIG_RSVD | MAN_START_COM); - if (value & MAN_START_COM) { - man_start_com = 1; + if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) { + s->man_start_com = true; } break; case R_INTR_STATUS: @@ -588,10 +624,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: xilinx_spips_update_cs_lines(s); - if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) || - (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) { - xilinx_spips_flush_txfifo(s); - } + xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); xilinx_spips_update_ixr(s); } diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index bac90a53ce..ad2175ac5c 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -76,6 +76,8 @@ struct XilinxSPIPS { uint32_t rx_discard; uint32_t regs[XLNX_SPIPS_R_MAX]; + + bool man_start_com; }; typedef struct { -- cgit v1.2.3-55-g7522 From c95997a39de679a1ae29c2f0637ec07f0291fedc Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Wed, 13 Dec 2017 17:59:22 +0000 Subject: xilinx_spips: Add support for the ZynqMP Generic QSPI Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Message-id: 20171126231634.9531-13-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- default-configs/arm-softmmu.mak | 2 +- hw/ssi/xilinx_spips.c | 579 ++++++++++++++++++++++++++++++++++++---- include/hw/ssi/xilinx_spips.h | 32 ++- 3 files changed, 564 insertions(+), 49 deletions(-) (limited to 'include/hw') diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index d37edc4312..b0d6e65038 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,5 +130,5 @@ CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y CONFIG_MSF2=y - CONFIG_FW_CFG_DMA=y +CONFIG_XILINX_AXI=y diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 3805d8b46d..ad1b2ba79f 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,30 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -116,9 +134,54 @@ #define R_MOD_ID (0xFC / 4) +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) +#define R_GQSPI_GEN_FIFO (0x140 / 4) +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) +#define R_GQSPI_DATA_STS (0x15c / 4) +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -137,42 +200,22 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) -{ - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); -} - -static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +static void xilinx_spips_update_cs(XilinxSPIPS *s, int field) { - int i, j; - bool found = false; - int field = s->regs[R_CONFIG] >> CS_SHIFT; + int i; for (i = 0; i < s->num_cs; i++) { - for (j = 0; j < num_effective_busses(s); j++) { - int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set = (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - if (s->cs_lines_state[cs_to_set]) { - s->cs_lines_state[cs_to_set] = false; - s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); - } - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - s->cs_lines_state[cs_to_set] = true; - } - } - if (xilinx_spips_cs_is_set(s, i, field)) { - found = true; + bool old_state = s->cs_lines_state[i]; + bool new_state = field & (1 << i); + + if (old_state != new_state) { + s->cs_lines_state[i] = new_state; + s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; s->link_state = 1; @@ -182,21 +225,51 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) } } +static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s) +{ + if (s->regs[R_GQSPI_GF_SNAPSHOT]) { + int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); + xilinx_spips_update_cs(XILINX_SPIPS(s), field); + } +} + +static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) +{ + int field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) == 2) { + /* Single bit chip-select for qspi */ + field &= 0x1; + field |= field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + field &= 0x1; + /* change from CS0 to CS1 */ + field <<= 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + field = 0; + } + xilinx_spips_update_cs(s, field); +} + static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |= + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >= s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | - IXR_TX_FIFO_MODE_FAIL); - /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |= - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); - /* drive external interrupt pin */ int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & IXR_ALL); if (new_irqline != s->irqline) { @@ -205,6 +278,37 @@ static void xilinx_spips_update_ixr(XilinxSPIPS *s) } } +static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s) +{ + uint32_t gqspi_int; + int new_irqline; + + s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |= + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + /* GQSPI Interrupt Trigger Status */ + gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK; + new_irqline = !!(gqspi_int & IXR_ALL); + + /* drive external interrupt pin */ + if (new_irqline != s->gqspi_irqline) { + s->gqspi_irqline = new_irqline; + qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline); + } +} + static void xilinx_spips_reset(DeviceState *d) { XilinxSPIPS *s = XILINX_SPIPS(d); @@ -234,6 +338,28 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } +static void xlnx_zynqmp_qspips_reset(DeviceState *d) +{ + XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d); + int i; + + xilinx_spips_reset(d); + + for (i = 0; i < XLNX_ZYNQMP_SPIPS_R_MAX; i++) { + s->regs[i] = 0; + } + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); + s->regs[R_GQSPI_TX_THRESH] = 1; + s->regs[R_GQSPI_RX_THRESH] = 1; + s->regs[R_GQSPI_GFIFO_THRESH] = 1; + s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK; + s->man_start_com_g = false; + s->gqspi_irqline = 0; + xlnx_zynqmp_qspips_update_ixr(s); +} + /* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: @@ -264,6 +390,108 @@ static inline void stripe8(uint8_t *x, int num, bool dir) memcpy(x, r, sizeof(uint8_t) * num); } +static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2] = { 0 }; + int num_stripes = 1; + uint8_t busses; + int i; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); + continue; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + + imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + s->regs[R_GQSPI_DATA_STS] = 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] = 0; + } + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" + " long - 2 ^ %" PRId8 " requested\n", imm); + } + s->regs[R_GQSPI_DATA_STS] = 1ul << imm; + } else { + s->regs[R_GQSPI_DATA_STS] = imm; + } + } + /* Zero length transfer check */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) && + (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) { + num_stripes = 2; + } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] = ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { + for (i = 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] = fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes == 1) { + /* mirror */ + tx_rx[1] = tx_rx[0]; + } + busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); + for (i = 0; i < 2; ++i) { + DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); + tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]); + DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); + } + if (s->regs[R_GQSPI_DATA_STS] > 1 && + busses == 0x3 && num_stripes == 2) { + s->regs[R_GQSPI_DATA_STS] -= 2; + } else if (s->regs[R_GQSPI_DATA_STS] > 0) { + s->regs[R_GQSPI_DATA_STS]--; + } + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i = 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -499,6 +727,25 @@ static void xilinx_spips_check_flush(XilinxSPIPS *s) xilinx_spips_update_ixr(s); } +static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s) +{ + bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { + xlnx_zynqmp_qspips_flush_fifo_g(s); + } + } else { + xilinx_spips_check_flush(XILINX_SPIPS(s)); + } + if (!gqspi_has_work) { + s->man_start_com_g = false; + } + xlnx_zynqmp_qspips_update_ixr(s); +} + static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) { int i; @@ -509,6 +756,53 @@ static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max) return max - i; } +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max == 0 || max > fifo->num) { + abort(); + } + *num = MIN(fifo->capacity - fifo->head, max); + ret = &fifo->data[fifo->head]; + fifo->head += *num; + fifo->head %= fifo->capacity; + fifo->num -= *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s = XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) { + return; + } + recv_fifo = &rq->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo = &s->rx_fifo; + } + while (recv_fifo->num >= 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd = pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret = stream_push(rq->dma, rq->dma_buf, 4); + assert(ret == 4); + xlnx_zynqmp_qspips_check_flush(rq); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -556,6 +850,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret <<= 8 * shortfall; } DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -565,6 +860,43 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, } +static uint64_t xlnx_zynqmp_qspips_read(void *opaque, + hwaddr addr, unsigned size) +{ + XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg = addr / 4; + uint32_t ret; + uint8_t rx_buf[4]; + int shortfall; + + if (reg <= R_MOD_ID) { + return xilinx_spips_read(opaque, addr, size); + } else { + switch (reg) { + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Read from empty GQSPI RX FIFO\n"); + return 0; + } + memset(rx_buf, 0, sizeof(rx_buf)); + shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf, + XILINX_SPIPS(s)->num_txrx_bytes); + ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) { + ret <<= 8 * shortfall; + } + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_ixr(s); + return ret; + default: + return s->regs[reg]; + } + } +} + static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { @@ -664,12 +996,81 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, } } +static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque); + uint32_t reg = addr / 4; + + if (reg <= R_MOD_ID) { + xilinx_qspips_write(opaque, addr, value, size); + } else { + switch (reg) { + case R_GQSPI_CNFG: + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { + s->man_start_com_g = true; + } + s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + break; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + break; + case R_GQSPI_FIFO_CTRL: + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |= value; + break; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &= ~value; + break; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &= ~value; + break; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + break; + default: + s->regs[reg] = value; + break; + } + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_check_flush(s); + xlnx_zynqmp_qspips_update_cs_lines(s); + xlnx_zynqmp_qspips_update_ixr(s); + } + xlnx_zynqmp_qspips_notify(s); +} + static const MemoryRegionOps qspips_ops = { .read = xilinx_spips_read, .write = xilinx_qspips_write, .endianness = DEVICE_LITTLE_ENDIAN, }; +static const MemoryRegionOps xlnx_zynqmp_qspips_ops = { + .read = xlnx_zynqmp_qspips_read, + .write = xlnx_zynqmp_qspips_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + #define LQSPI_CACHE_SIZE 1024 static void lqspi_load_cache(void *opaque, hwaddr addr) @@ -818,7 +1219,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) } memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s, - "spi", XLNX_SPIPS_R_MAX * 4); + "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4); sysbus_init_mmio(sbd, &s->iomem); s->irqline = -1; @@ -856,6 +1257,28 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) } } +static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev); + XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s); + + xilinx_qspips_realize(dev, errp); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); +} + +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -877,6 +1300,46 @@ static const VMStateDescription vmstate_xilinx_spips = { } }; +static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id) +{ + XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque; + XilinxSPIPS *qs = XILINX_SPIPS(s); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) && + fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) { + xlnx_zynqmp_qspips_update_ixr(s); + xlnx_zynqmp_qspips_update_cs_lines(s); + } + return 0; +} + +static const VMStateDescription vmstate_xilinx_qspips = { + .name = "xilinx_qspips", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0, + vmstate_xilinx_spips, XilinxSPIPS), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { + .name = "xlnx_zynqmp_qspips", + .version_id = 1, + .minimum_version_id = 1, + .post_load = xlnx_zynqmp_qspips_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0, + vmstate_xilinx_qspips, XilinxQSPIPS), + VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS), + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX), + VMSTATE_END_OF_LIST() + } +}; + static Property xilinx_qspips_properties[] = { /* We had to turn this off for 2.10 as it is not compatible with migration. * It can be enabled but will prevent the device to be migrated. @@ -921,6 +1384,19 @@ static void xilinx_spips_class_init(ObjectClass *klass, void *data) xsc->tx_fifo_size = TXFF_A; } +static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); + + dc->realize = xlnx_zynqmp_qspips_realize; + dc->reset = xlnx_zynqmp_qspips_reset; + dc->vmsd = &vmstate_xlnx_zynqmp_qspips; + xsc->reg_ops = &xlnx_zynqmp_qspips_ops; + xsc->rx_fifo_size = RXFF_A_Q; + xsc->tx_fifo_size = TXFF_A_Q; +} + static const TypeInfo xilinx_spips_info = { .name = TYPE_XILINX_SPIPS, .parent = TYPE_SYS_BUS_DEVICE, @@ -936,10 +1412,19 @@ static const TypeInfo xilinx_qspips_info = { .class_init = xilinx_qspips_class_init, }; +static const TypeInfo xlnx_zynqmp_qspips_info = { + .name = TYPE_XLNX_ZYNQMP_QSPIPS, + .parent = TYPE_XILINX_QSPIPS, + .instance_size = sizeof(XlnxZynqMPQSPIPS), + .instance_init = xlnx_zynqmp_qspips_init, + .class_init = xlnx_zynqmp_qspips_class_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index ad2175ac5c..75fc94ce5d 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,13 @@ #define XILINX_SPIPS_H #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -89,6 +91,30 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; + int gqspi_irqline; + + uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX]; + + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + Fifo32 fifo_g; + /* + * At the end of each generic command, misaligned extra bytes are discard + * or padded to tx and rx respectively to round it out (and avoid need for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; + bool man_start_com_g; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; @@ -100,6 +126,7 @@ typedef struct XilinxSPIPSClass { #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -111,4 +138,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ -- cgit v1.2.3-55-g7522 From babc1f30090b8541c9669d4ba74eedf0ee2894d8 Mon Sep 17 00:00:00 2001 From: Francisco Iglesias Date: Wed, 13 Dec 2017 17:59:22 +0000 Subject: xlnx-zcu102: Add support for the ZynqMP QSPI Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy QSPI) and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20171126231634.9531-14-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 54 insertions(+) (limited to 'include/hw') diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index bbe7d046e4..b126cf148b 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -151,6 +151,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo = drive_get_next(IF_MTD); + int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name = g_strdup_printf("qspi%d", bus); + + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name); + g_free(bus_name); + + flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ xlnx_zcu102_binfo.ram_size = ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c707c66322..325642058b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -171,6 +175,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); @@ -411,6 +418,25 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) g_free(bus_name); } + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + + /* Alias controller SPI bus to the SoC itself */ + bus_name = g_strdup_printf("qspi%d", i); + target_bus = g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a995..3e6fb9b7bd 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma; -- cgit v1.2.3-55-g7522 From 27f26bfed923e4c68a1acb61fdafcd0bc63abf71 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 13 Dec 2017 17:59:26 +0000 Subject: nvic: Make systick banked For the v8M security extension, there should be two systick devices, which use separate banked systick exceptions. The register interface is banked in the same way as for other banked registers, including the existence of an NS alias region for secure code to access the nonsecure timer. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 1512154296-5652-3-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 90 ++++++++++++++++++++++++++++++++++++------- include/hw/intc/armv7m_nvic.h | 4 +- 2 files changed, 80 insertions(+), 14 deletions(-) (limited to 'include/hw') diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63f2743576..dd49b6c335 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1827,6 +1827,36 @@ static const MemoryRegionOps nvic_sysreg_ns_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s = opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); + return memory_region_dispatch_write(mr, addr, value, size, attrs); +} + +static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + NVICState *s = opaque; + MemoryRegion *mr; + + /* Direct the access to the correct systick */ + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0); + return memory_region_dispatch_read(mr, addr, data, size, attrs); +} + +static const MemoryRegionOps nvic_systick_ops = { + .read_with_attrs = nvic_systick_read, + .write_with_attrs = nvic_systick_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s = opaque; @@ -2005,17 +2035,16 @@ static void nvic_systick_trigger(void *opaque, int n, int level) /* SysTick just asked us to pend its exception. * (This is different from an external interrupt line's * behaviour.) - * TODO: when we implement the banked systicks we must make - * this pend the correct banked exception. + * n == 0 : NonSecure systick + * n == 1 : Secure systick */ - armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false); + armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, n); } } static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s = NVIC(dev); - SysBusDevice *systick_sbd; Error *err = NULL; int regionlen; @@ -2032,14 +2061,35 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) /* include space for internal exception vectors */ s->num_irq += NVIC_FIRST_IRQ; - object_property_set_bool(OBJECT(&s->systick), true, "realized", &err); + object_property_set_bool(OBJECT(&s->systick[M_REG_NS]), true, + "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } - systick_sbd = SYS_BUS_DEVICE(&s->systick); - sysbus_connect_irq(systick_sbd, 0, - qdev_get_gpio_in_named(dev, "systick-trigger", 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_NS]), 0, + qdev_get_gpio_in_named(dev, "systick-trigger", + M_REG_NS)); + + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + /* We couldn't init the secure systick device in instance_init + * as we didn't know then if the CPU had the security extensions; + * so we have to do it here. + */ + object_initialize(&s->systick[M_REG_S], sizeof(s->systick[M_REG_S]), + TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&s->systick[M_REG_S]), sysbus_get_default()); + + object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true, + "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->systick[M_REG_S]), 0, + qdev_get_gpio_in_named(dev, "systick-trigger", + M_REG_S)); + } /* The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: @@ -2073,15 +2123,24 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); memory_region_add_subregion(&s->container, 0, &s->sysregmem); + + memory_region_init_io(&s->systickmem, OBJECT(s), + &nvic_systick_ops, s, + "nvic_systick", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x10, - sysbus_mmio_get_region(systick_sbd, 0), - 1); + &s->systickmem, 1); if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); + memory_region_init_io(&s->systick_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, &s->systickmem, + "nvic_systick_ns", 0xe0); + memory_region_add_subregion_overlap(&s->container, 0x20010, + &s->systick_ns_mem, 1); } sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); @@ -2099,12 +2158,17 @@ static void armv7m_nvic_instance_init(Object *obj) NVICState *nvic = NVIC(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - object_initialize(&nvic->systick, sizeof(nvic->systick), TYPE_SYSTICK); - qdev_set_parent_bus(DEVICE(&nvic->systick), sysbus_get_default()); + object_initialize(&nvic->systick[M_REG_NS], + sizeof(nvic->systick[M_REG_NS]), TYPE_SYSTICK); + qdev_set_parent_bus(DEVICE(&nvic->systick[M_REG_NS]), sysbus_get_default()); + /* We can't initialize the secure systick here, as we don't know + * yet if we need it. + */ sysbus_init_irq(sbd, &nvic->excpout); qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); - qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", 1); + qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", + M_REG_NUM_BANKS); } static void armv7m_nvic_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index ac7997ca8c..8bc29112e3 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -78,13 +78,15 @@ typedef struct NVICState { MemoryRegion sysregmem; MemoryRegion sysreg_ns_mem; + MemoryRegion systickmem; + MemoryRegion systick_ns_mem; MemoryRegion container; uint32_t num_irq; qemu_irq excpout; qemu_irq sysresetreq; - SysTickState systick; + SysTickState systick[M_REG_NUM_BANKS]; } NVICState; #endif -- cgit v1.2.3-55-g7522 From 4f0da466ca209c670c010e7aad0ed041e0bf2461 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 13 Dec 2017 17:59:26 +0000 Subject: xilinx_spips: Set all of the reset values Following the ZynqMP register spec let's ensure that all reset values are set. Signed-off-by: Alistair Francis Reviewed-by: Francisco Iglesias Message-id: 19836f3e0a298b13343c5a59c87425355e7fd8bd.1513104804.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 35 ++++++++++++++++++++++++++++++----- include/hw/ssi/xilinx_spips.h | 2 +- 2 files changed, 31 insertions(+), 6 deletions(-) (limited to 'include/hw') diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 899db814ee..42d9b04bd3 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -66,6 +66,7 @@ /* interrupt mechanism */ #define R_INTR_STATUS (0x04 / 4) +#define R_INTR_STATUS_RESET (0x104) #define R_INTR_EN (0x08 / 4) #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) @@ -102,6 +103,9 @@ #define R_SLAVE_IDLE_COUNT (0x24 / 4) #define R_TX_THRES (0x28 / 4) #define R_RX_THRES (0x2C / 4) +#define R_GPIO (0x30 / 4) +#define R_LPBK_DLY_ADJ (0x38 / 4) +#define R_LPBK_DLY_ADJ_RESET (0x33) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -140,8 +144,12 @@ #define R_GQSPI_IER (0x108 / 4) #define R_GQSPI_IDR (0x10c / 4) #define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_IMR_RESET (0xfbe) #define R_GQSPI_TX_THRESH (0x128 / 4) #define R_GQSPI_RX_THRESH (0x12c / 4) +#define R_GQSPI_GPIO (0x130 / 4) +#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4) +#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33) #define R_GQSPI_CNFG (0x100 / 4) FIELD(GQSPI_CNFG, MODE_EN, 30, 2) FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) @@ -177,8 +185,16 @@ FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) -#define R_GQSPI_MOD_ID (0x168 / 4) -#define R_GQSPI_MOD_ID_VALUE 0x010A0000 +#define R_GQSPI_MOD_ID (0x1fc / 4) +#define R_GQSPI_MOD_ID_RESET (0x10a0000) + +#define R_QSPIDMA_DST_CTRL (0x80c / 4) +#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) +#define R_QSPIDMA_DST_I_MASK (0x820 / 4) +#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) +#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) +#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) + /* size of TXRX FIFOs */ #define RXFF_A (128) #define TXFF_A (128) @@ -351,11 +367,20 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) fifo8_reset(&s->rx_fifo_g); fifo8_reset(&s->rx_fifo_g); fifo32_reset(&s->fifo_g); + s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET; + s->regs[R_GPIO] = 1; + s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET; + s->regs[R_GQSPI_GFIFO_THRESH] = 0x10; + s->regs[R_MOD_ID] = 0x01090101; + s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET; s->regs[R_GQSPI_TX_THRESH] = 1; s->regs[R_GQSPI_RX_THRESH] = 1; - s->regs[R_GQSPI_GFIFO_THRESH] = 1; - s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK; - s->regs[R_MOD_ID] = 0x01090101; + s->regs[R_GQSPI_GPIO] = 1; + s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET; + s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET; + s->regs[R_QSPIDMA_DST_CTRL] = R_QSPIDMA_DST_CTRL_RESET; + s->regs[R_QSPIDMA_DST_I_MASK] = R_QSPIDMA_DST_I_MASK_RESET; + s->regs[R_QSPIDMA_DST_CTRL2] = R_QSPIDMA_DST_CTRL2_RESET; s->man_start_com_g = false; s->gqspi_irqline = 0; xlnx_zynqmp_qspips_update_ixr(s); diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 75fc94ce5d..d398a4e81c 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,7 +32,7 @@ typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) -#define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4) +#define XLNX_ZYNQMP_SPIPS_R_MAX (0x830 / 4) /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 -- cgit v1.2.3-55-g7522 From 81950da6819bbe77f38835724cc4643f19677554 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Thu, 30 Nov 2017 21:19:00 +0100 Subject: hmp-commands: Remove the deprecated usb_add and usb_del It's easy to use device_add and device_del as replacement instead. The usb_add and usb_del commands are deprecated since QEMU 2.10, and nobody complained that they are still needed, so let's get rid of them now to make the HMP interface a little bit less overloaded. Reviewed-by: Dr. David Alan Gilbert Signed-off-by: Thomas Huth Message-Id: <1512073140-17672-1-git-send-email-thuth@redhat.com> Signed-off-by: Dr. David Alan Gilbert --- hmp-commands.hx | 33 --------------------------------- hw/usb/bus.c | 22 ---------------------- include/hw/usb.h | 1 - include/sysemu/sysemu.h | 2 -- qemu-doc.texi | 8 -------- vl.c | 44 -------------------------------------------- 6 files changed, 110 deletions(-) (limited to 'include/hw') diff --git a/hmp-commands.hx b/hmp-commands.hx index 4afd57cf5f..6d5ebdf6ab 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -663,39 +663,6 @@ STEXI @item sum @var{addr} @var{size} @findex sum Compute the checksum of a memory region. -ETEXI - - { - .name = "usb_add", - .args_type = "devname:s", - .params = "device", - .help = "add USB device (e.g. 'host:bus.addr' or 'host:vendor_id:product_id')", - .cmd = hmp_usb_add, - }, - -STEXI -@item usb_add @var{devname} -@findex usb_add -Add the USB device @var{devname}. This command is deprecated, please -use @code{device_add} instead. For details of available devices see -@ref{usb_devices} -ETEXI - - { - .name = "usb_del", - .args_type = "devname:s", - .params = "device", - .help = "remove USB device 'bus.addr'", - .cmd = hmp_usb_del, - }, - -STEXI -@item usb_del @var{devname} -@findex usb_del -Remove the USB device @var{devname} from the QEMU virtual USB -hub. @var{devname} has the syntax @code{bus.addr}. Use the monitor -command @code{info usb} to see the devices you can remove. This -command is deprecated, please use @code{device_del} instead. ETEXI { diff --git a/hw/usb/bus.c b/hw/usb/bus.c index e56dc3348a..11f7720d71 100644 --- a/hw/usb/bus.c +++ b/hw/usb/bus.c @@ -559,28 +559,6 @@ int usb_device_detach(USBDevice *dev) return 0; } -int usb_device_delete_addr(int busnr, int addr) -{ - USBBus *bus; - USBPort *port; - USBDevice *dev; - - bus = usb_bus_find(busnr); - if (!bus) - return -1; - - QTAILQ_FOREACH(port, &bus->used, next) { - if (port->dev->addr == addr) - break; - } - if (!port) - return -1; - dev = port->dev; - - object_unparent(OBJECT(dev)); - return 0; -} - static const char *usb_speed(unsigned int speed) { static const char *txt[] = { diff --git a/include/hw/usb.h b/include/hw/usb.h index eb28655270..9dd9c6f0d9 100644 --- a/include/hw/usb.h +++ b/include/hw/usb.h @@ -549,7 +549,6 @@ void usb_claim_port(USBDevice *dev, Error **errp); void usb_release_port(USBDevice *dev); void usb_device_attach(USBDevice *dev, Error **errp); int usb_device_detach(USBDevice *dev); -int usb_device_delete_addr(int busnr, int addr); void usb_check_attach(USBDevice *dev, Error **errp); static inline USBBus *usb_bus_from_device(USBDevice *d) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index c083869fcf..31612caf10 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -166,8 +166,6 @@ extern Chardev *serial_hds[MAX_SERIAL_PORTS]; extern Chardev *parallel_hds[MAX_PARALLEL_PORTS]; -void hmp_usb_add(Monitor *mon, const QDict *qdict); -void hmp_usb_del(Monitor *mon, const QDict *qdict); void hmp_info_usb(Monitor *mon, const QDict *qdict); void add_boot_device_path(int32_t bootindex, DeviceState *dev, diff --git a/qemu-doc.texi b/qemu-doc.texi index db2351c746..ee206b8cba 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -2518,14 +2518,6 @@ The ``host_net_add'' command is replaced by the ``netdev_add'' command. The ``host_net_remove'' command is replaced by the ``netdev_del'' command. -@subsection usb_add (since 2.10.0) - -The ``usb_add'' command is replaced by the ``device_add'' command. - -@subsection usb_del (since 2.10.0) - -The ``usb_del'' command is replaced by the ``device_del'' command. - @section System emulator devices @subsection ivshmem (since 2.6.0) diff --git a/vl.c b/vl.c index 1ad1c04637..fc8bd9372f 100644 --- a/vl.c +++ b/vl.c @@ -1479,28 +1479,6 @@ done: return 0; } -static int usb_device_del(const char *devname) -{ - int bus_num, addr; - const char *p; - - if (strstart(devname, "host:", &p)) { - return -1; - } - - if (!machine_usb(current_machine)) { - return -1; - } - - p = strchr(devname, '.'); - if (!p) - return -1; - bus_num = strtoul(devname, NULL, 0); - addr = strtoul(p + 1, NULL, 0); - - return usb_device_delete_addr(bus_num, addr); -} - static int usb_parse(const char *cmdline) { int r; @@ -1511,28 +1489,6 @@ static int usb_parse(const char *cmdline) return r; } -void hmp_usb_add(Monitor *mon, const QDict *qdict) -{ - const char *devname = qdict_get_str(qdict, "devname"); - - error_report("usb_add is deprecated, please use device_add instead"); - - if (usb_device_add(devname) < 0) { - error_report("could not add USB device '%s'", devname); - } -} - -void hmp_usb_del(Monitor *mon, const QDict *qdict) -{ - const char *devname = qdict_get_str(qdict, "devname"); - - error_report("usb_del is deprecated, please use device_del instead"); - - if (usb_device_del(devname) < 0) { - error_report("could not delete USB device '%s'", devname); - } -} - /***********************************************************/ /* machine registration */ -- cgit v1.2.3-55-g7522 From 67ee0cefb09672247f502c0f208f2a0e3c566173 Mon Sep 17 00:00:00 2001 From: Cornelia Huck Date: Fri, 24 Nov 2017 16:26:51 +0100 Subject: s390x: introduce 2.12 compat machine Acked-by: Christian Borntraeger Reviewed-by: David Hildenbrand Signed-off-by: Cornelia Huck --- hw/s390x/s390-virtio-ccw.c | 17 ++++++++++++++++- include/hw/compat.h | 3 +++ 2 files changed, 19 insertions(+), 1 deletion(-) (limited to 'include/hw') diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 6a57f94197..a23b8aec9f 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -639,6 +639,9 @@ bool css_migration_enabled(void) } \ type_init(ccw_machine_register_##suffix) +#define CCW_COMPAT_2_11 \ + HW_COMPAT_2_11 + #define CCW_COMPAT_2_10 \ HW_COMPAT_2_10 @@ -716,14 +719,26 @@ bool css_migration_enabled(void) .value = "0",\ }, +static void ccw_machine_2_12_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_2_12_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(2_12, "2.12", true); + static void ccw_machine_2_11_instance_options(MachineState *machine) { + ccw_machine_2_12_instance_options(machine); } static void ccw_machine_2_11_class_options(MachineClass *mc) { + ccw_machine_2_12_class_options(mc); + SET_MACHINE_COMPAT(mc, CCW_COMPAT_2_11); } -DEFINE_CCW_MACHINE(2_11, "2.11", true); +DEFINE_CCW_MACHINE(2_11, "2.11", false); static void ccw_machine_2_10_instance_options(MachineState *machine) { diff --git a/include/hw/compat.h b/include/hw/compat.h index cf389b4e85..263de973a7 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,9 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H +#define HW_COMPAT_2_11 \ + /* empty */ + #define HW_COMPAT_2_10 \ {\ .driver = "virtio-mouse-device",\ -- cgit v1.2.3-55-g7522 From fc21eb6bd9f340e8d2083064e86cf09868e69872 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Thu, 30 Nov 2017 17:27:31 +0100 Subject: s390x/tcg: rip out dead tpi code It is broken and not even wired up. We'll add a new handler soon, but that will live somewhere else. Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand Message-Id: <20171130162744.25442-4-david@redhat.com> Signed-off-by: Cornelia Huck --- hw/s390x/css.c | 6 ------ include/hw/s390x/css.h | 1 - target/s390x/internal.h | 1 - target/s390x/ioinst.c | 26 -------------------------- 4 files changed, 34 deletions(-) (limited to 'include/hw') diff --git a/hw/s390x/css.c b/hw/s390x/css.c index f6b5c807cd..6bd0fedc78 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -1723,12 +1723,6 @@ void css_undo_stcrw(CRW *crw) QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); } -int css_do_tpi(IOIntCode *int_code, int lowcore) -{ - /* No pending interrupts for !KVM. */ - return 0; - } - int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, int rfmt, void *buf) { diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index ab6ebe66b5..0a14f76fea 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -248,7 +248,6 @@ int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len); void css_do_tsch_update_subch(SubchDev *sch); int css_do_stcrw(CRW *crw); void css_undo_stcrw(CRW *crw); -int css_do_tpi(IOIntCode *int_code, int lowcore); int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, int rfmt, void *buf); void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo); diff --git a/target/s390x/internal.h b/target/s390x/internal.h index db39d5bfac..603b0d7a7c 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -388,7 +388,6 @@ void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb); void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb); int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb); void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb); -int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb); void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2, uint32_t ipb); void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1); diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index 23962fbebc..1d6857c14d 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -647,32 +647,6 @@ void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb) } } -int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb) -{ - CPUS390XState *env = &cpu->env; - uint64_t addr; - int lowcore; - IOIntCode int_code; - hwaddr len; - int ret; - uint8_t ar; - - trace_ioinst("tpi"); - addr = decode_basedisp_s(env, ipb, &ar); - if (addr & 3) { - program_interrupt(env, PGM_SPECIFICATION, 4); - return -EIO; - } - - lowcore = addr ? 0 : 1; - len = lowcore ? 8 /* two words */ : 12 /* three words */; - ret = css_do_tpi(&int_code, lowcore); - if (ret == 1) { - s390_cpu_virt_mem_write(cpu, lowcore ? 184 : addr, ar, &int_code, len); - } - return ret; -} - #define SCHM_REG1_RES(_reg) (_reg & 0x000000000ffffffc) #define SCHM_REG1_MBK(_reg) ((_reg & 0x00000000f0000000) >> 28) #define SCHM_REG1_UPD(_reg) ((_reg & 0x0000000000000002) >> 1) -- cgit v1.2.3-55-g7522 From 99577c492fb2916165ed9bc215f058877f0a4106 Mon Sep 17 00:00:00 2001 From: Halil Pasic Date: Wed, 6 Dec 2017 15:44:37 +0100 Subject: s390x/css: unrestrict cssids The default css 0xfe is currently restricted to virtual subchannel devices. The hope when the decision was made was, that non-virtual subchannel devices will come around when guest can exploit multiple channel subsystems. Since the guests generally don't do, the pain of the partitioned (cssid) namespace outweighs the gain. Let us remove the corresponding restrictions (virtual devices can be put only in 0xfe and non-virtual devices in any css except the 0xfe -- while s390-squash-mcss then remaps everything to cssid 0). At the same time, change our schema for generating css bus ids to put both virtual and non-virtual devices into the default css (spilling over into other css images, if needed). The intention is to deprecate s390-squash-mcss. With this change devices without a specified devno won't end up hidden to guests not supporting multiple channel subsystems, unless this can not be avoided (default css full). Let us also advertise the changes to the management software (so it can tell are cssids unrestricted or restricted). The adverse effect of getting rid of the restriction on migration should not be too severe. Vfio-ccw devices are not live-migratable yet, and for virtual devices using the extra freedom would only make sense with the aforementioned guest support in place. The auto-generated bus ids are affected by both changes. We hope to not encounter any auto-generated bus ids in production as Libvirt is always explicit about the bus id. Since 8ed179c937 ("s390x/css: catch section mismatch on load", 2017-05-18) the worst that can happen because the same device ended up having a different bus id is a cleanly failed migration. I find it hard to reason about the impact of changed auto-generated bus ids on migration for command line users as I don't know which rules is such an user supposed to follow. Another pain-point is down- or upgrade of QEMU for command line users. The old way and the new way of doing vfio-ccw are mutually incompatible. Libvirt is only going to support the new way, so for libvirt users, the possible problems at QEMU downgrade are the following. If a domain contains virtual devices placed into a css different than 0xfe the domain will refuse to start with a QEMU not having this patch. Putting devices into a css different that 0xfe however won't make much sense in the near future (guest support). Libvirt will refuse to do vfio-ccw with a QEMU not having this patch. This is business as usual. Signed-off-by: Halil Pasic Acked-by: Christian Borntraeger Reviewed-by: Dong Jia Shi Message-Id: <20171206144438.28908-2-pasic@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck --- hw/s390x/3270-ccw.c | 2 +- hw/s390x/css-bridge.c | 11 +++++++++++ hw/s390x/css.c | 28 ++++------------------------ hw/s390x/s390-ccw.c | 2 +- hw/s390x/s390-virtio-ccw.c | 1 - hw/s390x/virtio-ccw.c | 2 +- include/hw/s390x/css.h | 12 ++++-------- 7 files changed, 22 insertions(+), 36 deletions(-) (limited to 'include/hw') diff --git a/hw/s390x/3270-ccw.c b/hw/s390x/3270-ccw.c index 081e3ef6f4..3af13ea027 100644 --- a/hw/s390x/3270-ccw.c +++ b/hw/s390x/3270-ccw.c @@ -104,7 +104,7 @@ static void emulated_ccw_3270_realize(DeviceState *ds, Error **errp) SubchDev *sch; Error *err = NULL; - sch = css_create_sch(cdev->devno, true, cbus->squash_mcss, errp); + sch = css_create_sch(cdev->devno, cbus->squash_mcss, errp); if (!sch) { return; } diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index c4a9735d71..a91a237f37 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -123,6 +123,11 @@ static Property virtual_css_bridge_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static bool prop_get_true(Object *obj, Error **errp) +{ + return true; +} + static void virtual_css_bridge_class_init(ObjectClass *klass, void *data) { HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); @@ -131,6 +136,12 @@ static void virtual_css_bridge_class_init(ObjectClass *klass, void *data) hc->unplug = ccw_device_unplug; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->props = virtual_css_bridge_properties; + object_class_property_add_bool(klass, "cssid-unrestricted", + prop_get_true, NULL, NULL); + object_class_property_set_description(klass, "cssid-unrestricted", + "A css device can use any cssid, regardless whether virtual" + " or not (read only, always true)", + NULL); } static const TypeInfo virtual_css_bridge_info = { diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 6bd0fedc78..f071e1394b 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -2364,21 +2364,11 @@ const PropertyInfo css_devid_ro_propinfo = { .get = get_css_devid, }; -SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, - Error **errp) +SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp) { uint16_t schid = 0; SubchDev *sch; - if (bus_id.valid) { - if (is_virtual != (bus_id.cssid == VIRTUAL_CSSID)) { - error_setg(errp, "cssid %hhx not valid for %s devices", - bus_id.cssid, - (is_virtual ? "virtual" : "non-virtual")); - return NULL; - } - } - if (bus_id.valid) { if (squash_mcss) { bus_id.cssid = channel_subsys.default_cssid; @@ -2390,19 +2380,8 @@ SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, bus_id.devid, &schid, errp)) { return NULL; } - } else if (squash_mcss || is_virtual) { - bus_id.cssid = channel_subsys.default_cssid; - - if (!css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, - &bus_id.devid, &schid, errp)) { - return NULL; - } } else { - for (bus_id.cssid = 0; bus_id.cssid < MAX_CSSID; ++bus_id.cssid) { - if (bus_id.cssid == VIRTUAL_CSSID) { - continue; - } - + for (bus_id.cssid = channel_subsys.default_cssid;;) { if (!channel_subsys.css[bus_id.cssid]) { css_create_css_image(bus_id.cssid, false); } @@ -2412,7 +2391,8 @@ SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, NULL)) { break; } - if (bus_id.cssid == MAX_CSSID) { + bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID; + if (bus_id.cssid == channel_subsys.default_cssid) { error_setg(errp, "Virtual channel subsystem is full!"); return NULL; } diff --git a/hw/s390x/s390-ccw.c b/hw/s390x/s390-ccw.c index 0ef232ec27..4a9d4d2534 100644 --- a/hw/s390x/s390-ccw.c +++ b/hw/s390x/s390-ccw.c @@ -77,7 +77,7 @@ static void s390_ccw_realize(S390CCWDevice *cdev, char *sysfsdev, Error **errp) goto out_err_propagate; } - sch = css_create_sch(ccw_dev->devno, false, cbus->squash_mcss, &err); + sch = css_create_sch(ccw_dev->devno, cbus->squash_mcss, &err); if (!sch) { goto out_mdevid_free; } diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index a23b8aec9f..5d4aaaf158 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -302,7 +302,6 @@ static void ccw_init(MachineState *machine) /* * Non mcss-e enabled guests only see the devices from the default * css, which is determined by the value of the squash_mcss property. - * Note: we must not squash non virtual devices to css 0xFE. */ if (css_bus->squash_mcss) { ret = css_create_css_image(0, true); diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 184515ce94..3dd902a664 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -701,7 +701,7 @@ static void virtio_ccw_device_realize(VirtioCcwDevice *dev, Error **errp) SubchDev *sch; Error *err = NULL; - sch = css_create_sch(ccw_dev->devno, true, cbus->squash_mcss, errp); + sch = css_create_sch(ccw_dev->devno, cbus->squash_mcss, errp); if (!sch) { return; } diff --git a/include/hw/s390x/css.h b/include/hw/s390x/css.h index 0a14f76fea..35facb47d2 100644 --- a/include/hw/s390x/css.h +++ b/include/hw/s390x/css.h @@ -271,12 +271,9 @@ extern const PropertyInfo css_devid_ro_propinfo; * default css image for it. * If @p bus_id is valid, and @p squash_mcss is false, verify that it is * not already in use, and find a free devno for it. - * If @p bus_id is not valid, and if either @p squash_mcss or @p is_virtual - * is true, find a free subchannel id and device number across all - * subchannel sets from the default css image. - * If @p bus_id is not valid, and if both @p squash_mcss and @p is_virtual - * are false, find a non-full css image and find a free subchannel id and - * device number across all subchannel sets from it. + * If @p bus_id is not valid find a free subchannel id and device number + * across all subchannel sets and all css images starting from the default + * css image. * * If either of the former actions succeed, allocate a subchannel structure, * initialise it with the bus id, subchannel id and device number, register @@ -285,8 +282,7 @@ extern const PropertyInfo css_devid_ro_propinfo; * The caller becomes owner of the returned subchannel structure and * is responsible for unregistering and freeing it. */ -SubchDev *css_create_sch(CssDevId bus_id, bool is_virtual, bool squash_mcss, - Error **errp); +SubchDev *css_create_sch(CssDevId bus_id, bool squash_mcss, Error **errp); /** Turn on css migration */ void css_register_vmstate(void); -- cgit v1.2.3-55-g7522 From 2b6154120cbd7f5514cefd3c6084d39922d26d88 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 13 Nov 2017 16:50:40 +1100 Subject: spapr: Add pseries-2.12 machine type While we're at it fix a couple of small errors in the 2.11 and 2.10 models (they didn't have any real effect, but don't quite match the template). Signed-off-by: David Gibson --- hw/ppc/spapr.c | 26 +++++++++++++++++++++++--- include/hw/compat.h | 2 ++ 2 files changed, 25 insertions(+), 3 deletions(-) (limited to 'include/hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 1ac7eb0f8c..8881f2f1e8 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3713,28 +3713,48 @@ static const TypeInfo spapr_machine_info = { } \ type_init(spapr_machine_register_##suffix) +/* + * pseries-2.12 + */ +static void spapr_machine_2_12_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_2_12_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(2_12, "2.12", true); + /* * pseries-2.11 */ +#define SPAPR_COMPAT_2_11 \ + HW_COMPAT_2_11 + static void spapr_machine_2_11_instance_options(MachineState *machine) { + spapr_machine_2_12_instance_options(machine); } static void spapr_machine_2_11_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_2_12_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11); } -DEFINE_SPAPR_MACHINE(2_11, "2.11", true); +DEFINE_SPAPR_MACHINE(2_11, "2.11", false); /* * pseries-2.10 */ #define SPAPR_COMPAT_2_10 \ - HW_COMPAT_2_10 \ + HW_COMPAT_2_10 static void spapr_machine_2_10_instance_options(MachineState *machine) { + spapr_machine_2_11_instance_options(machine); } static void spapr_machine_2_10_class_options(MachineClass *mc) diff --git a/include/hw/compat.h b/include/hw/compat.h index cf389b4e85..0d2a6ac468 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,8 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H +#define HW_COMPAT_2_11 + #define HW_COMPAT_2_10 \ {\ .driver = "virtio-mouse-device",\ -- cgit v1.2.3-55-g7522 From 94ad93bd976841c26af75322301f5aad925114d6 Mon Sep 17 00:00:00 2001 From: Greg Kurz Date: Mon, 20 Nov 2017 10:19:54 +0100 Subject: spapr_cpu_core: instantiate CPUs separately The current code assumes that only the CPU core object holds a reference on each individual CPU object, and happily frees their allocated memory when the core is unrealized. This is dangerous as some other code can legitimely keep a pointer to a CPU if it calls object_ref(), but it would end up with a dangling pointer. Let's allocate all CPUs with object_new() and let QOM free them when their reference count reaches zero. This greatly simplify the code as we don't have to fiddle with the instance size anymore. Signed-off-by: Greg Kurz Acked-by: Igor Mammedov Signed-off-by: David Gibson --- hw/ppc/spapr.c | 11 +++-------- hw/ppc/spapr_cpu_core.c | 19 +++++++------------ include/hw/ppc/spapr_cpu_core.h | 2 +- 3 files changed, 11 insertions(+), 21 deletions(-) (limited to 'include/hw') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 8881f2f1e8..f1b96a4e92 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3180,12 +3180,10 @@ void spapr_core_release(DeviceState *dev) if (smc->pre_2_10_has_unused_icps) { sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); - sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); - size_t size = object_type_get_instance_size(scc->cpu_type); int i; for (i = 0; i < cc->nr_threads; i++) { - CPUState *cs = CPU(sc->threads + i * size); + CPUState *cs = CPU(sc->threads[i]); pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); } @@ -3231,7 +3229,7 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); CPUCore *cc = CPU_CORE(dev); - CPUState *cs = CPU(core->threads); + CPUState *cs = CPU(core->threads[0]); sPAPRDRConnector *drc; Error *local_err = NULL; int smt = kvmppc_smt_threads(); @@ -3276,15 +3274,12 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, core_slot->cpu = OBJECT(dev); if (smc->pre_2_10_has_unused_icps) { - sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); - size_t size = object_type_get_instance_size(scc->cpu_type); int i; for (i = 0; i < cc->nr_threads; i++) { sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); - void *obj = sc->threads + i * size; - cs = CPU(obj); + cs = CPU(sc->threads[i]); pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); } } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 3a4c174012..588f9b4571 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -79,13 +79,11 @@ const char *spapr_get_cpu_core_type(const char *cpu_type) static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) { sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); - sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); - size_t size = object_type_get_instance_size(scc->cpu_type); CPUCore *cc = CPU_CORE(dev); int i; for (i = 0; i < cc->nr_threads; i++) { - void *obj = sc->threads + i * size; + Object *obj = OBJECT(sc->threads[i]); DeviceState *dev = DEVICE(obj); CPUState *cs = CPU(dev); PowerPCCPU *cpu = POWERPC_CPU(cs); @@ -146,9 +144,8 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); CPUCore *cc = CPU_CORE(OBJECT(dev)); - size_t size; Error *local_err = NULL; - void *obj; + Object *obj; int i, j; if (!spapr) { @@ -156,18 +153,16 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) return; } - size = object_type_get_instance_size(scc->cpu_type); - sc->threads = g_malloc0(size * cc->nr_threads); + sc->threads = g_new(PowerPCCPU *, cc->nr_threads); for (i = 0; i < cc->nr_threads; i++) { char id[32]; CPUState *cs; PowerPCCPU *cpu; - obj = sc->threads + i * size; + obj = object_new(scc->cpu_type); - object_initialize(obj, size, scc->cpu_type); cs = CPU(obj); - cpu = POWERPC_CPU(cs); + cpu = sc->threads[i] = POWERPC_CPU(obj); cs->cpu_index = cc->core_id + i; cpu->vcpu_id = (cc->core_id * spapr->vsmt / smp_threads) + i; if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->vcpu_id)) { @@ -192,7 +187,7 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) } for (j = 0; j < cc->nr_threads; j++) { - obj = sc->threads + j * size; + obj = OBJECT(sc->threads[j]); spapr_cpu_core_realize_child(obj, spapr, &local_err); if (local_err) { @@ -203,7 +198,7 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) err: while (--i >= 0) { - obj = sc->threads + i * size; + obj = OBJECT(sc->threads[i]); object_unparent(obj); } g_free(sc->threads); diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h index f2d48d6a67..1129f344aa 100644 --- a/include/hw/ppc/spapr_cpu_core.h +++ b/include/hw/ppc/spapr_cpu_core.h @@ -28,7 +28,7 @@ typedef struct sPAPRCPUCore { CPUCore parent_obj; /*< public >*/ - void *threads; + PowerPCCPU **threads; int node_id; } sPAPRCPUCore; -- cgit v1.2.3-55-g7522 From 4f7a47beebd6d37861d08c81941be1b33a0ae627 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 1 Dec 2017 17:06:00 +0100 Subject: ppc/xics: introduce an icp_create() helper The sPAPR and the PowerNV core objects create the interrupt presenter object of the CPUs in a very similar way. Let's provide a common routine in which we use the presenter 'type' as a child identifier. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/xics.c | 21 +++++++++++++++++++++ hw/ppc/pnv_core.c | 10 +--------- hw/ppc/spapr_cpu_core.c | 13 ++----------- include/hw/ppc/xics.h | 3 +++ 4 files changed, 27 insertions(+), 20 deletions(-) (limited to 'include/hw') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index a1cc0e420c..bfc6b5bb23 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -384,6 +384,27 @@ static const TypeInfo icp_info = { .class_size = sizeof(ICPStateClass), }; +Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp) +{ + Error *local_err = NULL; + Object *obj; + + obj = object_new(type); + object_property_add_child(cpu, type, obj, &error_abort); + object_unref(obj); + object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), + &error_abort); + object_property_add_const_link(obj, ICP_PROP_CPU, cpu, &error_abort); + object_property_set_bool(obj, true, "realized", &local_err); + if (local_err) { + object_unparent(obj); + error_propagate(errp, local_err); + obj = NULL; + } + + return obj; +} + /* * ICS: Source layer */ diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 82ff440b33..8d966e0802 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -126,7 +126,6 @@ static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp) Error *local_err = NULL; CPUState *cs = CPU(child); PowerPCCPU *cpu = POWERPC_CPU(cs); - Object *obj; object_property_set_bool(child, true, "realized", &local_err); if (local_err) { @@ -134,13 +133,7 @@ static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp) return; } - obj = object_new(TYPE_PNV_ICP); - object_property_add_child(child, "icp", obj, NULL); - object_unref(obj); - object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(xi), - &error_abort); - object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); - object_property_set_bool(obj, true, "realized", &local_err); + icp_create(child, TYPE_PNV_ICP, xi, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -148,7 +141,6 @@ static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp) powernv_cpu_init(cpu, &local_err); if (local_err) { - object_unparent(obj); error_propagate(errp, local_err); return; } diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 1ea0e295dd..70e757f808 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -110,7 +110,6 @@ static void spapr_cpu_core_realize_child(Object *child, Error *local_err = NULL; CPUState *cs = CPU(child); PowerPCCPU *cpu = POWERPC_CPU(cs); - Object *obj; object_property_set_bool(child, true, "realized", &local_err); if (local_err) { @@ -122,21 +121,13 @@ static void spapr_cpu_core_realize_child(Object *child, goto error; } - obj = object_new(spapr->icp_type); - object_property_add_child(child, "icp", obj, &error_abort); - object_unref(obj); - object_property_add_const_link(obj, ICP_PROP_XICS, OBJECT(spapr), - &error_abort); - object_property_add_const_link(obj, ICP_PROP_CPU, child, &error_abort); - object_property_set_bool(obj, true, "realized", &local_err); + icp_create(child, spapr->icp_type, XICS_FABRIC(spapr), &local_err); if (local_err) { - goto free_icp; + goto error; } return; -free_icp: - object_unparent(obj); error: error_propagate(errp, local_err); } diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 2df99be111..2ba8b12208 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -212,4 +212,7 @@ typedef struct sPAPRMachineState sPAPRMachineState; int xics_kvm_init(sPAPRMachineState *spapr, Error **errp); void xics_spapr_init(sPAPRMachineState *spapr); +Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, + Error **errp); + #endif /* XICS_H */ -- cgit v1.2.3-55-g7522 From 60c6823b9bce6789f1ad95bca233fc490161b279 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 1 Dec 2017 17:06:02 +0100 Subject: spapr: move the IRQ allocation routines under the machine Also change the prototype to use a sPAPRMachineState and prefix them with spapr_irq_. It will let us synchronise the IRQ allocation with the XIVE interrupt mode when available. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Reviewed-by: Greg Kurz Signed-off-by: David Gibson --- hw/intc/trace-events | 4 -- hw/intc/xics_spapr.c | 114 ------------------------------------------------- hw/ppc/spapr.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_events.c | 4 +- hw/ppc/spapr_pci.c | 8 ++-- hw/ppc/spapr_vio.c | 2 +- hw/ppc/trace-events | 4 ++ include/hw/ppc/spapr.h | 6 +++ include/hw/ppc/xics.h | 4 -- 9 files changed, 131 insertions(+), 129 deletions(-) (limited to 'include/hw') diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b298fac7c6..7077aaaee6 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -64,10 +64,6 @@ xics_ics_simple_set_irq_lsi(int srcno, int nr) "set_irq_lsi: srcno %d [irq 0x%x] xics_ics_simple_write_xive(int nr, int srcno, int server, uint8_t priority) "ics_write_xive: irq 0x%x [src %d] server 0x%x prio 0x%x" xics_ics_simple_reject(int nr, int srcno) "reject irq 0x%x [src %d]" xics_ics_simple_eoi(int nr) "ics_eoi: irq 0x%x" -xics_alloc(int irq) "irq %d" -xics_alloc_block(int first, int num, bool lsi, int align) "first irq %d, %d irqs, lsi=%d, alignnum %d" -xics_ics_free(int src, int irq, int num) "Source#%d, first irq %d, %d irqs" -xics_ics_free_warn(int src, int irq) "Source#%d, irq %d is already free" # hw/intc/s390_flic_kvm.c flic_create_device(int err) "flic: create device failed %d" diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index e8c0a1b3e9..5a0967caf4 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -245,120 +245,6 @@ void xics_spapr_init(sPAPRMachineState *spapr) spapr_register_hypercall(H_IPOLL, h_ipoll); } -#define ICS_IRQ_FREE(ics, srcno) \ - (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) - -static int ics_find_free_block(ICSState *ics, int num, int alignnum) -{ - int first, i; - - for (first = 0; first < ics->nr_irqs; first += alignnum) { - if (num > (ics->nr_irqs - first)) { - return -1; - } - for (i = first; i < first + num; ++i) { - if (!ICS_IRQ_FREE(ics, i)) { - break; - } - } - if (i == (first + num)) { - return first; - } - } - - return -1; -} - -int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp) -{ - int irq; - - if (!ics) { - return -1; - } - if (irq_hint) { - if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { - error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); - return -1; - } - irq = irq_hint; - } else { - irq = ics_find_free_block(ics, 1, 1); - if (irq < 0) { - error_setg(errp, "can't allocate IRQ: no IRQ left"); - return -1; - } - irq += ics->offset; - } - - ics_set_irq_type(ics, irq - ics->offset, lsi); - trace_xics_alloc(irq); - - return irq; -} - -/* - * Allocate block of consecutive IRQs, and return the number of the first IRQ in - * the block. If align==true, aligns the first IRQ number to num. - */ -int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, - bool align, Error **errp) -{ - int i, first = -1; - - if (!ics) { - return -1; - } - - /* - * MSIMesage::data is used for storing VIRQ so - * it has to be aligned to num to support multiple - * MSI vectors. MSI-X is not affected by this. - * The hint is used for the first IRQ, the rest should - * be allocated continuously. - */ - if (align) { - assert((num == 1) || (num == 2) || (num == 4) || - (num == 8) || (num == 16) || (num == 32)); - first = ics_find_free_block(ics, num, num); - } else { - first = ics_find_free_block(ics, num, 1); - } - if (first < 0) { - error_setg(errp, "can't find a free %d-IRQ block", num); - return -1; - } - - for (i = first; i < first + num; ++i) { - ics_set_irq_type(ics, i, lsi); - } - first += ics->offset; - - trace_xics_alloc_block(first, num, lsi, align); - - return first; -} - -static void ics_free(ICSState *ics, int srcno, int num) -{ - int i; - - for (i = srcno; i < srcno + num; ++i) { - if (ICS_IRQ_FREE(ics, i)) { - trace_xics_ics_free_warn(0, i + ics->offset); - } - memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); - } -} - -void spapr_ics_free(ICSState *ics, int irq, int num) -{ - if (ics_valid_irq(ics, irq)) { - trace_xics_ics_free(0, irq, num); - ics_free(ics, irq - ics->offset, num); - } -} - void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle) { uint32_t interrupt_server_ranges_prop[] = { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f1b96a4e92..53c2c58a25 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3558,6 +3558,120 @@ static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) return cpu ? ICP(cpu->intc) : NULL; } +#define ICS_IRQ_FREE(ics, srcno) \ + (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) + +static int ics_find_free_block(ICSState *ics, int num, int alignnum) +{ + int first, i; + + for (first = 0; first < ics->nr_irqs; first += alignnum) { + if (num > (ics->nr_irqs - first)) { + return -1; + } + for (i = first; i < first + num; ++i) { + if (!ICS_IRQ_FREE(ics, i)) { + break; + } + } + if (i == (first + num)) { + return first; + } + } + + return -1; +} + +int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, + Error **errp) +{ + ICSState *ics = spapr->ics; + int irq; + + if (!ics) { + return -1; + } + if (irq_hint) { + if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { + error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint); + return -1; + } + irq = irq_hint; + } else { + irq = ics_find_free_block(ics, 1, 1); + if (irq < 0) { + error_setg(errp, "can't allocate IRQ: no IRQ left"); + return -1; + } + irq += ics->offset; + } + + ics_set_irq_type(ics, irq - ics->offset, lsi); + trace_spapr_irq_alloc(irq); + + return irq; +} + +/* + * Allocate block of consecutive IRQs, and return the number of the first IRQ in + * the block. If align==true, aligns the first IRQ number to num. + */ +int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, + bool align, Error **errp) +{ + ICSState *ics = spapr->ics; + int i, first = -1; + + if (!ics) { + return -1; + } + + /* + * MSIMesage::data is used for storing VIRQ so + * it has to be aligned to num to support multiple + * MSI vectors. MSI-X is not affected by this. + * The hint is used for the first IRQ, the rest should + * be allocated continuously. + */ + if (align) { + assert((num == 1) || (num == 2) || (num == 4) || + (num == 8) || (num == 16) || (num == 32)); + first = ics_find_free_block(ics, num, num); + } else { + first = ics_find_free_block(ics, num, 1); + } + if (first < 0) { + error_setg(errp, "can't find a free %d-IRQ block", num); + return -1; + } + + for (i = first; i < first + num; ++i) { + ics_set_irq_type(ics, i, lsi); + } + first += ics->offset; + + trace_spapr_irq_alloc_block(first, num, lsi, align); + + return first; +} + +void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) +{ + ICSState *ics = spapr->ics; + int srcno = irq - ics->offset; + int i; + + if (ics_valid_irq(ics, irq)) { + trace_spapr_irq_free(0, irq, num); + for (i = srcno; i < srcno + num; ++i) { + if (ICS_IRQ_FREE(ics, i)) { + trace_spapr_irq_free_warn(0, i + ics->offset); + } + memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); + } + } +} + static void spapr_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index e377fc7dde..cead596f3e 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -718,7 +718,7 @@ void spapr_events_init(sPAPRMachineState *spapr) spapr->event_sources = spapr_event_sources_new(); spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_EPOW, - spapr_ics_alloc(spapr->ics, 0, false, + spapr_irq_alloc(spapr, 0, false, &error_fatal)); /* NOTE: if machine supports modern/dedicated hotplug event source, @@ -731,7 +731,7 @@ void spapr_events_init(sPAPRMachineState *spapr) */ if (spapr->use_hotplug_event_source) { spapr_event_sources_register(spapr->event_sources, EVENT_CLASS_HOT_PLUG, - spapr_ics_alloc(spapr->ics, 0, false, + spapr_irq_alloc(spapr, 0, false, &error_fatal)); } diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 5a3122a9f9..e0ef77a480 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -314,7 +314,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, return; } - spapr_ics_free(spapr->ics, msi->first_irq, msi->num); + spapr_irq_free(spapr, msi->first_irq, msi->num); if (msi_present(pdev)) { spapr_msi_setmsg(pdev, 0, false, 0, 0); } @@ -352,7 +352,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, } /* Allocate MSIs */ - irq = spapr_ics_alloc_block(spapr->ics, req_num, false, + irq = spapr_irq_alloc_block(spapr, req_num, false, ret_intr_type == RTAS_TYPE_MSI, &err); if (err) { error_reportf_err(err, "Can't allocate MSIs for device %x: ", @@ -363,7 +363,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr, /* Release previous MSIs */ if (msi) { - spapr_ics_free(spapr->ics, msi->first_irq, msi->num); + spapr_irq_free(spapr, msi->first_irq, msi->num); g_hash_table_remove(phb->msi, &config_addr); } @@ -1675,7 +1675,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) uint32_t irq; Error *local_err = NULL; - irq = spapr_ics_alloc_block(spapr->ics, 1, true, false, &local_err); + irq = spapr_irq_alloc_block(spapr, 1, true, false, &local_err); if (local_err) { error_propagate(errp, local_err); error_prepend(errp, "can't allocate LSIs: "); diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index ea3bc8bd9e..bb7ed2c537 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -454,7 +454,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp) dev->qdev.id = id; } - dev->irq = spapr_ics_alloc(spapr->ics, dev->irq, false, &local_err); + dev->irq = spapr_irq_alloc(spapr, dev->irq, false, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 4a6a6490fa..b7c3e64b5e 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -12,6 +12,10 @@ spapr_pci_msi_retry(unsigned config_addr, unsigned req_num, unsigned max_irqs) " # hw/ppc/spapr.c spapr_cas_failed(unsigned long n) "DT diff buffer is too small: %ld bytes" spapr_cas_continue(unsigned long n) "Copy changes to the guest: %ld bytes" +spapr_irq_alloc(int irq) "irq %d" +spapr_irq_alloc_block(int first, int num, bool lsi, int align) "first irq %d, %d irqs, lsi=%d, alignnum %d" +spapr_irq_free(int src, int irq, int num) "Source#%d, first irq %d, %d irqs" +spapr_irq_free_warn(int src, int irq) "Source#%d, irq %d is already free" # hw/ppc/spapr_hcall.c spapr_cas_pvr_try(uint32_t pvr) "0x%x" diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 9d21ca9bde..895f48471e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -707,4 +707,10 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); int spapr_vcpu_id(PowerPCCPU *cpu); PowerPCCPU *spapr_find_cpu(int vcpu_id); +int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, + Error **errp); +int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, + bool align, Error **errp); +void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); + #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 2ba8b12208..0b67abbbb9 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -181,10 +181,6 @@ typedef struct XICSFabricClass { #define XICS_IRQS_SPAPR 1024 -int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp); -int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align, - Error **errp); -void spapr_ics_free(ICSState *ics, int irq, int num); void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); qemu_irq xics_get_qirq(XICSFabric *xi, int irq); -- cgit v1.2.3-55-g7522 From 7718375584a0214c951668a6e92896aaed88b289 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 1 Dec 2017 17:06:04 +0100 Subject: spapr: introduce a spapr_qirq() helper xics_get_qirq() is only used by the sPAPR machine. Let's move it there and change its name to reflect its scope. It will be useful for XIVE support which will use its own set of qirqs. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/intc/xics.c | 12 ------------ hw/ppc/spapr.c | 11 +++++++++++ hw/ppc/spapr_events.c | 12 +++++------- hw/ppc/spapr_pci.c | 2 +- include/hw/pci-host/spapr.h | 2 +- include/hw/ppc/spapr.h | 1 + include/hw/ppc/spapr_vio.h | 2 +- include/hw/ppc/xics.h | 1 - 8 files changed, 20 insertions(+), 23 deletions(-) (limited to 'include/hw') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 700f6baa13..e73e623e3b 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -713,18 +713,6 @@ static const TypeInfo xics_fabric_info = { /* * Exported functions */ -qemu_irq xics_get_qirq(XICSFabric *xi, int irq) -{ - XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); - ICSState *ics = xic->ics_get(xi, irq); - - if (ics) { - return ics->qirqs[irq - ics->offset]; - } - - return NULL; -} - ICPState *xics_icp_get(XICSFabric *xi, int server) { XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 02cc7ffd4d..8a6a59f098 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3680,6 +3680,17 @@ void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num) } } +qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq) +{ + ICSState *ics = spapr->ics; + + if (ics_valid_irq(ics, irq)) { + return ics->qirqs[irq - ics->offset]; + } + + return NULL; +} + static void spapr_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index cead596f3e..7dc87fc7bd 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -472,9 +472,8 @@ static void spapr_powerdown_req(Notifier *n, void *opaque) rtas_event_log_queue(spapr, entry); - qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), - rtas_event_log_to_irq(spapr, - RTAS_LOG_TYPE_EPOW))); + qemu_irq_pulse(spapr_qirq(spapr, + rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_EPOW))); } static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action, @@ -556,9 +555,8 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action, rtas_event_log_queue(spapr, entry); - qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), - rtas_event_log_to_irq(spapr, - RTAS_LOG_TYPE_HOTPLUG))); + qemu_irq_pulse(spapr_qirq(spapr, + rtas_event_log_to_irq(spapr, RTAS_LOG_TYPE_HOTPLUG))); } void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc) @@ -678,7 +676,7 @@ static void check_exception(PowerPCCPU *cpu, sPAPRMachineState *spapr, spapr_event_sources_get_source(spapr->event_sources, i); g_assert(source->enabled); - qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), source->irq)); + qemu_irq_pulse(spapr_qirq(spapr, source->irq)); } } diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index e0ef77a480..39134f0ef0 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -723,7 +723,7 @@ static void spapr_msi_write(void *opaque, hwaddr addr, trace_spapr_pci_msi_write(addr, data, irq); - qemu_irq_pulse(xics_get_qirq(XICS_FABRIC(spapr), irq)); + qemu_irq_pulse(spapr_qirq(spapr, irq)); } static const MemoryRegionOps spapr_msi_ops = { diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h index 38470b2f0e..0fae4fc6a4 100644 --- a/include/hw/pci-host/spapr.h +++ b/include/hw/pci-host/spapr.h @@ -108,7 +108,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin) { sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - return xics_get_qirq(XICS_FABRIC(spapr), phb->lsi_table[pin].irq); + return spapr_qirq(spapr, phb->lsi_table[pin].irq); } PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 895f48471e..6b8e04c787 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -712,5 +712,6 @@ int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi, int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi, bool align, Error **errp); void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num); +qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq); #endif /* HW_SPAPR_H */ diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 2e9685a5d9..e8b006d18f 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -87,7 +87,7 @@ static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev) { sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); - return xics_get_qirq(XICS_FABRIC(spapr), dev->irq); + return spapr_qirq(spapr, dev->irq); } static inline bool spapr_vio_dma_valid(VIOsPAPRDevice *dev, uint64_t taddr, diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 0b67abbbb9..6cebff47a7 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -183,7 +183,6 @@ typedef struct XICSFabricClass { void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle); -qemu_irq xics_get_qirq(XICSFabric *xi, int irq); ICPState *xics_icp_get(XICSFabric *xi, int server); /* Internal XICS interfaces */ -- cgit v1.2.3-55-g7522 From bb2d8ab6369abc8e90a9f7e2e8f154fea752bdaf Mon Sep 17 00:00:00 2001 From: Greg Kurz Date: Wed, 6 Dec 2017 09:13:16 +0100 Subject: spapr: fix LSI interrupt specifiers in the device tree LoPAPR 1.1 B.6.9.1.2 describes the "#interrupt-cells" property of the PowerPC External Interrupt Source Controller node as follows: “#interrupt-cells” Standard property name to define the number of cells in an interrupt- specifier within an interrupt domain. prop-encoded-array: An integer, encoded as with encode-int, that denotes the number of cells required to represent an interrupt specifier in its child nodes. The value of this property for the PowerPC External Interrupt option shall be 2. Thus all interrupt specifiers (as used in the standard “interrupts” property) shall consist of two cells, each containing an integer encoded as with encode-int. The first integer represents the interrupt number the second integer is the trigger code: 0 for edge triggered, 1 for level triggered. This patch fixes the interrupt specifiers in the "interrupt-map" property of the PHB node, that were setting the second cell to 8 (confusion with IRQ_TYPE_LEVEL_LOW ?) instead of 1. VIO devices and RTAS event sources use the same format for interrupt specifiers: while here, we introduce a common helper to handle the encoding details. Signed-off-by: Greg Kurz Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater -- v3: - reference public LoPAPR instead of internal PAPR+ in changelog - change helper name to spapr_dt_xics_irq() v2: - drop the erroneous changes to the "interrupts" prop in PCI device nodes - introduce a common helper to encode interrupt specifiers Signed-off-by: David Gibson --- hw/ppc/spapr_events.c | 3 +-- hw/ppc/spapr_pci.c | 3 +-- hw/ppc/spapr_vio.c | 3 ++- include/hw/ppc/spapr.h | 10 ++++++++++ 4 files changed, 14 insertions(+), 5 deletions(-) (limited to 'include/hw') diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index 7dc87fc7bd..c7a64e6b8d 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -282,8 +282,7 @@ void spapr_dt_events(sPAPRMachineState *spapr, void *fdt) continue; } - interrupts[0] = cpu_to_be32(source->irq); - interrupts[1] = 0; + spapr_dt_xics_irq(interrupts, source->irq, false); _FDT(node_offset = fdt_add_subnode(fdt, event_sources, source_name)); _FDT(fdt_setprop(fdt, node_offset, "interrupts", interrupts, diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 39134f0ef0..88797b3d36 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2121,8 +2121,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb, irqmap[2] = 0; irqmap[3] = cpu_to_be32(j+1); irqmap[4] = cpu_to_be32(xics_phandle); - irqmap[5] = cpu_to_be32(phb->lsi_table[lsi_num].irq); - irqmap[6] = cpu_to_be32(0x8); + spapr_dt_xics_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); } } /* Write interrupt map */ diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c index bb7ed2c537..472dd6f33a 100644 --- a/hw/ppc/spapr_vio.c +++ b/hw/ppc/spapr_vio.c @@ -126,8 +126,9 @@ static int vio_make_devnode(VIOsPAPRDevice *dev, } if (dev->irq) { - uint32_t ints_prop[] = {cpu_to_be32(dev->irq), 0}; + uint32_t ints_prop[2]; + spapr_dt_xics_irq(ints_prop, dev->irq, false); ret = fdt_setprop(fdt, node_off, "interrupts", ints_prop, sizeof(ints_prop)); if (ret < 0) { diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 6b8e04c787..14757b805e 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -590,6 +590,16 @@ void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr); #define RTAS_EVENT_SCAN_RATE 1 +/* This helper should be used to encode interrupt specifiers when the related + * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, + * VIO devices, RTAS event sources and PHBs). + */ +static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi) +{ + intspec[0] = cpu_to_be32(irq); + intspec[1] = is_lsi ? cpu_to_be32(1) : 0; +} + typedef struct sPAPRTCETable sPAPRTCETable; #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" -- cgit v1.2.3-55-g7522 From 493b78303532146c8161b33e878db8af7dca3b81 Mon Sep 17 00:00:00 2001 From: Marc-André Lureau Date: Mon, 6 Nov 2017 19:39:23 +0100 Subject: qdev: add DEFINE_PROP_TPMBE A property to lookup a tpm backend. Signed-off-by: Marc-André Lureau Reviewed-by: Stefan Berger Signed-off-by: Stefan Berger --- hw/core/qdev-properties-system.c | 64 ++++++++++++++++++++++++++++++++++++++++ include/hw/qdev-properties.h | 3 ++ 2 files changed, 67 insertions(+) (limited to 'include/hw') diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index ec10da7424..c17364655c 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -21,6 +21,7 @@ #include "net/hub.h" #include "qapi/visitor.h" #include "chardev/char-fe.h" +#include "sysemu/tpm_backend.h" #include "sysemu/iothread.h" static void get_pointer(Object *obj, Visitor *v, Property *prop, @@ -236,6 +237,69 @@ const PropertyInfo qdev_prop_chr = { .release = release_chr, }; +/* --- character device --- */ + +static void get_tpm(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + TPMBackend **be = qdev_get_prop_ptr(dev, opaque); + char *p; + + p = g_strdup(*be ? (*be)->id : ""); + visit_type_str(v, name, &p, errp); + g_free(p); +} + +static void set_tpm(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Error *local_err = NULL; + Property *prop = opaque; + TPMBackend *s, **be = qdev_get_prop_ptr(dev, prop); + char *str; + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_str(v, name, &str, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + s = qemu_find_tpm_be(str); + if (s == NULL) { + error_setg(errp, "Property '%s.%s' can't find value '%s'", + object_get_typename(obj), prop->name, str); + } else if (tpm_backend_init(s, TPM_IF(obj), errp) == 0) { + *be = s; /* weak reference, avoid cyclic ref */ + } + g_free(str); +} + +static void release_tpm(Object *obj, const char *name, void *opaque) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + TPMBackend **be = qdev_get_prop_ptr(dev, prop); + + if (*be) { + tpm_backend_reset(*be); + } +} + +const PropertyInfo qdev_prop_tpm = { + .name = "str", + .description = "ID of a tpm to use as a backend", + .get = get_tpm, + .set = set_tpm, + .release = release_tpm, +}; + /* --- netdev device --- */ static void get_netdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index e2321f1cc1..4d24cdf8d6 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -17,6 +17,7 @@ extern const PropertyInfo qdev_prop_int64; extern const PropertyInfo qdev_prop_size; extern const PropertyInfo qdev_prop_string; extern const PropertyInfo qdev_prop_chr; +extern const PropertyInfo qdev_prop_tpm; extern const PropertyInfo qdev_prop_ptr; extern const PropertyInfo qdev_prop_macaddr; extern const PropertyInfo qdev_prop_on_off_auto; @@ -186,6 +187,8 @@ extern const PropertyInfo qdev_prop_link; #define DEFINE_PROP_CHR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharBackend) +#define DEFINE_PROP_TPMBE(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_tpm, TPMBackend *) #define DEFINE_PROP_STRING(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*) #define DEFINE_PROP_NETDEV(_n, _s, _f) \ -- cgit v1.2.3-55-g7522 From 9102fe6c7f63306670b7d45635ddfeab72409199 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 13 Dec 2017 02:17:34 -0300 Subject: hw/registerfields: fix a typo in the FIELD() documentation Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Michael Tokarev --- include/hw/registerfields.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/hw') diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index af101d5ae6..ad9d7a82a3 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,7 +22,7 @@ /* Define SHIFT, LENGTH and MASK constants for a field within a register */ -/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH +/* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH * constants for field BAR in register FOO. */ #define FIELD(reg, field, shift, length) \ -- cgit v1.2.3-55-g7522 From cdb70a5c18aec03ef3b8b1bc68d5ca8a3cd80155 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 13 Dec 2017 02:17:35 -0300 Subject: hw/registerfields: add 64-bit extract/deposit macros Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Michael Tokarev --- include/hw/registerfields.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/hw') diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index ad9d7a82a3..f59e7f47bd 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -35,6 +35,9 @@ #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX64(storage, reg, field) \ + extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) /* Extract a field from an array of registers */ #define ARRAY_FIELD_EX32(regs, reg, field) \ @@ -52,6 +55,14 @@ d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH, v.v); \ d; }) +#define FIELD_DP64(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v = { .v = val }; \ + uint64_t d; \ + d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) /* Deposit a field to array of registers. */ #define ARRAY_FIELD_DP32(regs, reg, field, val) \ -- cgit v1.2.3-55-g7522 From 27de8f2dcf9c7daa3f5691cefab3563dea3535d2 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 13 Dec 2017 02:17:36 -0300 Subject: hw/registerfields: add missing include This allows to use this header in qtests. This fixes: CC tests/test.o include/hw/registerfields.h:32:41: error: implicit declaration of function ‘MAKE_64BIT_MASK’ [-Werror=implicit-function-declaration] MAKE_64BIT_MASK(shift, length)}; ^ include/hw/registerfields.h:39:5: error: implicit declaration of function ‘extract64’; [-Werror=implicit-function-declaration] extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Michael Tokarev --- include/hw/registerfields.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/hw') diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index f59e7f47bd..44e0b94edf 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -11,6 +11,8 @@ #ifndef REGISTERFIELDS_H #define REGISTERFIELDS_H +#include + /* Define constants for a 32 bit register */ /* This macro will define A_FOO, for the byte address of a register -- cgit v1.2.3-55-g7522 From b86caf7ad8ba779747975fe838b26aba366eb731 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:43:54 -0300 Subject: hw: remove "qemu/osdep.h" from header files applied using ./scripts/clean-includes Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Corey Minyard Tested-by: Corey Minyard Signed-off-by: Michael Tokarev --- include/hw/acpi/ipmi.h | 1 - include/hw/cpu/core.h | 1 - include/hw/i2c/ppc4xx_i2c.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include/hw') diff --git a/include/hw/acpi/ipmi.h b/include/hw/acpi/ipmi.h index ab2bb29048..c38483565c 100644 --- a/include/hw/acpi/ipmi.h +++ b/include/hw/acpi/ipmi.h @@ -9,7 +9,6 @@ #ifndef HW_ACPI_IPMI_H #define HW_ACPI_IPMI_H -#include "qemu/osdep.h" #include "hw/acpi/aml-build.h" /* diff --git a/include/hw/cpu/core.h b/include/hw/cpu/core.h index 79ac79c29c..b7470644d8 100644 --- a/include/hw/cpu/core.h +++ b/include/hw/cpu/core.h @@ -9,7 +9,6 @@ #ifndef HW_CPU_CORE_H #define HW_CPU_CORE_H -#include "qemu/osdep.h" #include "hw/qdev.h" #define TYPE_CPU_CORE "cpu-core" diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h index e53042f6d4..3450bda577 100644 --- a/include/hw/i2c/ppc4xx_i2c.h +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -25,7 +25,6 @@ #ifndef PPC4XX_I2C_H #define PPC4XX_I2C_H -#include "qemu/osdep.h" #include "qemu-common.h" #include "hw/sysbus.h" #include "hw/i2c/i2c.h" -- cgit v1.2.3-55-g7522 From 40a3bbc93e5a75bbfc1d220b8bf9bfc33bb1b4e5 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:14 -0300 Subject: hw/unicore32: restrict hw addr defines to source file and drop unused #includes Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Michael Tokarev --- hw/unicore32/puv3.c | 15 ++++++++++----- include/hw/unicore32/puv3.h | 10 ---------- 2 files changed, 10 insertions(+), 15 deletions(-) (limited to 'include/hw') diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index 1b39cc035b..db26959a1d 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -11,16 +11,11 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu-common.h" #include "cpu.h" #include "ui/console.h" -#include "elf.h" -#include "exec/address-spaces.h" -#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/i386/pc.h" -#include "qemu/error-report.h" #include "sysemu/qtest.h" #undef DEBUG_PUV3 @@ -29,6 +24,16 @@ #define KERNEL_LOAD_ADDR 0x03000000 #define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */ +/* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ +#define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */ + +/* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ +#define PUV3_GPIO_BASE (0xee500000) /* APB-5 */ +#define PUV3_INTC_BASE (0xee600000) /* APB-6 */ +#define PUV3_OST_BASE (0xee800000) /* APB-8 */ +#define PUV3_PM_BASE (0xeea00000) /* APB-10 */ +#define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */ + static void puv3_intc_cpu_handler(void *opaque, int irq, int level) { UniCore32CPU *cpu = opaque; diff --git a/include/hw/unicore32/puv3.h b/include/hw/unicore32/puv3.h index 5a4839f8df..f587a1f622 100644 --- a/include/hw/unicore32/puv3.h +++ b/include/hw/unicore32/puv3.h @@ -14,16 +14,6 @@ #define PUV3_REGS_OFFSET (0x1000) /* 4K is reasonable */ -/* PKUnity System bus (AHB): 0xc0000000 - 0xedffffff (640MB) */ -#define PUV3_DMA_BASE (0xc0200000) /* AHB-4 */ - -/* PKUnity Peripheral bus (APB): 0xee000000 - 0xefffffff (128MB) */ -#define PUV3_GPIO_BASE (0xee500000) /* APB-5 */ -#define PUV3_INTC_BASE (0xee600000) /* APB-6 */ -#define PUV3_OST_BASE (0xee800000) /* APB-8 */ -#define PUV3_PM_BASE (0xeea00000) /* APB-10 */ -#define PUV3_PS2_BASE (0xeeb00000) /* APB-11 */ - /* Hardware interrupts */ #define PUV3_IRQS_NR (32) -- cgit v1.2.3-55-g7522 From acf695eca605ed18fd485af3414e78d1edf93082 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:15 -0300 Subject: hw/timer/i8254: rename pit_init() -> i8254_pit_init() and remove the old i386/pc dependency Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau Signed-off-by: Michael Tokarev --- hw/alpha/dp264.c | 2 +- hw/i386/pc.c | 2 +- hw/isa/i82378.c | 2 +- hw/mips/mips_fulong2e.c | 2 +- hw/mips/mips_jazz.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/mips/mips_r4k.c | 2 +- hw/timer/i8254.c | 1 - hw/timer/i8254_common.c | 1 - include/hw/timer/i8254.h | 5 +++-- include/hw/timer/i8254_internal.h | 2 +- 11 files changed, 11 insertions(+), 12 deletions(-) (limited to 'include/hw') diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index babd6ea514..887a7401f1 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -80,7 +80,7 @@ static void clipper_init(MachineState *machine) /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ rtc_init(isa_bus, 1900, rtc_irq); - pit_init(isa_bus, 0x40, 0, NULL); + i8254_pit_init(isa_bus, 0x40, 0, NULL); isa_create_simple(isa_bus, "i8042"); /* VGA setup. Don't bother loading the bios. */ diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 186545d2a4..6a6041573f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1573,7 +1573,7 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, if (kvm_pit_in_kernel()) { pit = kvm_pit_init(isa_bus, 0x40); } else { - pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); + pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); } if (hpet) { /* connect PIT to output control line of the HPET */ diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index d20ea4c2ee..a9c15f858d 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -97,7 +97,7 @@ static void i82378_realize(PCIDevice *pci, Error **errp) isa_bus_irqs(isabus, s->i8259); /* 1 82C54 (pit) */ - isa = pit_init(isabus, 0x40, 0, NULL); + isa = i8254_pit_init(isabus, 0x40, 0, NULL); /* speaker */ pcspk_init(isabus, isa); diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 146cf0fccd..2a2a09c9de 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -359,7 +359,7 @@ static void mips_fulong2e_init(MachineState *machine) smbus_eeprom_init(smbus, 1, eeprom_spd, sizeof(eeprom_spd)); /* init other devices */ - pit = pit_init(isa_bus, 0x40, 0, NULL); + pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); DMA_init(isa_bus, 0); /* Super I/O */ diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index fe4f17389f..995419344d 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -218,7 +218,7 @@ static void mips_jazz_init(MachineState *machine, i8259 = i8259_init(isa_bus, env->irq[4]); isa_bus_irqs(isa_bus, i8259); DMA_init(isa_bus, 0); - pit = pit_init(isa_bus, 0x40, 0, NULL); + pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); pcspk_init(isa_bus, pit); /* Video card */ diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index ec6af4a277..88b4733743 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1208,7 +1208,7 @@ void mips_malta_init(MachineState *machine) isa_get_irq(NULL, 9), NULL, 0, NULL); smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size); g_free(smbus_eeprom_buf); - pit = pit_init(isa_bus, 0x40, 0, NULL); + pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); DMA_init(isa_bus, 0); /* Super I/O */ diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 3bbb1827e1..58d7bac18b 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -272,7 +272,7 @@ void mips_r4k_init(MachineState *machine) rtc_init(isa_bus, 2000, NULL); - pit = pit_init(isa_bus, 0x40, 0, NULL); + pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c index 5e61ad50a8..dbc4a0baec 100644 --- a/hw/timer/i8254.c +++ b/hw/timer/i8254.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" #include "qemu/timer.h" #include "hw/timer/i8254.h" diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c index b623c96198..6190b6fc5d 100644 --- a/hw/timer/i8254_common.c +++ b/hw/timer/i8254_common.c @@ -24,7 +24,6 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" #include "qemu/timer.h" #include "hw/timer/i8254.h" diff --git a/include/hw/timer/i8254.h b/include/hw/timer/i8254.h index 5adae9fa44..5b12eb918e 100644 --- a/include/hw/timer/i8254.h +++ b/include/hw/timer/i8254.h @@ -26,6 +26,7 @@ #define HW_I8254_H #include "hw/hw.h" +#include "hw/qdev.h" #include "hw/isa/isa.h" #define PIT_FREQ 1193182 @@ -48,8 +49,8 @@ typedef struct PITChannelInfo { #define TYPE_I8254 "isa-pit" #define TYPE_KVM_I8254 "kvm-pit" -static inline ISADevice *pit_init(ISABus *bus, int base, int isa_irq, - qemu_irq alt_irq) +static inline ISADevice *i8254_pit_init(ISABus *bus, int base, int isa_irq, + qemu_irq alt_irq) { DeviceState *dev; ISADevice *d; diff --git a/include/hw/timer/i8254_internal.h b/include/hw/timer/i8254_internal.h index dc09cc0467..c37a438f82 100644 --- a/include/hw/timer/i8254_internal.h +++ b/include/hw/timer/i8254_internal.h @@ -26,8 +26,8 @@ #define QEMU_I8254_INTERNAL_H #include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" +#include "qemu/timer.h" typedef struct PITChannelState { int count; /* can be 65536 */ -- cgit v1.2.3-55-g7522 From 6c646a11bf5ef87424fa07d3c42d04e709cd7c5e Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:16 -0300 Subject: hw/timer/mc146818: rename rtc_init() -> mc146818_rtc_init() Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau Reviewed-by: David Gibson Signed-off-by: Michael Tokarev --- hw/alpha/dp264.c | 2 +- hw/i386/pc.c | 2 +- hw/isa/i82378.c | 3 ++- hw/mips/mips_fulong2e.c | 2 +- hw/mips/mips_jazz.c | 2 +- hw/mips/mips_malta.c | 2 +- hw/mips/mips_r4k.c | 2 +- hw/ppc/pnv.c | 2 +- hw/timer/mc146818rtc.c | 2 +- include/hw/timer/mc146818rtc.h | 3 ++- 10 files changed, 12 insertions(+), 10 deletions(-) (limited to 'include/hw') diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 887a7401f1..766373eec7 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -78,7 +78,7 @@ static void clipper_init(MachineState *machine) clipper_pci_map_irq); /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ - rtc_init(isa_bus, 1900, rtc_irq); + mc146818_rtc_init(isa_bus, 1900, rtc_irq); i8254_pit_init(isa_bus, 0x40, 0, NULL); isa_create_simple(isa_bus, "i8042"); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 6a6041573f..fe5e8b53bb 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1565,7 +1565,7 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } } - *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); + *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); qemu_register_boot_set(pc_boot_set, *rtc_state); diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index a9c15f858d..a5d67bc6d7 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -21,6 +21,7 @@ #include "hw/pci/pci.h" #include "hw/i386/pc.h" #include "hw/timer/i8254.h" +#include "hw/timer/mc146818rtc.h" #include "hw/audio/pcspk.h" #define TYPE_I82378 "i82378" @@ -106,7 +107,7 @@ static void i82378_realize(PCIDevice *pci, Error **errp) isa = isa_create_simple(isabus, "i82374"); /* timer */ - isa_create_simple(isabus, "mc146818rtc"); + isa_create_simple(isabus, TYPE_MC146818_RTC); } static void i82378_init(Object *obj) diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 2a2a09c9de..725e25a134 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -365,7 +365,7 @@ static void mips_fulong2e_init(MachineState *machine) /* Super I/O */ isa_create_simple(isa_bus, "i8042"); - rtc_init(isa_bus, 2000, NULL); + mc146818_rtc_init(isa_bus, 2000, NULL); serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); parallel_hds_isa_init(isa_bus, 1); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 995419344d..22a3d5169c 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -288,7 +288,7 @@ static void mips_jazz_init(MachineState *machine, fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds); /* Real time clock */ - rtc_init(isa_bus, 1980, NULL); + mc146818_rtc_init(isa_bus, 1980, NULL); memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000); memory_region_add_subregion(address_space, 0x80004000, rtc); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 88b4733743..37f19428d6 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1214,7 +1214,7 @@ void mips_malta_init(MachineState *machine) /* Super I/O */ isa_create_simple(isa_bus, "i8042"); - rtc_init(isa_bus, 2000, NULL); + mc146818_rtc_init(isa_bus, 2000, NULL); serial_hds_isa_init(isa_bus, 0, 2); parallel_hds_isa_init(isa_bus, 1); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 58d7bac18b..9884ee7e9f 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -270,7 +270,7 @@ void mips_r4k_init(MachineState *machine) i8259 = i8259_init(isa_bus, env->irq[2]); isa_bus_irqs(isa_bus, i8259); - rtc_init(isa_bus, 2000, NULL); + mc146818_rtc_init(isa_bus, 2000, NULL); pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c35c439d81..94ffc8e137 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -655,7 +655,7 @@ static void ppc_powernv_init(MachineState *machine) serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); /* Create an RTC ISA device too */ - rtc_init(pnv->isa_bus, 2000, NULL); + mc146818_rtc_init(pnv->isa_bus, 2000, NULL); /* OpenPOWER systems use a IPMI SEL Event message to notify the * host to powerdown */ diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index 7764be25ec..35a05a64cc 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -999,7 +999,7 @@ static void rtc_realizefn(DeviceState *dev, Error **errp) qdev_init_gpio_out(dev, &s->irq, 1); } -ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) +ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) { DeviceState *dev; ISADevice *isadev; diff --git a/include/hw/timer/mc146818rtc.h b/include/hw/timer/mc146818rtc.h index 7c8e64b203..fe6ed63f71 100644 --- a/include/hw/timer/mc146818rtc.h +++ b/include/hw/timer/mc146818rtc.h @@ -6,7 +6,8 @@ #define TYPE_MC146818_RTC "mc146818rtc" -ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq); +ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, + qemu_irq intercept_irq); void rtc_set_memory(ISADevice *dev, int addr, int val); int rtc_get_memory(ISADevice *dev, int addr); -- cgit v1.2.3-55-g7522 From 9dc047ce8f9e787bb9a9c5892c38c2424a0ee65f Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:17 -0300 Subject: hw/acpi: ACPI_PM_* defines are not restricted to i386 arch this allows to remove the old i386/pc dependency on acpi/core. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Igor Mammedov Signed-off-by: Michael Tokarev --- hw/acpi/core.c | 1 - include/hw/acpi/acpi.h | 11 +++++++++++ include/hw/i386/pc.h | 11 ----------- 3 files changed, 11 insertions(+), 12 deletions(-) (limited to 'include/hw') diff --git a/hw/acpi/core.c b/hw/acpi/core.c index cd0a1d357b..eb9b76f70b 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "sysemu/sysemu.h" #include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/acpi/acpi.h" #include "hw/nvram/fw_cfg.h" #include "qemu/config-file.h" diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h index 7b3d93cf0d..39ff512129 100644 --- a/include/hw/acpi/acpi.h +++ b/include/hw/acpi/acpi.h @@ -39,6 +39,17 @@ #define ACPI_PM2_REGISTER_WIDTH 8 #define ACPI_PM_TIMER_WIDTH 32 +/* PC-style peripherals (also used by other machines). */ +#define ACPI_PM_PROP_S3_DISABLED "disable_s3" +#define ACPI_PM_PROP_S4_DISABLED "disable_s4" +#define ACPI_PM_PROP_S4_VAL "s4_val" +#define ACPI_PM_PROP_SCI_INT "sci_int" +#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" +#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" +#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" +#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" +#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" + /* PM Timer ticks per second (HZ) */ #define PM_TIMER_FREQUENCY 3579545 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ef438bd765..252526e600 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -151,17 +151,6 @@ struct PCMachineClass { #define PC_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) -/* PC-style peripherals (also used by other machines). */ - -#define ACPI_PM_PROP_S3_DISABLED "disable_s3" -#define ACPI_PM_PROP_S4_DISABLED "disable_s4" -#define ACPI_PM_PROP_S4_VAL "s4_val" -#define ACPI_PM_PROP_SCI_INT "sci_int" -#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" -#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" -#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" -#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" -#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" #define ACPI_PM_PROP_TCO_ENABLED "enable_tco" /* parallel.c */ -- cgit v1.2.3-55-g7522 From b1c439d1794a86536bf5f47d9823ff156a7d7433 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:18 -0300 Subject: hw/acpi/ich9: extract ACPI_PM_PROP_TCO_ENABLED from i386/pc enable_tco is specific to i386/pc. Suggested-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Igor Mammedov Signed-off-by: Michael Tokarev --- include/hw/acpi/ich9.h | 2 ++ include/hw/i386/pc.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/hw') diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index a352c94fde..59aeb06393 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -63,6 +63,8 @@ typedef struct ICH9LPCPMRegs { TCOIORegs tco_regs; } ICH9LPCPMRegs; +#define ACPI_PM_PROP_TCO_ENABLED "enable_tco" + void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, bool smm_enabled, qemu_irq sci_irq); diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 252526e600..3794473108 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -151,8 +151,6 @@ struct PCMachineClass { #define PC_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) -#define ACPI_PM_PROP_TCO_ENABLED "enable_tco" - /* parallel.c */ void parallel_hds_isa_init(ISABus *bus, int n); -- cgit v1.2.3-55-g7522 From 866e2b3727b6f9f55d5921365f2c97ecf763de65 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:21 -0300 Subject: hw/display/vga: extract public API from i386/pc to "hw/display/vga.h" and remove the old i386/pc dependency. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Michael Tokarev --- MAINTAINERS | 1 + hw/display/vga-isa-mm.c | 3 +-- hw/display/vga-isa.c | 2 +- hw/display/vga.c | 2 +- hw/mips/mips_jazz.c | 1 + include/hw/display/vga.h | 25 +++++++++++++++++++++++++ include/hw/i386/pc.h | 12 ------------ vl.c | 2 +- 8 files changed, 31 insertions(+), 17 deletions(-) create mode 100644 include/hw/display/vga.h (limited to 'include/hw') diff --git a/MAINTAINERS b/MAINTAINERS index acbff2f1bb..8859a50c36 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -881,6 +881,7 @@ F: hw/timer/hpet* F: hw/timer/i8254* F: hw/timer/mc146818rtc* F: hw/watchdog/wdt_ib700.c +F: include/hw/display/vga.h F: include/hw/i2c/pm_smbus.h F: include/hw/isa/i8257.h F: include/hw/timer/hpet.h diff --git a/hw/display/vga-isa-mm.c b/hw/display/vga-isa-mm.c index 68c4d6e23e..e887b45651 100644 --- a/hw/display/vga-isa-mm.c +++ b/hw/display/vga-isa-mm.c @@ -23,10 +23,9 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/i386/pc.h" +#include "hw/display/vga.h" #include "vga_int.h" #include "ui/pixel_ops.h" -#include "qemu/timer.h" #define VGA_RAM_SIZE (8192 * 1024) diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index 26f69fd40a..469834add5 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -25,7 +25,7 @@ */ #include "qemu/osdep.h" #include "hw/hw.h" -#include "hw/i386/pc.h" +#include "hw/isa/isa.h" #include "vga_int.h" #include "ui/pixel_ops.h" #include "qemu/timer.h" diff --git a/hw/display/vga.c b/hw/display/vga.c index 4163b532e0..a0412000a5 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -24,7 +24,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/hw.h" -#include "hw/i386/pc.h" +#include "hw/display/vga.h" #include "hw/pci/pci.h" #include "vga_int.h" #include "vga_regs.h" diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 22a3d5169c..0d2c0683ba 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -39,6 +39,7 @@ #include "hw/loader.h" #include "hw/timer/mc146818rtc.h" #include "hw/timer/i8254.h" +#include "hw/display/vga.h" #include "hw/audio/pcspk.h" #include "sysemu/block-backend.h" #include "hw/sysbus.h" diff --git a/include/hw/display/vga.h b/include/hw/display/vga.h new file mode 100644 index 0000000000..0401a3a292 --- /dev/null +++ b/include/hw/display/vga.h @@ -0,0 +1,25 @@ +/* + * QEMU VGA Emulator. + * + * Copyright (c) 2003 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#ifndef QEMU_HW_DISPLAY_VGA_H +#define QEMU_HW_DISPLAY_VGA_H + +#include "exec/memory.h" + +enum vga_retrace_method { + VGA_RETRACE_DUMB, + VGA_RETRACE_PRECISE +}; + +extern enum vga_retrace_method vga_retrace_method; + +int isa_vga_mm_init(hwaddr vram_base, + hwaddr ctrl_base, int it_shift, + MemoryRegion *address_space); + +#endif diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 3794473108..1d55ba3322 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -302,18 +302,6 @@ PCIBus *find_i440fx(void); extern PCIDevice *piix4_dev; int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); -/* vga.c */ -enum vga_retrace_method { - VGA_RETRACE_DUMB, - VGA_RETRACE_PRECISE -}; - -extern enum vga_retrace_method vga_retrace_method; - -int isa_vga_mm_init(hwaddr vram_base, - hwaddr ctrl_base, int it_shift, - MemoryRegion *address_space); - /* ne2000.c */ static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) { diff --git a/vl.c b/vl.c index c1ba52306a..e9012bb009 100644 --- a/vl.c +++ b/vl.c @@ -57,9 +57,9 @@ int main(int argc, char **argv) #include "hw/boards.h" #include "sysemu/accel.h" #include "hw/usb.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" #include "hw/scsi/scsi.h" +#include "hw/display/vga.h" #include "hw/bt.h" #include "sysemu/watchdog.h" #include "hw/smbios/smbios.h" -- cgit v1.2.3-55-g7522 From 489983d6b4cb501a86dfd08648fb370aec0f9b51 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:22 -0300 Subject: hw/net/ne2000: extract ne2k-isa code from i386/pc to ne2000-isa.c - add "hw/net/ne2000-isa.h" - remove the old i386 dependency Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau Acked-by: David Gibson [PPC] Signed-off-by: Michael Tokarev --- hw/i386/pc.c | 1 + hw/mips/mips_r4k.c | 1 + hw/net/ne2000-isa.c | 6 ++---- hw/net/ne2000.c | 2 -- hw/net/ne2000.h | 3 +++ hw/ppc/prep.c | 1 + include/hw/i386/pc.h | 20 -------------------- include/hw/net/ne2000-isa.h | 33 +++++++++++++++++++++++++++++++++ 8 files changed, 41 insertions(+), 26 deletions(-) create mode 100644 include/hw/net/ne2000-isa.h (limited to 'include/hw') diff --git a/hw/i386/pc.c b/hw/i386/pc.c index fe5e8b53bb..3fcf318a95 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -69,6 +69,7 @@ #include "qom/cpu.h" #include "hw/nmi.h" #include "hw/i386/intel_iommu.h" +#include "hw/net/ne2000-isa.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 9884ee7e9f..244bd41813 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -18,6 +18,7 @@ #include "hw/char/serial.h" #include "hw/isa/isa.h" #include "net/net.h" +#include "hw/net/ne2000-isa.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/block/flash.h" diff --git a/hw/net/ne2000-isa.c b/hw/net/ne2000-isa.c index f3455339ee..70e5c1d3d4 100644 --- a/hw/net/ne2000-isa.c +++ b/hw/net/ne2000-isa.c @@ -22,17 +22,15 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "hw/hw.h" -#include "hw/i386/pc.h" #include "hw/isa/isa.h" +#include "hw/net/ne2000-isa.h" #include "hw/qdev.h" -#include "net/net.h" #include "ne2000.h" +#include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qapi/error.h" #include "qapi/visitor.h" -#define TYPE_ISA_NE2000 "ne2k_isa" #define ISA_NE2000(obj) OBJECT_CHECK(ISANE2000State, (obj), TYPE_ISA_NE2000) typedef struct ISANE2000State { diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c index 3938e6ddd8..6874c8c6b9 100644 --- a/hw/net/ne2000.c +++ b/hw/net/ne2000.c @@ -22,9 +22,7 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "hw/hw.h" #include "hw/pci/pci.h" -#include "net/net.h" #include "ne2000.h" #include "hw/loader.h" #include "sysemu/sysemu.h" diff --git a/hw/net/ne2000.h b/hw/net/ne2000.h index d213dccae3..adb8021bd1 100644 --- a/hw/net/ne2000.h +++ b/hw/net/ne2000.h @@ -1,6 +1,9 @@ #ifndef HW_NE2000_H #define HW_NE2000_H +#include "hw/hw.h" +#include "net/net.h" + #define NE2000_PMEM_SIZE (32*1024) #define NE2000_PMEM_START (16*1024) #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START) diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index 6f8accc397..af08ac319a 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -42,6 +42,7 @@ #include "hw/loader.h" #include "hw/timer/mc146818rtc.h" #include "hw/isa/pc87312.h" +#include "hw/net/ne2000-isa.h" #include "sysemu/block-backend.h" #include "sysemu/arch_init.h" #include "sysemu/kvm.h" diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 1d55ba3322..ab84e31cce 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -302,26 +302,6 @@ PCIBus *find_i440fx(void); extern PCIDevice *piix4_dev; int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); -/* ne2000.c */ -static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) -{ - DeviceState *dev; - ISADevice *isadev; - - qemu_check_nic_model(nd, "ne2k_isa"); - - isadev = isa_try_create(bus, "ne2k_isa"); - if (!isadev) { - return false; - } - dev = DEVICE(isadev); - qdev_prop_set_uint32(dev, "iobase", base); - qdev_prop_set_uint32(dev, "irq", irq); - qdev_set_nic_properties(dev, nd); - qdev_init_nofail(dev); - return true; -} - /* pc_sysfw.c */ void pc_system_firmware_init(MemoryRegion *rom_memory, bool isapc_ram_fw); diff --git a/include/hw/net/ne2000-isa.h b/include/hw/net/ne2000-isa.h new file mode 100644 index 0000000000..ff2bed9c95 --- /dev/null +++ b/include/hw/net/ne2000-isa.h @@ -0,0 +1,33 @@ +/* + * QEMU NE2000 emulation -- isa bus windup + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ +#include "hw/hw.h" +#include "hw/qdev.h" +#include "hw/isa/isa.h" +#include "net/net.h" + +#define TYPE_ISA_NE2000 "ne2k_isa" + +static inline ISADevice *isa_ne2000_init(ISABus *bus, int base, int irq, + NICInfo *nd) +{ + ISADevice *d; + + qemu_check_nic_model(nd, "ne2k_isa"); + + d = isa_try_create(bus, TYPE_ISA_NE2000); + if (d) { + DeviceState *dev = DEVICE(d); + + qdev_prop_set_uint32(dev, "iobase", base); + qdev_prop_set_uint32(dev, "irq", irq); + qdev_set_nic_properties(dev, nd); + qdev_init_nofail(dev); + } + return d; +} -- cgit v1.2.3-55-g7522 From 0d5d8a3a906f782eab8a85079eede78879dc8155 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Tue, 17 Oct 2017 13:44:23 -0300 Subject: hw/misc/pvpanic: extract public API from i386/pc to "hw/misc/pvpanic.h" and remove the old i386/pc dependency. Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Michael Tokarev --- hw/i386/acpi-build.c | 2 +- hw/misc/pvpanic.c | 9 ++++----- include/hw/i386/pc.h | 3 --- include/hw/misc/pvpanic.h | 21 +++++++++++++++++++++ 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 include/hw/misc/pvpanic.h (limited to 'include/hw') diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index dd1420b410..5a6dee081c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -28,8 +28,8 @@ #include "qemu/error-report.h" #include "hw/pci/pci.h" #include "qom/cpu.h" -#include "hw/i386/pc.h" #include "target/i386/cpu.h" +#include "hw/misc/pvpanic.h" #include "hw/timer/hpet.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c index 3a0e4ba828..b26250dec9 100644 --- a/hw/misc/pvpanic.c +++ b/hw/misc/pvpanic.c @@ -17,7 +17,7 @@ #include "qemu/log.h" #include "hw/nvram/fw_cfg.h" -#include "hw/i386/pc.h" +#include "hw/misc/pvpanic.h" /* The bit of supported pv event */ #define PVPANIC_F_PANICKED 0 @@ -25,9 +25,8 @@ /* The pv event value */ #define PVPANIC_PANICKED (1 << PVPANIC_F_PANICKED) -#define TYPE_ISA_PVPANIC_DEVICE "pvpanic" #define ISA_PVPANIC_DEVICE(obj) \ - OBJECT_CHECK(PVPanicState, (obj), TYPE_ISA_PVPANIC_DEVICE) + OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC) static void handle_event(int event) { @@ -104,7 +103,7 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp) uint16_t pvpanic_port(void) { - Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL); + Object *o = object_resolve_path_type("", TYPE_PVPANIC, NULL); if (!o) { return 0; } @@ -126,7 +125,7 @@ static void pvpanic_isa_class_init(ObjectClass *klass, void *data) } static TypeInfo pvpanic_isa_info = { - .name = TYPE_ISA_PVPANIC_DEVICE, + .name = TYPE_PVPANIC, .parent = TYPE_ISA_DEVICE, .instance_size = sizeof(PVPanicState), .instance_init = pvpanic_isa_initfn, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ab84e31cce..6f77eb0665 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -306,9 +306,6 @@ int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); void pc_system_firmware_init(MemoryRegion *rom_memory, bool isapc_ram_fw); -/* pvpanic.c */ -uint16_t pvpanic_port(void); - /* acpi-build.c */ void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h new file mode 100644 index 0000000000..36a54e270c --- /dev/null +++ b/include/hw/misc/pvpanic.h @@ -0,0 +1,21 @@ +/* + * QEMU simulated pvpanic device. + * + * Copyright Fujitsu, Corp. 2013 + * + * Authors: + * Wen Congyang + * Hu Tao + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ +#ifndef HW_MISC_PVPANIC_H +#define HW_MISC_PVPANIC_H + +#define TYPE_PVPANIC "pvpanic" + +uint16_t pvpanic_port(void); + +#endif -- cgit v1.2.3-55-g7522 From 7f709ce739d46ecd6df98921a20e9dce1dcc421b Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Tue, 22 Nov 2016 10:08:02 -0800 Subject: target/xtensa: import libisa source The canonical way of dealing with Xtensa instructions decoding and encoding is through the libisa. Libisa is a configuration-independent library with a stable interface plus generated configuration-specific xtensa-modules.c file with implementations of decoding and encoding functions. Libisa is MIT-licensed and originally disributed xtensa-modules.c files are also MIT-licensed and are available as a part of xtensa configuration overlay. Signed-off-by: Max Filippov --- include/hw/xtensa/xtensa-isa.h | 838 +++++++++++++++++ target/xtensa/Makefile.objs | 1 + target/xtensa/xtensa-isa-internal.h | 231 +++++ target/xtensa/xtensa-isa.c | 1745 +++++++++++++++++++++++++++++++++++ target/xtensa/xtensa-isa.h | 1 + 5 files changed, 2816 insertions(+) create mode 100644 include/hw/xtensa/xtensa-isa.h create mode 100644 target/xtensa/xtensa-isa-internal.h create mode 100644 target/xtensa/xtensa-isa.c create mode 100644 target/xtensa/xtensa-isa.h (limited to 'include/hw') diff --git a/include/hw/xtensa/xtensa-isa.h b/include/hw/xtensa/xtensa-isa.h new file mode 100644 index 0000000000..353f82ba25 --- /dev/null +++ b/include/hw/xtensa/xtensa-isa.h @@ -0,0 +1,838 @@ +/* Interface definition for configurable Xtensa ISA support. + * + * Copyright (c) 2001-2013 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Version number: This is intended to help support code that works with + * versions of this library from multiple Xtensa releases. + */ + +#define XTENSA_ISA_VERSION 7000 + +/* + * This file defines the interface to the Xtensa ISA library. This + * library contains most of the ISA-specific information for a + * particular Xtensa processor. For example, the set of valid + * instructions, their opcode encodings and operand fields are all + * included here. + * + * This interface basically defines a number of abstract data types. + * + * . an instruction buffer - for holding the raw instruction bits + * . ISA info - information about the ISA as a whole + * . instruction formats - instruction size and slot structure + * . opcodes - information about individual instructions + * . operands - information about register and immediate instruction operands + * . stateOperands - information about processor state instruction operands + * . interfaceOperands - information about interface instruction operands + * . register files - register file information + * . processor states - internal processor state information + * . system registers - "special registers" and "user registers" + * . interfaces - TIE interfaces that are external to the processor + * . functional units - TIE shared functions + * + * The interface defines a set of functions to access each data type. + * With the exception of the instruction buffer, the internal + * representations of the data structures are hidden. All accesses must + * be made through the functions defined here. + */ + +typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa; + + +/* + * Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are + * represented here using sequential integers beginning with 0. The + * specific values are only fixed for a particular instantiation of an + * xtensa_isa structure, so these values should only be used + * internally. + */ + +typedef int xtensa_opcode; +typedef int xtensa_format; +typedef int xtensa_regfile; +typedef int xtensa_state; +typedef int xtensa_sysreg; +typedef int xtensa_interface; +typedef int xtensa_funcUnit; + + +/* Define a unique value for undefined items. */ + +#define XTENSA_UNDEFINED -1 + + +/* + * Overview of using this interface to decode/encode instructions: + * + * Each Xtensa instruction is associated with a particular instruction + * format, where the format defines a fixed number of slots for + * operations. The formats for the core Xtensa ISA have only one slot, + * but FLIX instructions may have multiple slots. Within each slot, + * there is a single opcode and some number of associated operands. + * + * The encoding and decoding functions operate on instruction buffers, + * not on the raw bytes of the instructions. The same instruction + * buffer data structure is used for both entire instructions and + * individual slots in those instructions -- the contents of a slot need + * to be extracted from or inserted into the buffer for the instruction + * as a whole. + * + * Decoding an instruction involves first finding the format, which + * identifies the number of slots, and then decoding each slot + * separately. A slot is decoded by finding the opcode and then using + * the opcode to determine how many operands there are. For example: + * + * xtensa_insnbuf_from_chars + * xtensa_format_decode + * for each slot { + * xtensa_format_get_slot + * xtensa_opcode_decode + * for each operand { + * xtensa_operand_get_field + * xtensa_operand_decode + * } + * } + * + * Encoding an instruction is roughly the same procedure in reverse: + * + * xtensa_format_encode + * for each slot { + * xtensa_opcode_encode + * for each operand { + * xtensa_operand_encode + * xtensa_operand_set_field + * } + * xtensa_format_set_slot + * } + * xtensa_insnbuf_to_chars + */ + + +/* Error handling. */ + +/* + * Error codes. The code for the most recent error condition can be + * retrieved with the "errno" function. For any result other than + * xtensa_isa_ok, an error message containing additional information + * about the problem can be retrieved using the "error_msg" function. + * The error messages are stored in an internal buffer, which should + * not be freed and may be overwritten by subsequent operations. + */ + +typedef enum xtensa_isa_status_enum { + xtensa_isa_ok = 0, + xtensa_isa_bad_format, + xtensa_isa_bad_slot, + xtensa_isa_bad_opcode, + xtensa_isa_bad_operand, + xtensa_isa_bad_field, + xtensa_isa_bad_iclass, + xtensa_isa_bad_regfile, + xtensa_isa_bad_sysreg, + xtensa_isa_bad_state, + xtensa_isa_bad_interface, + xtensa_isa_bad_funcUnit, + xtensa_isa_wrong_slot, + xtensa_isa_no_field, + xtensa_isa_out_of_memory, + xtensa_isa_buffer_overflow, + xtensa_isa_internal_error, + xtensa_isa_bad_value +} xtensa_isa_status; + +xtensa_isa_status xtensa_isa_errno(xtensa_isa isa); + +char *xtensa_isa_error_msg(xtensa_isa isa); + + + +/* Instruction buffers. */ + +typedef uint32_t xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + + +/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */ + +int xtensa_insnbuf_size(xtensa_isa isa); + + +/* Allocate an xtensa_insnbuf of the right size. */ + +xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa); + + +/* Release an xtensa_insnbuf. */ + +void xtensa_insnbuf_free(xtensa_isa isa, xtensa_insnbuf buf); + + +/* + * Conversion between raw memory (char arrays) and our internal + * instruction representation. This is complicated by the Xtensa ISA's + * variable instruction lengths. When converting to chars, the buffer + * must contain a valid instruction so we know how many bytes to copy; + * thus, the "to_chars" function returns the number of bytes copied or + * XTENSA_UNDEFINED on error. The "from_chars" function first reads the + * minimal number of bytes required to decode the instruction length and + * then proceeds to copy the entire instruction into the buffer; if the + * memory does not contain a valid instruction, it copies the maximum + * number of bytes required for the longest Xtensa instruction. The + * "num_chars" argument may be used to limit the number of bytes that + * can be read or written. Otherwise, if "num_chars" is zero, the + * functions may read or write past the end of the code. + */ + +int xtensa_insnbuf_to_chars(xtensa_isa isa, const xtensa_insnbuf insn, + unsigned char *cp, int num_chars); + +void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn, + const unsigned char *cp, int num_chars); + + + +/* ISA information. */ + +/* Initialize the ISA information. */ + +xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p, + char **error_msg_p); + + +/* Deallocate an xtensa_isa structure. */ + +void xtensa_isa_free(xtensa_isa isa); + + +/* Get the maximum instruction size in bytes. */ + +int xtensa_isa_maxlength(xtensa_isa isa); + + +/* + * Decode the length in bytes of an instruction in raw memory (not an + * insnbuf). This function reads only the minimal number of bytes + * required to decode the instruction length. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp); + + +/* + * Get the number of stages in the processor's pipeline. The pipeline + * stage values returned by other functions in this library will range + * from 0 to N-1, where N is the value returned by this function. + * Note that the stage numbers used here may not correspond to the + * actual processor hardware, e.g., the hardware may have additional + * stages before stage 0. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_isa_num_pipe_stages(xtensa_isa isa); + + +/* Get the number of various entities that are defined for this processor. */ + +int xtensa_isa_num_formats(xtensa_isa isa); + +int xtensa_isa_num_opcodes(xtensa_isa isa); + +int xtensa_isa_num_regfiles(xtensa_isa isa); + +int xtensa_isa_num_states(xtensa_isa isa); + +int xtensa_isa_num_sysregs(xtensa_isa isa); + +int xtensa_isa_num_interfaces(xtensa_isa isa); + +int xtensa_isa_num_funcUnits(xtensa_isa isa); + + + +/* Instruction formats. */ + +/* Get the name of a format. Returns null on error. */ + +const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt); + + +/* + * Given a format name, return the format number. Returns + * XTENSA_UNDEFINED if the name is not a valid format. + */ + +xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname); + + +/* + * Decode the instruction format from a binary instruction buffer. + * Returns XTENSA_UNDEFINED if the format is not recognized. + */ + +xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn); + + +/* + * Set the instruction format field(s) in a binary instruction buffer. + * All the other fields are set to zero. Returns non-zero on error. + */ + +int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt, + xtensa_insnbuf insn); + + +/* + * Find the length (in bytes) of an instruction. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_format_length(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the number of slots in an instruction. Returns XTENSA_UNDEFINED + * on error. + */ + +int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt); + + +/* + * Get the opcode for a no-op in a particular slot. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt, + int slot); + + +/* + * Get the bits for a specified slot out of an insnbuf for the + * instruction as a whole and put them into an insnbuf for that one + * slot, and do the opposite to set a slot. Return non-zero on error. + */ + +int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf); + +int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf); + + + +/* Opcode information. */ + +/* + * Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + * the name is not a valid opcode mnemonic. + */ + +xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname); + + +/* + * Decode the opcode for one instruction slot from a binary instruction + * buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is + * illegal. + */ + +xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf); + + +/* + * Set the opcode field(s) for an instruction slot. All other fields + * in the slot are set to zero. Returns non-zero if the opcode cannot + * be encoded. + */ + +int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc); + + +/* Get the mnemonic name for an opcode. Returns null on error. */ + +const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc); + + +/* Check various properties of opcodes. These functions return 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. The instructions are classified as + * follows: + * + * branch: conditional branch; may fall through to next instruction (B*) + * jump: unconditional branch (J, JX, RET*, RF*) + * loop: zero-overhead loop (LOOP*) + * call: unconditional call; control returns to next instruction (CALL*) + * + * For the opcodes that affect control flow in some way, the branch + * target may be specified by an immediate operand or it may be an + * address stored in a register. You can distinguish these by + * checking if the instruction has a PC-relative immediate + * operand. + */ + +int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Find the number of ordinary operands, state operands, and interface + * operands for an instruction. These return XTENSA_UNDEFINED on + * error. + */ + +int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc); + +int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc); + + +/* + * Get functional unit usage requirements for an opcode. Each "use" + * is identified by a pair. The + * "num_funcUnit_uses" function returns the number of these "uses" or + * XTENSA_UNDEFINED on error. The "funcUnit_use" function returns + * a pointer to a "use" pair or null on error. + */ + +typedef struct xtensa_funcUnit_use_struct { + xtensa_funcUnit unit; + int stage; +} xtensa_funcUnit_use; + +int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc); + +xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa, + xtensa_opcode opc, int u); + + + +/* Operand information. */ + +/* Get the name of an operand. Returns null on error. */ + +const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some operands are "invisible", i.e., not explicitly specified in + * assembly language. When assembling an instruction, you need not set + * the values of invisible operands, since they are either hardwired or + * derived from other field values. The values of invisible operands + * can be examined in the same way as other operands, but remember that + * an invisible operand may get its value from another visible one, so + * the entire instruction must be available before examining the + * invisible operand values. This function returns 1 if an operand is + * visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note + * that whether an operand is visible is orthogonal to whether it is + * "implicit", i.e., whether it is encoded in a field in the + * instruction. + */ + +int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an operand is an input ('i'), output ('o'), or inout ('m') + * operand. Note: The output operand of a conditional assignment + * (e.g., movnez) appears here as an inout ('m') even if it is declared + * in the TIE code as an output ('o'); this allows the compiler to + * properly handle register allocation for conditional assignments. + * Returns 0 on error. + */ + +char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Get and set the raw (encoded) value of the field for the specified + * operand. The "set" function does not check if the value fits in the + * field; that is done by the "encode" function below. Both of these + * functions return non-zero on error, e.g., if the field is not defined + * for the specified slot. + */ + +int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32_t *valp); + +int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32_t val); + + +/* + * Encode and decode operands. The raw bits in the operand field may + * be encoded in a variety of different ways. These functions hide + * the details of that encoding. The result values are returned through + * the argument pointer. The return value is non-zero on error. + */ + +int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + +int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp); + + +/* + * An operand may be either a register operand or an immediate of some + * sort (e.g., PC-relative or not). The "is_register" function returns + * 0 if the operand is an immediate, 1 if it is a register, and + * XTENSA_UNDEFINED on error. The "regfile" function returns the + * regfile for a register operand, or XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd); + +xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc, + int opnd); + + +/* + * Register operands may span multiple consecutive registers, e.g., a + * 64-bit data type may occupy two 32-bit registers. Only the first + * register is encoded in the operand field. This function specifies + * the number of consecutive registers occupied by this operand. For + * non-register operands, the return value is undefined. Returns + * XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Some register operands do not completely identify the register being + * accessed. For example, the operand value may be added to an internal + * state value. By definition, this implies that the corresponding + * regfile is not allocatable. Unknown registers should generally be + * treated with worst-case assumptions. The function returns 0 if the + * register value is unknown, 1 if known, and XTENSA_UNDEFINED on + * error. + */ + +int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * Check if an immediate operand is PC-relative. Returns 0 for register + * operands and non-PC-relative immediates, 1 for PC-relative + * immediates, and XTENSA_UNDEFINED on error. + */ + +int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd); + + +/* + * For PC-relative offset operands, the interpretation of the offset may + * vary between opcodes, e.g., is it relative to the current PC or that + * of the next instruction? The following functions are defined to + * perform PC-relative relocations and to undo them (as in the + * disassembler). The "do_reloc" function takes the desired address + * value and the PC of the current instruction and sets the value to the + * corresponding PC-relative offset (which can then be encoded and + * stored into the operand field). The "undo_reloc" function takes the + * unencoded offset value and the current PC and sets the value to the + * appropriate address. The return values are non-zero on error. Note + * that these functions do not replace the encode/decode functions; the + * operands must be encoded/decoded separately and the encode functions + * are responsible for detecting invalid operand values. + */ + +int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + +int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc); + + + +/* State Operands. */ + +/* + * Get the state accessed by a state operand. Returns XTENSA_UNDEFINED + * on error. + */ + +xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc, + int stOp); + + +/* + * Check if a state operand is an input ('i'), output ('o'), or inout + * ('m') operand. Returns 0 on error. + */ + +char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp); + + + +/* Interface Operands. */ + +/* + * Get the external interface accessed by an interface operand. + * Returns XTENSA_UNDEFINED on error. + */ + +xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa, + xtensa_opcode opc, + int ifOp); + + + +/* Register Files. */ + +/* + * Regfiles include both "real" regfiles and "views", where a view + * allows a group of adjacent registers in a real "parent" regfile to be + * viewed as a single register. A regfile view has all the same + * properties as its parent except for its (long) name, bit width, number + * of entries, and default ctype. You can use the parent function to + * distinguish these two classes. + */ + +/* + * Look up a regfile by either its name or its abbreviated "short name". + * Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function + * ignores "view" regfiles since they always have the same shortname as + * their parents. + */ + +xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name); + +xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa, + const char *shortname); + + +/* + * Get the name or abbreviated "short name" of a regfile. + * Returns null on error. + */ + +const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf); + +const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the parent regfile of a "view" regfile. If the regfile is not a + * view, the result is the same as the input parameter. Returns + * XTENSA_UNDEFINED on error. + */ + +xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the bit width of a regfile or regfile view. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf); + + +/* + * Get the number of regfile entries. Returns XTENSA_UNDEFINED on + * error. + */ + +int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf); + + + +/* Processor States. */ + +/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */ + +xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name); + + +/* Get the name for a processor state. Returns null on error. */ + +const char *xtensa_state_name(xtensa_isa isa, xtensa_state st); + + +/* + * Get the bit width for a processor state. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st); + + +/* + * Check if a state is exported from the processor core. Returns 0 if + * the condition is false, 1 if the condition is true, and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st); + + +/* + * Check for a "shared_or" state. Returns 0 if the condition is false, + * 1 if the condition is true, and XTENSA_UNDEFINED on error. + */ + +int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st); + + + +/* Sysregs ("special registers" and "user registers"). */ + +/* + * Look up a register by its number and whether it is a "user register" + * or a "special register". Returns XTENSA_UNDEFINED if the sysreg does + * not exist. + */ + +xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user); + + +/* + * Check if there exists a sysreg with a given name. + * If not, this function returns XTENSA_UNDEFINED. + */ + +xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name); + + +/* Get the name of a sysreg. Returns null on error. */ + +const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* Get the register number. Returns XTENSA_UNDEFINED on error. */ + +int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg); + + +/* + * Check if a sysreg is a "special register" or a "user register". + * Returns 0 for special registers, 1 for user registers and + * XTENSA_UNDEFINED on error. + */ + +int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg); + + + +/* Interfaces. */ + +/* + * Find an interface by name. The return value is XTENSA_UNDEFINED if + * the specified interface is not found. + */ + +xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname); + + +/* Get the name of an interface. Returns null on error. */ + +const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf); + + +/* + * Get the bit width for an interface. + * Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if an interface is an input ('i') or output ('o') with respect + * to the Xtensa processor core. Returns 0 on error. + */ + +char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf); + + +/* + * Check if accessing an interface has potential side effects. + * Currently "data" interfaces have side effects and "control" + * interfaces do not. Returns 1 if there are side effects, 0 if not, + * and XTENSA_UNDEFINED on error. + */ + +int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf); + + +/* + * Some interfaces may be related such that accessing one interface + * has side effects on a set of related interfaces. The interfaces + * are partitioned into equivalence classes of related interfaces, and + * each class is assigned a unique identifier number. This function + * returns the class identifier for an interface, or XTENSA_UNDEFINED + * on error. These identifiers can be compared to determine if two + * interfaces are related; the specific values of the identifiers have + * no particular meaning otherwise. + */ + +int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf); + + +/* Functional Units. */ + +/* + * Find a functional unit by name. The return value is XTENSA_UNDEFINED if + * the specified unit is not found. + */ + +xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname); + + +/* Get the name of a functional unit. Returns null on error. */ + +const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun); + + +/* + * Functional units may be replicated. See how many instances of a + * particular function unit exist. Returns XTENSA_UNDEFINED on error. + */ + +int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun); + + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ diff --git a/target/xtensa/Makefile.objs b/target/xtensa/Makefile.objs index 481de91973..0429706680 100644 --- a/target/xtensa/Makefile.objs +++ b/target/xtensa/Makefile.objs @@ -3,5 +3,6 @@ obj-y += core-dc232b.o obj-y += core-dc233c.o obj-y += core-fsf.o obj-$(CONFIG_SOFTMMU) += monitor.o +obj-y += xtensa-isa.o obj-y += translate.o op_helper.o helper.o cpu.o obj-y += gdbstub.o diff --git a/target/xtensa/xtensa-isa-internal.h b/target/xtensa/xtensa-isa-internal.h new file mode 100644 index 0000000000..c29295ff96 --- /dev/null +++ b/target/xtensa/xtensa-isa-internal.h @@ -0,0 +1,231 @@ +/* Internal definitions for the Xtensa ISA library. + * + * Copyright (c) 2004-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_ISA_INTERNAL_H +#define XTENSA_ISA_INTERNAL_H + +#ifndef uint32 +#define uint32 uint32_t +#endif + +/* Flags. */ + +#define XTENSA_OPERAND_IS_REGISTER 0x00000001 +#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002 +#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004 +#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008 + +#define XTENSA_OPCODE_IS_BRANCH 0x00000001 +#define XTENSA_OPCODE_IS_JUMP 0x00000002 +#define XTENSA_OPCODE_IS_LOOP 0x00000004 +#define XTENSA_OPCODE_IS_CALL 0x00000008 + +#define XTENSA_STATE_IS_EXPORTED 0x00000001 +#define XTENSA_STATE_IS_SHARED_OR 0x00000002 + +#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001 + +/* Function pointer typedefs */ +typedef void (*xtensa_format_encode_fn)(xtensa_insnbuf); +typedef void (*xtensa_get_slot_fn)(const xtensa_insnbuf, xtensa_insnbuf); +typedef void (*xtensa_set_slot_fn)(xtensa_insnbuf, const xtensa_insnbuf); +typedef int (*xtensa_opcode_decode_fn)(const xtensa_insnbuf); +typedef uint32_t (*xtensa_get_field_fn)(const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn)(xtensa_insnbuf, uint32_t); +typedef int (*xtensa_immed_decode_fn)(uint32_t *); +typedef int (*xtensa_immed_encode_fn)(uint32_t *); +typedef int (*xtensa_do_reloc_fn)(uint32_t *, uint32_t); +typedef int (*xtensa_undo_reloc_fn)(uint32_t *, uint32_t); +typedef void (*xtensa_opcode_encode_fn)(xtensa_insnbuf); +typedef int (*xtensa_format_decode_fn)(const xtensa_insnbuf); +typedef int (*xtensa_length_decode_fn)(const unsigned char *); + +typedef struct xtensa_format_internal_struct { + const char *name; /* Instruction format name. */ + int length; /* Instruction length in bytes. */ + xtensa_format_encode_fn encode_fn; + int num_slots; + int *slot_id; /* Array[num_slots] of slot IDs. */ +} xtensa_format_internal; + +typedef struct xtensa_slot_internal_struct { + const char *name; /* Not necessarily unique. */ + const char *format; + int position; + xtensa_get_slot_fn get_fn; + xtensa_set_slot_fn set_fn; + xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */ + xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */ + xtensa_opcode_decode_fn opcode_decode_fn; + const char *nop_name; +} xtensa_slot_internal; + +typedef struct xtensa_operand_internal_struct { + const char *name; + int field_id; + xtensa_regfile regfile; /* Register file. */ + int num_regs; /* Usually 1; 2 for reg pairs, etc. */ + uint32_t flags; /* See XTENSA_OPERAND_* flags. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + +typedef struct xtensa_arg_internal_struct { + union { + int operand_id; /* For normal operands. */ + xtensa_state state; /* For stateOperands. */ + } u; + char inout; /* Direction: 'i', 'o', or 'm'. */ +} xtensa_arg_internal; + +typedef struct xtensa_iclass_internal_struct { + int num_operands; /* Size of "operands" array. */ + xtensa_arg_internal *operands; /* Array[num_operands]. */ + + int num_stateOperands; /* Size of "stateOperands" array. */ + xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */ + + int num_interfaceOperands; /* Size of "interfaceOperands". */ + xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */ +} xtensa_iclass_internal; + +typedef struct xtensa_opcode_internal_struct { + const char *name; /* Opcode mnemonic. */ + int iclass_id; /* Iclass for this opcode. */ + uint32_t flags; /* See XTENSA_OPCODE_* flags. */ + xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */ + int num_funcUnit_uses; /* Number of funcUnit_use entries. */ + xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */ +} xtensa_opcode_internal; + +typedef struct xtensa_regfile_internal_struct { + const char *name; /* Full name of the regfile. */ + const char *shortname; /* Abbreviated name. */ + xtensa_regfile parent; /* View parent (or identity). */ + int num_bits; /* Width of the registers. */ + int num_entries; /* Number of registers. */ +} xtensa_regfile_internal; + +typedef struct xtensa_interface_internal_struct { + const char *name; /* Interface name. */ + int num_bits; /* Width of the interface. */ + uint32_t flags; /* See XTENSA_INTERFACE_* flags. */ + int class_id; /* Class of related interfaces. */ + char inout; /* "i" or "o". */ +} xtensa_interface_internal; + +typedef struct xtensa_funcUnit_internal_struct { + const char *name; /* Functional unit name. */ + int num_copies; /* Number of instances. */ +} xtensa_funcUnit_internal; + +typedef struct xtensa_state_internal_struct { + const char *name; /* State name. */ + int num_bits; /* Number of state bits. */ + uint32_t flags; /* See XTENSA_STATE_* flags. */ +} xtensa_state_internal; + +typedef struct xtensa_sysreg_internal_struct { + const char *name; /* Register name. */ + int number; /* Register number. */ + int is_user; /* Non-zero if a "user register". */ +} xtensa_sysreg_internal; + +typedef struct xtensa_lookup_entry_struct { + const char *key; + union { + xtensa_opcode opcode; /* Internal opcode number. */ + xtensa_sysreg sysreg; /* Internal sysreg number. */ + xtensa_state state; /* Internal state number. */ + xtensa_interface intf; /* Internal interface number. */ + xtensa_funcUnit fun; /* Internal funcUnit number. */ + } u; +} xtensa_lookup_entry; + +typedef struct xtensa_isa_internal_struct { + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + + int num_formats; + xtensa_format_internal *formats; + xtensa_format_decode_fn format_decode_fn; + xtensa_length_decode_fn length_decode_fn; + + int num_slots; + xtensa_slot_internal *slots; + + int num_fields; + + int num_operands; + xtensa_operand_internal *operands; + + int num_iclasses; + xtensa_iclass_internal *iclasses; + + int num_opcodes; + xtensa_opcode_internal *opcodes; + xtensa_lookup_entry *opname_lookup_table; + + int num_regfiles; + xtensa_regfile_internal *regfiles; + + int num_states; + xtensa_state_internal *states; + xtensa_lookup_entry *state_lookup_table; + + int num_sysregs; + xtensa_sysreg_internal *sysregs; + xtensa_lookup_entry *sysreg_lookup_table; + + /* + * The current Xtensa ISA only supports 256 of each kind of sysreg so + * we can get away with implementing lookups with tables indexed by + * the register numbers. If we ever allow larger sysreg numbers, this + * may have to be reimplemented. The first entry in the following + * arrays corresponds to "special" registers and the second to "user" + * registers. + */ + int max_sysreg_num[2]; + xtensa_sysreg *sysreg_table[2]; + + int num_interfaces; + xtensa_interface_internal *interfaces; + xtensa_lookup_entry *interface_lookup_table; + + int num_funcUnits; + xtensa_funcUnit_internal *funcUnits; + xtensa_lookup_entry *funcUnit_lookup_table; + + int num_stages; /* Number of pipe stages. */ +} xtensa_isa_internal; + +int xtensa_isa_name_compare(const void *, const void *); + +extern xtensa_isa_status xtisa_errno; +extern char xtisa_error_msg[]; + +#endif /* !XTENSA_ISA_INTERNAL_H */ diff --git a/target/xtensa/xtensa-isa.c b/target/xtensa/xtensa-isa.c new file mode 100644 index 0000000000..e0076a694f --- /dev/null +++ b/target/xtensa/xtensa-isa.c @@ -0,0 +1,1745 @@ +/* Configurable Xtensa ISA support. + * + * Copyright (c) 2001-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include "xtensa-isa.h" +#include "xtensa-isa-internal.h" + +xtensa_isa_status xtisa_errno; +char xtisa_error_msg[1024]; + + +xtensa_isa_status xtensa_isa_errno(xtensa_isa isa __attribute__ ((unused))) +{ + return xtisa_errno; +} + + +char *xtensa_isa_error_msg(xtensa_isa isa __attribute__ ((unused))) +{ + return xtisa_error_msg; +} + + +#define CHECK_ALLOC(MEM, ERRVAL) \ + do { \ + if ((MEM) == 0) { \ + xtisa_errno = xtensa_isa_out_of_memory; \ + strcpy(xtisa_error_msg, "out of memory"); \ + return ERRVAL; \ + } \ + } while (0) + +#define CHECK_ALLOC_FOR_INIT(MEM, ERRVAL, ERRNO_P, ERROR_MSG_P) \ + do { \ + if ((MEM) == 0) { \ + xtisa_errno = xtensa_isa_out_of_memory; \ + strcpy(xtisa_error_msg, "out of memory"); \ + if (ERRNO_P) { \ + *(ERRNO_P) = xtisa_errno; \ + } \ + if (ERROR_MSG_P) { \ + *(ERROR_MSG_P) = xtisa_error_msg; \ + } \ + return ERRVAL; \ + } \ + } while (0) + + +/* Instruction buffers. */ + +int xtensa_insnbuf_size(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->insnbuf_size; +} + + +xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa) +{ + xtensa_insnbuf result = (xtensa_insnbuf) + malloc(xtensa_insnbuf_size(isa) * sizeof(xtensa_insnbuf_word)); + + CHECK_ALLOC(result, 0); + return result; +} + + +void xtensa_insnbuf_free(xtensa_isa isa __attribute__ ((unused)), + xtensa_insnbuf buf) +{ + free(buf); +} + + +/* + * Given , the index of a byte in a xtensa_insnbuf, our + * internal representation of a xtensa instruction word, return the index of + * its word and the bit index of its low order byte in the xtensa_insnbuf. + */ + +static inline int byte_to_word_index(int byte_index) +{ + return byte_index / sizeof(xtensa_insnbuf_word); +} + + +static inline int byte_to_bit_index(int byte_index) +{ + return (byte_index & 0x3) * 8; +} + + +/* + * Copy an instruction in the 32-bit words pointed at by "insn" to + * characters pointed at by "cp". This is more complicated than you + * might think because we want 16-bit instructions in bytes 2 & 3 for + * big-endian configurations. This function allows us to specify + * which byte in "insn" to start with and which way to increment, + * allowing trivial implementation for both big- and little-endian + * configurations....and it seems to make pretty good code for + * both. + */ + +int xtensa_insnbuf_to_chars(xtensa_isa isa, + const xtensa_insnbuf insn, + unsigned char *cp, + int num_chars) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int insn_size = xtensa_isa_maxlength(isa); + int fence_post, start, increment, i, byte_count; + xtensa_format fmt; + + if (num_chars == 0) { + num_chars = insn_size; + } + + if (intisa->is_big_endian) { + start = insn_size - 1; + increment = -1; + } else { + start = 0; + increment = 1; + } + + /* + * Find the instruction format. Do nothing if the buffer does not contain + * a valid instruction since we need to know how many bytes to copy. + */ + fmt = xtensa_format_decode(isa, insn); + if (fmt == XTENSA_UNDEFINED) { + return XTENSA_UNDEFINED; + } + + byte_count = xtensa_format_length(isa, fmt); + if (byte_count == XTENSA_UNDEFINED) { + return XTENSA_UNDEFINED; + } + + if (byte_count > num_chars) { + xtisa_errno = xtensa_isa_buffer_overflow; + strcpy(xtisa_error_msg, "output buffer too small for instruction"); + return XTENSA_UNDEFINED; + } + + fence_post = start + (byte_count * increment); + + for (i = start; i != fence_post; i += increment, ++cp) { + int word_inx = byte_to_word_index(i); + int bit_inx = byte_to_bit_index(i); + + *cp = (insn[word_inx] >> bit_inx) & 0xff; + } + + return byte_count; +} + + +/* + * Inward conversion from byte stream to xtensa_insnbuf. See + * xtensa_insnbuf_to_chars for a discussion of why this is complicated + * by endianness. + */ + +void xtensa_insnbuf_from_chars(xtensa_isa isa, + xtensa_insnbuf insn, + const unsigned char *cp, + int num_chars) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int max_size, insn_size, fence_post, start, increment, i; + + max_size = xtensa_isa_maxlength(isa); + + /* Decode the instruction length so we know how many bytes to read. */ + insn_size = (intisa->length_decode_fn)(cp); + if (insn_size == XTENSA_UNDEFINED) { + /* + * This should never happen when the byte stream contains a + * valid instruction. Just read the maximum number of bytes.... + */ + insn_size = max_size; + } + + if (num_chars == 0 || num_chars > insn_size) { + num_chars = insn_size; + } + + if (intisa->is_big_endian) { + start = max_size - 1; + increment = -1; + } else { + start = 0; + increment = 1; + } + + fence_post = start + (num_chars * increment); + memset(insn, 0, xtensa_insnbuf_size(isa) * sizeof(xtensa_insnbuf_word)); + + for (i = start; i != fence_post; i += increment, ++cp) { + int word_inx = byte_to_word_index(i); + int bit_inx = byte_to_bit_index(i); + + insn[word_inx] |= (*cp & 0xff) << bit_inx; + } +} + + +/* ISA information. */ + +xtensa_isa xtensa_isa_init(void *xtensa_modules, xtensa_isa_status *errno_p, + char **error_msg_p) +{ + xtensa_isa_internal *isa = xtensa_modules; + int n, is_user; + + /* Set up the opcode name lookup table. */ + isa->opname_lookup_table = + malloc(isa->num_opcodes * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->opname_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_opcodes; n++) { + isa->opname_lookup_table[n].key = isa->opcodes[n].name; + isa->opname_lookup_table[n].u.opcode = n; + } + qsort(isa->opname_lookup_table, isa->num_opcodes, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the state name lookup table. */ + isa->state_lookup_table = + malloc(isa->num_states * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->state_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_states; n++) { + isa->state_lookup_table[n].key = isa->states[n].name; + isa->state_lookup_table[n].u.state = n; + } + qsort(isa->state_lookup_table, isa->num_states, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the sysreg name lookup table. */ + isa->sysreg_lookup_table = + malloc(isa->num_sysregs * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->sysreg_lookup_table, NULL, errno_p, error_msg_p); + for (n = 0; n < isa->num_sysregs; n++) { + isa->sysreg_lookup_table[n].key = isa->sysregs[n].name; + isa->sysreg_lookup_table[n].u.sysreg = n; + } + qsort(isa->sysreg_lookup_table, isa->num_sysregs, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the user & system sysreg number tables. */ + for (is_user = 0; is_user < 2; is_user++) { + isa->sysreg_table[is_user] = + malloc((isa->max_sysreg_num[is_user] + 1) * sizeof(xtensa_sysreg)); + CHECK_ALLOC_FOR_INIT(isa->sysreg_table[is_user], NULL, + errno_p, error_msg_p); + + for (n = 0; n <= isa->max_sysreg_num[is_user]; n++) { + isa->sysreg_table[is_user][n] = XTENSA_UNDEFINED; + } + } + for (n = 0; n < isa->num_sysregs; n++) { + xtensa_sysreg_internal *sreg = &isa->sysregs[n]; + is_user = sreg->is_user; + + if (sreg->number >= 0) { + isa->sysreg_table[is_user][sreg->number] = n; + } + } + + /* Set up the interface lookup table. */ + isa->interface_lookup_table = + malloc(isa->num_interfaces * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->interface_lookup_table, NULL, errno_p, + error_msg_p); + for (n = 0; n < isa->num_interfaces; n++) { + isa->interface_lookup_table[n].key = isa->interfaces[n].name; + isa->interface_lookup_table[n].u.intf = n; + } + qsort(isa->interface_lookup_table, isa->num_interfaces, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + /* Set up the funcUnit lookup table. */ + isa->funcUnit_lookup_table = + malloc(isa->num_funcUnits * sizeof(xtensa_lookup_entry)); + CHECK_ALLOC_FOR_INIT(isa->funcUnit_lookup_table, NULL, errno_p, + error_msg_p); + for (n = 0; n < isa->num_funcUnits; n++) { + isa->funcUnit_lookup_table[n].key = isa->funcUnits[n].name; + isa->funcUnit_lookup_table[n].u.fun = n; + } + qsort(isa->funcUnit_lookup_table, isa->num_funcUnits, + sizeof(xtensa_lookup_entry), xtensa_isa_name_compare); + + isa->insnbuf_size = ((isa->insn_size + sizeof(xtensa_insnbuf_word) - 1) / + sizeof(xtensa_insnbuf_word)); + isa->num_stages = XTENSA_UNDEFINED; + + return (xtensa_isa)isa; +} + + +void xtensa_isa_free(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + /* + * With this version of the code, the xtensa_isa structure is not + * dynamically allocated, so this function is not essential. Free + * the memory allocated by xtensa_isa_init and restore the xtensa_isa + * structure to its initial state. + */ + + if (intisa->opname_lookup_table) { + free(intisa->opname_lookup_table); + intisa->opname_lookup_table = 0; + } + + if (intisa->state_lookup_table) { + free(intisa->state_lookup_table); + intisa->state_lookup_table = 0; + } + + if (intisa->sysreg_lookup_table) { + free(intisa->sysreg_lookup_table); + intisa->sysreg_lookup_table = 0; + } + for (n = 0; n < 2; n++) { + if (intisa->sysreg_table[n]) { + free(intisa->sysreg_table[n]); + intisa->sysreg_table[n] = 0; + } + } + + if (intisa->interface_lookup_table) { + free(intisa->interface_lookup_table); + intisa->interface_lookup_table = 0; + } + + if (intisa->funcUnit_lookup_table) { + free(intisa->funcUnit_lookup_table); + intisa->funcUnit_lookup_table = 0; + } +} + + +int xtensa_isa_name_compare(const void *v1, const void *v2) +{ + xtensa_lookup_entry *e1 = (xtensa_lookup_entry *)v1; + xtensa_lookup_entry *e2 = (xtensa_lookup_entry *)v2; + + return strcasecmp(e1->key, e2->key); +} + + +int xtensa_isa_maxlength(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->insn_size; +} + + +int xtensa_isa_length_from_chars(xtensa_isa isa, const unsigned char *cp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return (intisa->length_decode_fn)(cp); +} + + +int xtensa_isa_num_pipe_stages(xtensa_isa isa) +{ + xtensa_opcode opcode; + xtensa_funcUnit_use *use; + int num_opcodes, num_uses; + int i, stage, max_stage; + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + /* Only compute the value once. */ + if (intisa->num_stages != XTENSA_UNDEFINED) { + return intisa->num_stages; + } + + max_stage = -1; + + num_opcodes = xtensa_isa_num_opcodes(isa); + for (opcode = 0; opcode < num_opcodes; opcode++) { + num_uses = xtensa_opcode_num_funcUnit_uses(isa, opcode); + for (i = 0; i < num_uses; i++) { + use = xtensa_opcode_funcUnit_use(isa, opcode, i); + stage = use->stage; + if (stage > max_stage) { + max_stage = stage; + } + } + } + + intisa->num_stages = max_stage + 1; + return intisa->num_states; +} + + +int xtensa_isa_num_formats(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_formats; +} + + +int xtensa_isa_num_opcodes(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_opcodes; +} + + +int xtensa_isa_num_regfiles(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_regfiles; +} + + +int xtensa_isa_num_states(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_states; +} + + +int xtensa_isa_num_sysregs(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_sysregs; +} + + +int xtensa_isa_num_interfaces(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_interfaces; +} + + +int xtensa_isa_num_funcUnits(xtensa_isa isa) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + return intisa->num_funcUnits; +} + + +/* Instruction formats. */ + + +#define CHECK_FORMAT(INTISA, FMT, ERRVAL) \ + do { \ + if ((FMT) < 0 || (FMT) >= (INTISA)->num_formats) { \ + xtisa_errno = xtensa_isa_bad_format; \ + strcpy(xtisa_error_msg, "invalid format specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +#define CHECK_SLOT(INTISA, FMT, SLOT, ERRVAL) \ + do { \ + if ((SLOT) < 0 || (SLOT) >= (INTISA)->formats[FMT].num_slots) { \ + xtisa_errno = xtensa_isa_bad_slot; \ + strcpy(xtisa_error_msg, "invalid slot specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +const char *xtensa_format_name(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, NULL); + return intisa->formats[fmt].name; +} + + +xtensa_format xtensa_format_lookup(xtensa_isa isa, const char *fmtname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int fmt; + + if (!fmtname || !*fmtname) { + xtisa_errno = xtensa_isa_bad_format; + strcpy(xtisa_error_msg, "invalid format name"); + return XTENSA_UNDEFINED; + } + + for (fmt = 0; fmt < intisa->num_formats; fmt++) { + if (strcasecmp(fmtname, intisa->formats[fmt].name) == 0) { + return fmt; + } + } + + xtisa_errno = xtensa_isa_bad_format; + sprintf(xtisa_error_msg, "format \"%s\" not recognized", fmtname); + return XTENSA_UNDEFINED; +} + + +xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_format fmt; + + fmt = (intisa->format_decode_fn)(insn); + if (fmt != XTENSA_UNDEFINED) { + return fmt; + } + + xtisa_errno = xtensa_isa_bad_format; + strcpy(xtisa_error_msg, "cannot decode instruction format"); + return XTENSA_UNDEFINED; +} + + +int xtensa_format_encode(xtensa_isa isa, xtensa_format fmt, + xtensa_insnbuf insn) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, -1); + (*intisa->formats[fmt].encode_fn)(insn); + return 0; +} + + +int xtensa_format_length(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + return intisa->formats[fmt].length; +} + + +int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + return intisa->formats[fmt].num_slots; +} + + +xtensa_opcode xtensa_format_slot_nop_opcode(xtensa_isa isa, xtensa_format fmt, + int slot) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + CHECK_SLOT(intisa, fmt, slot, XTENSA_UNDEFINED); + + slot_id = intisa->formats[fmt].slot_id[slot]; + return xtensa_opcode_lookup(isa, intisa->slots[slot_id].nop_name); +} + + +int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf insn, xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + (*intisa->slots[slot_id].get_fn)(insn, slotbuf); + return 0; +} + + +int xtensa_format_set_slot(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf insn, const xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + (*intisa->slots[slot_id].set_fn)(insn, slotbuf); + return 0; +} + + +/* Opcode information. */ + + +#define CHECK_OPCODE(INTISA, OPC, ERRVAL) \ + do { \ + if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) { \ + xtisa_errno = xtensa_isa_bad_opcode; \ + strcpy(xtisa_error_msg, "invalid opcode specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_opcode xtensa_opcode_lookup(xtensa_isa isa, const char *opname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!opname || !*opname) { + xtisa_errno = xtensa_isa_bad_opcode; + strcpy(xtisa_error_msg, "invalid opcode name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_opcodes != 0) { + entry.key = opname; + result = bsearch(&entry, intisa->opname_lookup_table, + intisa->num_opcodes, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_opcode; + sprintf(xtisa_error_msg, "opcode \"%s\" not recognized", opname); + return XTENSA_UNDEFINED; + } + + return result->u.opcode; +} + + +xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + xtensa_opcode opc; + + CHECK_FORMAT(intisa, fmt, XTENSA_UNDEFINED); + CHECK_SLOT(intisa, fmt, slot, XTENSA_UNDEFINED); + + slot_id = intisa->formats[fmt].slot_id[slot]; + + opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); + if (opc != XTENSA_UNDEFINED) { + return opc; + } + + xtisa_errno = xtensa_isa_bad_opcode; + strcpy(xtisa_error_msg, "cannot decode opcode"); + return XTENSA_UNDEFINED; +} + + +int xtensa_opcode_encode(xtensa_isa isa, xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int slot_id; + xtensa_opcode_encode_fn encode_fn; + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + CHECK_OPCODE(intisa, opc, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + encode_fn = intisa->opcodes[opc].encode_fns[slot_id]; + if (!encode_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "opcode \"%s\" is not allowed in slot %d of format \"%s\"", + intisa->opcodes[opc].name, slot, intisa->formats[fmt].name); + return -1; + } + (*encode_fn)(slotbuf); + return 0; +} + + +const char *xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, NULL); + return intisa->opcodes[opc].name; +} + + +int xtensa_opcode_is_branch(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_BRANCH) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_jump(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_JUMP) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_loop(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_LOOP) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_is_call(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + if ((intisa->opcodes[opc].flags & XTENSA_OPCODE_IS_CALL) != 0) { + return 1; + } + return 0; +} + + +int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_operands; +} + + +int xtensa_opcode_num_stateOperands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_stateOperands; +} + + +int xtensa_opcode_num_interfaceOperands(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + return intisa->iclasses[iclass_id].num_interfaceOperands; +} + + +int xtensa_opcode_num_funcUnit_uses(xtensa_isa isa, xtensa_opcode opc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + return intisa->opcodes[opc].num_funcUnit_uses; +} + + +xtensa_funcUnit_use *xtensa_opcode_funcUnit_use(xtensa_isa isa, + xtensa_opcode opc, int u) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_OPCODE(intisa, opc, NULL); + if (u < 0 || u >= intisa->opcodes[opc].num_funcUnit_uses) { + xtisa_errno = xtensa_isa_bad_funcUnit; + sprintf(xtisa_error_msg, "invalid functional unit use number (%d); " + "opcode \"%s\" has %d", u, intisa->opcodes[opc].name, + intisa->opcodes[opc].num_funcUnit_uses); + return NULL; + } + return &intisa->opcodes[opc].funcUnit_uses[u]; +} + + +/* Operand information. */ + + +#define CHECK_OPERAND(INTISA, OPC, ICLASS, OPND, ERRVAL) \ + do { \ + if ((OPND) < 0 || (OPND) >= (ICLASS)->num_operands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, "invalid operand number (%d); " \ + "opcode \"%s\" has %d operands", (OPND), \ + (INTISA)->opcodes[(OPC)].name, (ICLASS)->num_operands); \ + return ERRVAL; \ + } \ + } while (0) + + +static xtensa_operand_internal *get_operand(xtensa_isa_internal *intisa, + xtensa_opcode opc, int opnd) +{ + xtensa_iclass_internal *iclass; + int iclass_id, operand_id; + + CHECK_OPCODE(intisa, opc, NULL); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, NULL); + operand_id = iclass->operands[opnd].u.operand_id; + return &intisa->operands[operand_id]; +} + + +const char *xtensa_operand_name(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return NULL; + } + return intop->name; +} + + +int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id, operand_id; + xtensa_operand_internal *intop; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, XTENSA_UNDEFINED); + + /* Special case for "sout" operands. */ + if (iclass->operands[opnd].inout == 's') { + return 0; + } + + operand_id = iclass->operands[opnd].u.operand_id; + intop = &intisa->operands[operand_id]; + + if ((intop->flags & XTENSA_OPERAND_IS_INVISIBLE) == 0) { + return 1; + } + return 0; +} + + +char xtensa_operand_inout(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + char inout; + + CHECK_OPCODE(intisa, opc, 0); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_OPERAND(intisa, opc, iclass, opnd, 0); + inout = iclass->operands[opnd].inout; + + /* Special case for "sout" and "_sin" operands. */ + if (inout == 's') { + return 'o'; + } + if (inout == 't') { + return 'i'; + } + return inout; +} + + +int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + const xtensa_insnbuf slotbuf, uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + int slot_id; + xtensa_get_field_fn get_fn; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "implicit operand has no field"); + return -1; + } + get_fn = intisa->slots[slot_id].get_field_fns[intop->field_id]; + if (!get_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "operand \"%s\" does not exist in slot %d of format \"%s\"", + intop->name, slot, intisa->formats[fmt].name); + return -1; + } + *valp = (*get_fn)(slotbuf); + return 0; +} + + +int xtensa_operand_set_field(xtensa_isa isa, xtensa_opcode opc, int opnd, + xtensa_format fmt, int slot, + xtensa_insnbuf slotbuf, uint32_t val) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + int slot_id; + xtensa_set_field_fn set_fn; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + CHECK_FORMAT(intisa, fmt, -1); + CHECK_SLOT(intisa, fmt, slot, -1); + + slot_id = intisa->formats[fmt].slot_id[slot]; + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "implicit operand has no field"); + return -1; + } + set_fn = intisa->slots[slot_id].set_field_fns[intop->field_id]; + if (!set_fn) { + xtisa_errno = xtensa_isa_wrong_slot; + sprintf(xtisa_error_msg, + "operand \"%s\" does not exist in slot %d of format \"%s\"", + intop->name, slot, intisa->formats[fmt].name); + return -1; + } + (*set_fn)(slotbuf, val); + return 0; +} + + +int xtensa_operand_encode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + uint32_t test_val, orig_val; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if (!intop->encode) { + /* + * This is a default operand for a field. How can we tell if the + * value fits in the field? Write the value into the field, + * read it back, and then make sure we get the same value. + */ + static xtensa_insnbuf tmpbuf; + int slot_id; + + if (!tmpbuf) { + tmpbuf = xtensa_insnbuf_alloc(isa); + CHECK_ALLOC(tmpbuf, -1); + } + + /* + * A default operand is always associated with a field, + * but check just to be sure.... + */ + if (intop->field_id == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand has no field"); + return -1; + } + + /* Find some slot that includes the field. */ + for (slot_id = 0; slot_id < intisa->num_slots; slot_id++) { + xtensa_get_field_fn get_fn = + intisa->slots[slot_id].get_field_fns[intop->field_id]; + xtensa_set_field_fn set_fn = + intisa->slots[slot_id].set_field_fns[intop->field_id]; + + if (get_fn && set_fn) { + (*set_fn)(tmpbuf, *valp); + return (*get_fn)(tmpbuf) != *valp; + } + } + + /* Couldn't find any slot containing the field.... */ + xtisa_errno = xtensa_isa_no_field; + strcpy(xtisa_error_msg, "field does not exist in any slot"); + return -1; + } + + /* + * Encode the value. In some cases, the encoding function may detect + * errors, but most of the time the only way to determine if the value + * was successfully encoded is to decode it and check if it matches + * the original value. + */ + orig_val = *valp; + if ((*intop->encode)(valp) || + (test_val = *valp, (*intop->decode)(&test_val)) || + test_val != orig_val) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, "cannot encode operand value 0x%08x", *valp); + return -1; + } + + return 0; +} + + +int xtensa_operand_decode(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + /* Use identity function for "default" operands. */ + if (!intop->decode) { + return 0; + } + + if ((*intop->decode)(valp)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, "cannot decode operand value 0x%08x", *valp); + return -1; + } + return 0; +} + + +int xtensa_operand_is_register(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_REGISTER) != 0) { + return 1; + } + return 0; +} + + +xtensa_regfile xtensa_operand_regfile(xtensa_isa isa, xtensa_opcode opc, + int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + return intop->regfile; +} + + +int xtensa_operand_num_regs(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + return intop->num_regs; +} + + +int xtensa_operand_is_known_reg(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_UNKNOWN) == 0) { + return 1; + } + return 0; +} + + +int xtensa_operand_is_PCrelative(xtensa_isa isa, xtensa_opcode opc, int opnd) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return XTENSA_UNDEFINED; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) != 0) { + return 1; + } + return 0; +} + + +int xtensa_operand_do_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) { + return 0; + } + + if (!intop->do_reloc) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand missing do_reloc function"); + return -1; + } + + if ((*intop->do_reloc)(valp, pc)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, + "do_reloc failed for value 0x%08x at PC 0x%08x", *valp, pc); + return -1; + } + + return 0; +} + + +int xtensa_operand_undo_reloc(xtensa_isa isa, xtensa_opcode opc, int opnd, + uint32_t *valp, uint32_t pc) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_operand_internal *intop; + + intop = get_operand(intisa, opc, opnd); + if (!intop) { + return -1; + } + + if ((intop->flags & XTENSA_OPERAND_IS_PCRELATIVE) == 0) { + return 0; + } + + if (!intop->undo_reloc) { + xtisa_errno = xtensa_isa_internal_error; + strcpy(xtisa_error_msg, "operand missing undo_reloc function"); + return -1; + } + + if ((*intop->undo_reloc)(valp, pc)) { + xtisa_errno = xtensa_isa_bad_value; + sprintf(xtisa_error_msg, + "undo_reloc failed for value 0x%08x at PC 0x%08x", *valp, pc); + return -1; + } + + return 0; +} + + +/* State Operands. */ + + +#define CHECK_STATE_OPERAND(INTISA, OPC, ICLASS, STOP, ERRVAL) \ + do { \ + if ((STOP) < 0 || (STOP) >= (ICLASS)->num_stateOperands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, "invalid state operand number (%d); " \ + "opcode \"%s\" has %d state operands", (STOP), \ + (INTISA)->opcodes[(OPC)].name, \ + (ICLASS)->num_stateOperands); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_state xtensa_stateOperand_state(xtensa_isa isa, xtensa_opcode opc, + int stOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_STATE_OPERAND(intisa, opc, iclass, stOp, XTENSA_UNDEFINED); + return iclass->stateOperands[stOp].u.state; +} + + +char xtensa_stateOperand_inout(xtensa_isa isa, xtensa_opcode opc, int stOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, 0); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_STATE_OPERAND(intisa, opc, iclass, stOp, 0); + return iclass->stateOperands[stOp].inout; +} + + +/* Interface Operands. */ + + +#define CHECK_INTERFACE_OPERAND(INTISA, OPC, ICLASS, IFOP, ERRVAL) \ + do { \ + if ((IFOP) < 0 || (IFOP) >= (ICLASS)->num_interfaceOperands) { \ + xtisa_errno = xtensa_isa_bad_operand; \ + sprintf(xtisa_error_msg, \ + "invalid interface operand number (%d); " \ + "opcode \"%s\" has %d interface operands", (IFOP), \ + (INTISA)->opcodes[(OPC)].name, \ + (ICLASS)->num_interfaceOperands); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_interface xtensa_interfaceOperand_interface(xtensa_isa isa, + xtensa_opcode opc, + int ifOp) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_iclass_internal *iclass; + int iclass_id; + + CHECK_OPCODE(intisa, opc, XTENSA_UNDEFINED); + iclass_id = intisa->opcodes[opc].iclass_id; + iclass = &intisa->iclasses[iclass_id]; + CHECK_INTERFACE_OPERAND(intisa, opc, iclass, ifOp, XTENSA_UNDEFINED); + return iclass->interfaceOperands[ifOp]; +} + + +/* Register Files. */ + + +#define CHECK_REGFILE(INTISA, RF, ERRVAL) \ + do { \ + if ((RF) < 0 || (RF) >= (INTISA)->num_regfiles) { \ + xtisa_errno = xtensa_isa_bad_regfile; \ + strcpy(xtisa_error_msg, "invalid regfile specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_regfile xtensa_regfile_lookup(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_regfile; + strcpy(xtisa_error_msg, "invalid regfile name"); + return XTENSA_UNDEFINED; + } + + /* The expected number of regfiles is small; use a linear search. */ + for (n = 0; n < intisa->num_regfiles; n++) { + if (!strcmp(intisa->regfiles[n].name, name)) { + return n; + } + } + + xtisa_errno = xtensa_isa_bad_regfile; + sprintf(xtisa_error_msg, "regfile \"%s\" not recognized", name); + return XTENSA_UNDEFINED; +} + + +xtensa_regfile xtensa_regfile_lookup_shortname(xtensa_isa isa, + const char *shortname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + int n; + + if (!shortname || !*shortname) { + xtisa_errno = xtensa_isa_bad_regfile; + strcpy(xtisa_error_msg, "invalid regfile shortname"); + return XTENSA_UNDEFINED; + } + + /* The expected number of regfiles is small; use a linear search. */ + for (n = 0; n < intisa->num_regfiles; n++) { + /* + * Ignore regfile views since they always have the same shortnames + * as their parents. + */ + if (intisa->regfiles[n].parent != n) { + continue; + } + if (!strcmp(intisa->regfiles[n].shortname, shortname)) { + return n; + } + } + + xtisa_errno = xtensa_isa_bad_regfile; + sprintf(xtisa_error_msg, "regfile shortname \"%s\" not recognized", + shortname); + return XTENSA_UNDEFINED; +} + + +const char *xtensa_regfile_name(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, NULL); + return intisa->regfiles[rf].name; +} + + +const char *xtensa_regfile_shortname(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, NULL); + return intisa->regfiles[rf].shortname; +} + + +xtensa_regfile xtensa_regfile_view_parent(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].parent; +} + + +int xtensa_regfile_num_bits(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].num_bits; +} + + +int xtensa_regfile_num_entries(xtensa_isa isa, xtensa_regfile rf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_REGFILE(intisa, rf, XTENSA_UNDEFINED); + return intisa->regfiles[rf].num_entries; +} + + +/* Processor States. */ + + +#define CHECK_STATE(INTISA, ST, ERRVAL) \ + do { \ + if ((ST) < 0 || (ST) >= (INTISA)->num_states) { \ + xtisa_errno = xtensa_isa_bad_state; \ + strcpy(xtisa_error_msg, "invalid state specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_state xtensa_state_lookup(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_state; + strcpy(xtisa_error_msg, "invalid state name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_states != 0) { + entry.key = name; + result = bsearch(&entry, intisa->state_lookup_table, + intisa->num_states, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_state; + sprintf(xtisa_error_msg, "state \"%s\" not recognized", name); + return XTENSA_UNDEFINED; + } + + return result->u.state; +} + + +const char *xtensa_state_name(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, NULL); + return intisa->states[st].name; +} + + +int xtensa_state_num_bits(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + return intisa->states[st].num_bits; +} + + +int xtensa_state_is_exported(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + if ((intisa->states[st].flags & XTENSA_STATE_IS_EXPORTED) != 0) { + return 1; + } + return 0; +} + + +int xtensa_state_is_shared_or(xtensa_isa isa, xtensa_state st) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_STATE(intisa, st, XTENSA_UNDEFINED); + if ((intisa->states[st].flags & XTENSA_STATE_IS_SHARED_OR) != 0) { + return 1; + } + return 0; +} + + +/* Sysregs. */ + + +#define CHECK_SYSREG(INTISA, SYSREG, ERRVAL) \ + do { \ + if ((SYSREG) < 0 || (SYSREG) >= (INTISA)->num_sysregs) { \ + xtisa_errno = xtensa_isa_bad_sysreg; \ + strcpy(xtisa_error_msg, "invalid sysreg specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_sysreg xtensa_sysreg_lookup(xtensa_isa isa, int num, int is_user) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + if (is_user != 0) { + is_user = 1; + } + + if (num < 0 || num > intisa->max_sysreg_num[is_user] || + intisa->sysreg_table[is_user][num] == XTENSA_UNDEFINED) { + xtisa_errno = xtensa_isa_bad_sysreg; + strcpy(xtisa_error_msg, "sysreg not recognized"); + return XTENSA_UNDEFINED; + } + + return intisa->sysreg_table[is_user][num]; +} + + +xtensa_sysreg xtensa_sysreg_lookup_name(xtensa_isa isa, const char *name) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!name || !*name) { + xtisa_errno = xtensa_isa_bad_sysreg; + strcpy(xtisa_error_msg, "invalid sysreg name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_sysregs != 0) { + entry.key = name; + result = bsearch(&entry, intisa->sysreg_lookup_table, + intisa->num_sysregs, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_sysreg; + sprintf(xtisa_error_msg, "sysreg \"%s\" not recognized", name); + return XTENSA_UNDEFINED; + } + + return result->u.sysreg; +} + + +const char *xtensa_sysreg_name(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, NULL); + return intisa->sysregs[sysreg].name; +} + + +int xtensa_sysreg_number(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); + return intisa->sysregs[sysreg].number; +} + + +int xtensa_sysreg_is_user(xtensa_isa isa, xtensa_sysreg sysreg) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_SYSREG(intisa, sysreg, XTENSA_UNDEFINED); + if (intisa->sysregs[sysreg].is_user) { + return 1; + } + return 0; +} + + +/* Interfaces. */ + + +#define CHECK_INTERFACE(INTISA, INTF, ERRVAL) \ + do { \ + if ((INTF) < 0 || (INTF) >= (INTISA)->num_interfaces) { \ + xtisa_errno = xtensa_isa_bad_interface; \ + strcpy(xtisa_error_msg, "invalid interface specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_interface xtensa_interface_lookup(xtensa_isa isa, const char *ifname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!ifname || !*ifname) { + xtisa_errno = xtensa_isa_bad_interface; + strcpy(xtisa_error_msg, "invalid interface name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_interfaces != 0) { + entry.key = ifname; + result = bsearch(&entry, intisa->interface_lookup_table, + intisa->num_interfaces, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_interface; + sprintf(xtisa_error_msg, "interface \"%s\" not recognized", ifname); + return XTENSA_UNDEFINED; + } + + return result->u.intf; +} + + +const char *xtensa_interface_name(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, NULL); + return intisa->interfaces[intf].name; +} + + +int xtensa_interface_num_bits(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + return intisa->interfaces[intf].num_bits; +} + + +char xtensa_interface_inout(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, 0); + return intisa->interfaces[intf].inout; +} + + +int xtensa_interface_has_side_effect(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + if ((intisa->interfaces[intf].flags & + XTENSA_INTERFACE_HAS_SIDE_EFFECT) != 0) { + return 1; + } + return 0; +} + + +int xtensa_interface_class_id(xtensa_isa isa, xtensa_interface intf) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_INTERFACE(intisa, intf, XTENSA_UNDEFINED); + return intisa->interfaces[intf].class_id; +} + + +/* Functional Units. */ + + +#define CHECK_FUNCUNIT(INTISA, FUN, ERRVAL) \ + do { \ + if ((FUN) < 0 || (FUN) >= (INTISA)->num_funcUnits) { \ + xtisa_errno = xtensa_isa_bad_funcUnit; \ + strcpy(xtisa_error_msg, "invalid functional unit specifier"); \ + return ERRVAL; \ + } \ + } while (0) + + +xtensa_funcUnit xtensa_funcUnit_lookup(xtensa_isa isa, const char *fname) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + xtensa_lookup_entry entry, *result = 0; + + if (!fname || !*fname) { + xtisa_errno = xtensa_isa_bad_funcUnit; + strcpy(xtisa_error_msg, "invalid functional unit name"); + return XTENSA_UNDEFINED; + } + + if (intisa->num_funcUnits != 0) { + entry.key = fname; + result = bsearch(&entry, intisa->funcUnit_lookup_table, + intisa->num_funcUnits, sizeof(xtensa_lookup_entry), + xtensa_isa_name_compare); + } + + if (!result) { + xtisa_errno = xtensa_isa_bad_funcUnit; + sprintf(xtisa_error_msg, + "functional unit \"%s\" not recognized", fname); + return XTENSA_UNDEFINED; + } + + return result->u.fun; +} + + +const char *xtensa_funcUnit_name(xtensa_isa isa, xtensa_funcUnit fun) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FUNCUNIT(intisa, fun, NULL); + return intisa->funcUnits[fun].name; +} + + +int xtensa_funcUnit_num_copies(xtensa_isa isa, xtensa_funcUnit fun) +{ + xtensa_isa_internal *intisa = (xtensa_isa_internal *)isa; + + CHECK_FUNCUNIT(intisa, fun, XTENSA_UNDEFINED); + return intisa->funcUnits[fun].num_copies; +} diff --git a/target/xtensa/xtensa-isa.h b/target/xtensa/xtensa-isa.h new file mode 100644 index 0000000000..d06614c187 --- /dev/null +++ b/target/xtensa/xtensa-isa.h @@ -0,0 +1 @@ +#include -- cgit v1.2.3-55-g7522 From 9d3b155186c2788570f4802700d030c84e0f0746 Mon Sep 17 00:00:00 2001 From: Mao Zhongyi Date: Wed, 22 Nov 2017 11:08:44 +0800 Subject: hw/block: Fix the return type When the function no success value to transmit, it usually make the function return void. It has turned out not to be a success, because it means that the extra local_err variable and error_propagate() will be needed. It leads to cumbersome code, therefore, transmit success/ failure in the return value is worth. So fix the return type of blkconf_apply_backend_options(), blkconf_geometry() and virtio_blk_data_plane_create() to avoid it. Cc: John Snow Cc: Kevin Wolf Cc: Max Reitz Cc: Stefan Hajnoczi Signed-off-by: Mao Zhongyi Reviewed-by: Stefan Hajnoczi Message-id: ac0edc1fc70c4457e5cec94405eb7d1f89f9c2c1.1511317952.git.maozy.fnst@cn.fujitsu.com Signed-off-by: Stefan Hajnoczi --- hw/block/block.c | 15 +++++++++------ hw/block/dataplane/virtio-blk.c | 12 +++++++----- hw/block/dataplane/virtio-blk.h | 2 +- include/hw/block/block.h | 4 ++-- 4 files changed, 19 insertions(+), 14 deletions(-) (limited to 'include/hw') diff --git a/hw/block/block.c b/hw/block/block.c index 27878d0087..b0269c857f 100644 --- a/hw/block/block.c +++ b/hw/block/block.c @@ -51,7 +51,7 @@ void blkconf_blocksizes(BlockConf *conf) } } -void blkconf_apply_backend_options(BlockConf *conf, bool readonly, +bool blkconf_apply_backend_options(BlockConf *conf, bool readonly, bool resizable, Error **errp) { BlockBackend *blk = conf->blk; @@ -76,7 +76,7 @@ void blkconf_apply_backend_options(BlockConf *conf, bool readonly, ret = blk_set_perm(blk, perm, shared_perm, errp); if (ret < 0) { - return; + return false; } switch (conf->wce) { @@ -99,9 +99,11 @@ void blkconf_apply_backend_options(BlockConf *conf, bool readonly, blk_set_enable_write_cache(blk, wce); blk_set_on_error(blk, rerror, werror); + + return true; } -void blkconf_geometry(BlockConf *conf, int *ptrans, +bool blkconf_geometry(BlockConf *conf, int *ptrans, unsigned cyls_max, unsigned heads_max, unsigned secs_max, Error **errp) { @@ -129,15 +131,16 @@ void blkconf_geometry(BlockConf *conf, int *ptrans, if (conf->cyls || conf->heads || conf->secs) { if (conf->cyls < 1 || conf->cyls > cyls_max) { error_setg(errp, "cyls must be between 1 and %u", cyls_max); - return; + return false; } if (conf->heads < 1 || conf->heads > heads_max) { error_setg(errp, "heads must be between 1 and %u", heads_max); - return; + return false; } if (conf->secs < 1 || conf->secs > secs_max) { error_setg(errp, "secs must be between 1 and %u", secs_max); - return; + return false; } } + return true; } diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index 5556f0e64e..f6fc639e88 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -76,7 +76,7 @@ static void notify_guest_bh(void *opaque) } /* Context: QEMU global mutex held */ -void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, +bool virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp) { @@ -91,11 +91,11 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, error_setg(errp, "device is incompatible with iothread " "(transport does not support notifiers)"); - return; + return false; } if (!virtio_device_ioeventfd_enabled(vdev)) { error_setg(errp, "ioeventfd is required for iothread"); - return; + return false; } /* If dataplane is (re-)enabled while the guest is running there could @@ -103,12 +103,12 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, */ if (blk_op_is_blocked(conf->conf.blk, BLOCK_OP_TYPE_DATAPLANE, errp)) { error_prepend(errp, "cannot start virtio-blk dataplane: "); - return; + return false; } } /* Don't try if transport does not support notifiers. */ if (!virtio_device_ioeventfd_enabled(vdev)) { - return; + return false; } s = g_new0(VirtIOBlockDataPlane, 1); @@ -126,6 +126,8 @@ void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, s->batch_notify_vqs = bitmap_new(conf->num_queues); *dataplane = s; + + return true; } /* Context: QEMU global mutex held */ diff --git a/hw/block/dataplane/virtio-blk.h b/hw/block/dataplane/virtio-blk.h index db3f47b173..5e18bb99ae 100644 --- a/hw/block/dataplane/virtio-blk.h +++ b/hw/block/dataplane/virtio-blk.h @@ -19,7 +19,7 @@ typedef struct VirtIOBlockDataPlane VirtIOBlockDataPlane; -void virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, +bool virtio_blk_data_plane_create(VirtIODevice *vdev, VirtIOBlkConf *conf, VirtIOBlockDataPlane **dataplane, Error **errp); void virtio_blk_data_plane_destroy(VirtIOBlockDataPlane *s); diff --git a/include/hw/block/block.h b/include/hw/block/block.h index f3f6e8ef02..64b9298829 100644 --- a/include/hw/block/block.h +++ b/include/hw/block/block.h @@ -72,11 +72,11 @@ static inline unsigned int get_physical_block_exp(BlockConf *conf) /* Configuration helpers */ void blkconf_serial(BlockConf *conf, char **serial); -void blkconf_geometry(BlockConf *conf, int *trans, +bool blkconf_geometry(BlockConf *conf, int *trans, unsigned cyls_max, unsigned heads_max, unsigned secs_max, Error **errp); void blkconf_blocksizes(BlockConf *conf); -void blkconf_apply_backend_options(BlockConf *conf, bool readonly, +bool blkconf_apply_backend_options(BlockConf *conf, bool readonly, bool resizable, Error **errp); /* Hard disk geometry */ -- cgit v1.2.3-55-g7522 From 6040aedddb5f474a9c2304b6a432a652d82b3d3c Mon Sep 17 00:00:00 2001 From: Mark Kanda Date: Mon, 11 Dec 2017 09:16:24 -0600 Subject: virtio-blk: make queue size configurable Depending on the configuration, it can be beneficial to adjust the virtio-blk queue size to something other than the current default of 128. Add a new property to make the queue size configurable. Signed-off-by: Mark Kanda Reviewed-by: Karl Heubaum Reviewed-by: Martin K. Petersen Reviewed-by: Ameya More Message-id: 52e6d742811f10dbd16e996e86cf375b9577c187.1513005190.git.mark.kanda@oracle.com Signed-off-by: Stefan Hajnoczi --- hw/block/virtio-blk.c | 10 +++++++++- include/hw/virtio/virtio-blk.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include/hw') diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c index 41a4ccdede..66ab0b19c8 100644 --- a/hw/block/virtio-blk.c +++ b/hw/block/virtio-blk.c @@ -928,6 +928,13 @@ static void virtio_blk_device_realize(DeviceState *dev, Error **errp) error_setg(errp, "num-queues property must be larger than 0"); return; } + if (!is_power_of_2(conf->queue_size) || + conf->queue_size > VIRTQUEUE_MAX_SIZE) { + error_setg(errp, "invalid queue-size property (%" PRIu16 "), " + "must be a power of 2 (max %d)", + conf->queue_size, VIRTQUEUE_MAX_SIZE); + return; + } blkconf_serial(&conf->conf, &conf->serial); if (!blkconf_apply_backend_options(&conf->conf, @@ -950,7 +957,7 @@ static void virtio_blk_device_realize(DeviceState *dev, Error **errp) s->sector_mask = (s->conf.conf.logical_block_size / BDRV_SECTOR_SIZE) - 1; for (i = 0; i < conf->num_queues; i++) { - virtio_add_queue(vdev, 128, virtio_blk_handle_output); + virtio_add_queue(vdev, conf->queue_size, virtio_blk_handle_output); } virtio_blk_data_plane_create(vdev, conf, &s->dataplane, &err); if (err != NULL) { @@ -1009,6 +1016,7 @@ static Property virtio_blk_properties[] = { DEFINE_PROP_BIT("request-merging", VirtIOBlock, conf.request_merging, 0, true), DEFINE_PROP_UINT16("num-queues", VirtIOBlock, conf.num_queues, 1), + DEFINE_PROP_UINT16("queue-size", VirtIOBlock, conf.queue_size, 128), DEFINE_PROP_LINK("iothread", VirtIOBlock, conf.iothread, TYPE_IOTHREAD, IOThread *), DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/virtio/virtio-blk.h b/include/hw/virtio/virtio-blk.h index d3c8a6fa8c..5117431d96 100644 --- a/include/hw/virtio/virtio-blk.h +++ b/include/hw/virtio/virtio-blk.h @@ -39,6 +39,7 @@ struct VirtIOBlkConf uint32_t config_wce; uint32_t request_merging; uint16_t num_queues; + uint16_t queue_size; }; struct VirtIOBlockDataPlane; -- cgit v1.2.3-55-g7522 From 89be9e99c83095af25ce16907143c31f2959188b Mon Sep 17 00:00:00 2001 From: Cornelia Huck Date: Mon, 18 Dec 2017 19:36:31 +0100 Subject: tpm: move qdev_prop_tpm to hw/tpm/ Building with --disable-tpm yields ../hw/core/qdev-properties-system.o: In function `set_tpm': /home/cohuck/git/qemu/hw/core/qdev-properties-system.c:274: undefined reference to `qemu_find_tpm_be' /home/cohuck/git/qemu/hw/core/qdev-properties-system.c:278: undefined reference to `tpm_backend_init' ../hw/core/qdev-properties-system.o: In function `release_tpm': /home/cohuck/git/qemu/hw/core/qdev-properties-system.c:291: undefined reference to `tpm_backend_reset' Move the implementation of DEFINE_PROP_TPMBE to hw/tpm/ so that it is only built when tpm is actually configured, and build tpm_util in every case. Fixes: 493b78303532 ("qdev: add DEFINE_PROP_TPMBE") Reported-by: Thomas Huth Reviewed-by: Marc-André Lureau Signed-off-by: Cornelia Huck Reviewed-by: Laurent Vivier Signed-off-by: Stefan Berger --- hw/core/qdev-properties-system.c | 64 -------------------------------------- hw/tpm/Makefile.objs | 5 +-- hw/tpm/tpm_util.c | 67 ++++++++++++++++++++++++++++++++++++++++ hw/tpm/tpm_util.h | 3 ++ include/hw/qdev-properties.h | 2 -- 5 files changed, 73 insertions(+), 68 deletions(-) (limited to 'include/hw') diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index c17364655c..ec10da7424 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -21,7 +21,6 @@ #include "net/hub.h" #include "qapi/visitor.h" #include "chardev/char-fe.h" -#include "sysemu/tpm_backend.h" #include "sysemu/iothread.h" static void get_pointer(Object *obj, Visitor *v, Property *prop, @@ -237,69 +236,6 @@ const PropertyInfo qdev_prop_chr = { .release = release_chr, }; -/* --- character device --- */ - -static void get_tpm(Object *obj, Visitor *v, const char *name, void *opaque, - Error **errp) -{ - DeviceState *dev = DEVICE(obj); - TPMBackend **be = qdev_get_prop_ptr(dev, opaque); - char *p; - - p = g_strdup(*be ? (*be)->id : ""); - visit_type_str(v, name, &p, errp); - g_free(p); -} - -static void set_tpm(Object *obj, Visitor *v, const char *name, void *opaque, - Error **errp) -{ - DeviceState *dev = DEVICE(obj); - Error *local_err = NULL; - Property *prop = opaque; - TPMBackend *s, **be = qdev_get_prop_ptr(dev, prop); - char *str; - - if (dev->realized) { - qdev_prop_set_after_realize(dev, name, errp); - return; - } - - visit_type_str(v, name, &str, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - s = qemu_find_tpm_be(str); - if (s == NULL) { - error_setg(errp, "Property '%s.%s' can't find value '%s'", - object_get_typename(obj), prop->name, str); - } else if (tpm_backend_init(s, TPM_IF(obj), errp) == 0) { - *be = s; /* weak reference, avoid cyclic ref */ - } - g_free(str); -} - -static void release_tpm(Object *obj, const char *name, void *opaque) -{ - DeviceState *dev = DEVICE(obj); - Property *prop = opaque; - TPMBackend **be = qdev_get_prop_ptr(dev, prop); - - if (*be) { - tpm_backend_reset(*be); - } -} - -const PropertyInfo qdev_prop_tpm = { - .name = "str", - .description = "ID of a tpm to use as a backend", - .get = get_tpm, - .set = set_tpm, - .release = release_tpm, -}; - /* --- netdev device --- */ static void get_netdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/hw/tpm/Makefile.objs b/hw/tpm/Makefile.objs index 41f0b7a590..7a93b24636 100644 --- a/hw/tpm/Makefile.objs +++ b/hw/tpm/Makefile.objs @@ -1,3 +1,4 @@ +common-obj-y += tpm_util.o common-obj-$(CONFIG_TPM_TIS) += tpm_tis.o -common-obj-$(CONFIG_TPM_PASSTHROUGH) += tpm_passthrough.o tpm_util.o -common-obj-$(CONFIG_TPM_EMULATOR) += tpm_emulator.o tpm_util.o +common-obj-$(CONFIG_TPM_PASSTHROUGH) += tpm_passthrough.o +common-obj-$(CONFIG_TPM_EMULATOR) += tpm_emulator.o diff --git a/hw/tpm/tpm_util.c b/hw/tpm/tpm_util.c index a317243a7e..17cafbe6b3 100644 --- a/hw/tpm/tpm_util.c +++ b/hw/tpm/tpm_util.c @@ -21,9 +21,13 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/visitor.h" #include "tpm_util.h" #include "tpm_int.h" #include "exec/memory.h" +#include "sysemu/tpm_backend.h" +#include "hw/qdev.h" #define DEBUG_TPM 0 @@ -33,6 +37,69 @@ } \ } while (0) +/* tpm backend property */ + +static void get_tpm(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + TPMBackend **be = qdev_get_prop_ptr(dev, opaque); + char *p; + + p = g_strdup(*be ? (*be)->id : ""); + visit_type_str(v, name, &p, errp); + g_free(p); +} + +static void set_tpm(Object *obj, Visitor *v, const char *name, void *opaque, + Error **errp) +{ + DeviceState *dev = DEVICE(obj); + Error *local_err = NULL; + Property *prop = opaque; + TPMBackend *s, **be = qdev_get_prop_ptr(dev, prop); + char *str; + + if (dev->realized) { + qdev_prop_set_after_realize(dev, name, errp); + return; + } + + visit_type_str(v, name, &str, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + s = qemu_find_tpm_be(str); + if (s == NULL) { + error_setg(errp, "Property '%s.%s' can't find value '%s'", + object_get_typename(obj), prop->name, str); + } else if (tpm_backend_init(s, TPM_IF(obj), errp) == 0) { + *be = s; /* weak reference, avoid cyclic ref */ + } + g_free(str); +} + +static void release_tpm(Object *obj, const char *name, void *opaque) +{ + DeviceState *dev = DEVICE(obj); + Property *prop = opaque; + TPMBackend **be = qdev_get_prop_ptr(dev, prop); + + if (*be) { + tpm_backend_reset(*be); + } +} + +const PropertyInfo qdev_prop_tpm = { + .name = "str", + .description = "ID of a tpm to use as a backend", + .get = get_tpm, + .set = set_tpm, + .release = release_tpm, +}; + /* * Write an error message in the given output buffer. */ diff --git a/hw/tpm/tpm_util.h b/hw/tpm/tpm_util.h index 1c17e3913b..2393b6bc0e 100644 --- a/hw/tpm/tpm_util.h +++ b/hw/tpm/tpm_util.h @@ -39,4 +39,7 @@ static inline uint32_t tpm_cmd_get_size(const void *b) int tpm_util_get_buffer_size(int tpm_fd, TPMVersion tpm_version, size_t *buffersize); +#define DEFINE_PROP_TPMBE(_n, _s, _f) \ + DEFINE_PROP(_n, _s, _f, qdev_prop_tpm, TPMBackend *) + #endif /* TPM_TPM_UTIL_H */ diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 4d24cdf8d6..60b42ac561 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -187,8 +187,6 @@ extern const PropertyInfo qdev_prop_link; #define DEFINE_PROP_CHR(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_chr, CharBackend) -#define DEFINE_PROP_TPMBE(_n, _s, _f) \ - DEFINE_PROP(_n, _s, _f, qdev_prop_tpm, TPMBackend *) #define DEFINE_PROP_STRING(_n, _s, _f) \ DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*) #define DEFINE_PROP_NETDEV(_n, _s, _f) \ -- cgit v1.2.3-55-g7522 From 1b23190aba72a974c9a08496bf6d45e14b60087a Mon Sep 17 00:00:00 2001 From: Peter Xu Date: Sun, 10 Dec 2017 14:38:17 +0800 Subject: i8259: generalize statistics into common code It was only for userspace i8259. Move it to general code so that kvm-i8259 can also use it in the future. Signed-off-by: Peter Xu Message-Id: <20171210063819.14892-4-peterx@redhat.com> Signed-off-by: Paolo Bonzini --- hw/intc/i8259.c | 37 +------------------------------------ hw/intc/i8259_common.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/hw/isa/i8259_internal.h | 7 +++++-- 3 files changed, 47 insertions(+), 38 deletions(-) (limited to 'include/hw') diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 20c9d0a58b..d9b9666aff 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -25,11 +25,9 @@ #include "hw/hw.h" #include "hw/i386/pc.h" #include "hw/isa/isa.h" -#include "monitor/monitor.h" #include "qemu/timer.h" #include "qemu/log.h" #include "hw/isa/i8259_internal.h" -#include "hw/intc/intc.h" #include "trace.h" /* debug PIC */ @@ -51,8 +49,6 @@ typedef struct PICClass { DeviceRealize parent_realize; } PICClass; -static int irq_level[16]; -static uint64_t irq_count[16]; #ifdef DEBUG_IRQ_LATENCY static int64_t irq_time[16]; #endif @@ -126,13 +122,7 @@ static void pic_set_irq(void *opaque, int irq, int level) int irq_index = s->master ? irq : irq + 8; trace_pic_set_irq(s->master, irq, level); - - if (level != irq_level[irq_index]) { - irq_level[irq_index] = level; - if (level == 1) { - irq_count[irq_index]++; - } - } + pic_stat_update_irq(irq_index, level); #ifdef DEBUG_IRQ_LATENCY if (level) { @@ -235,31 +225,6 @@ static void pic_reset(DeviceState *dev) pic_init_reset(s); } -static bool pic_get_statistics(InterruptStatsProvider *obj, - uint64_t **irq_counts, unsigned int *nb_irqs) -{ - PICCommonState *s = PIC_COMMON(obj); - - if (s->master) { - *irq_counts = irq_count; - *nb_irqs = ARRAY_SIZE(irq_count); - } else { - *irq_counts = NULL; - *nb_irqs = 0; - } - return true; -} - -static void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) -{ - PICCommonState *s = PIC_COMMON(obj); - monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " - "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", - s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, - s->irq_base, s->read_reg_select, s->elcr, - s->special_fully_nested_mode); -} - static void pic_ioport_write(void *opaque, hwaddr addr64, uint64_t val64, unsigned size) { diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index 18427b459a..a3caddeefb 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -25,6 +25,10 @@ #include "qemu/osdep.h" #include "hw/i386/pc.h" #include "hw/isa/i8259_internal.h" +#include "monitor/monitor.h" + +static int irq_level[16]; +static uint64_t irq_count[16]; void pic_reset_common(PICCommonState *s) { @@ -98,6 +102,43 @@ ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) return isadev; } +void pic_stat_update_irq(int irq, int level) +{ + if (level != irq_level[irq]) { + irq_level[irq] = level; + if (level == 1) { + irq_count[irq]++; + } + } +} + +bool pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, unsigned int *nb_irqs) +{ + PICCommonState *s = PIC_COMMON(obj); + + if (s->master) { + *irq_counts = irq_count; + *nb_irqs = ARRAY_SIZE(irq_count); + } else { + *irq_counts = NULL; + *nb_irqs = 0; + } + + return true; +} + +void pic_print_info(InterruptStatsProvider *obj, Monitor *mon) +{ + PICCommonState *s = PIC_COMMON(obj); + + monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d " + "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n", + s->master ? 0 : 1, s->irr, s->imr, s->isr, s->priority_add, + s->irq_base, s->read_reg_select, s->elcr, + s->special_fully_nested_mode); +} + static const VMStateDescription vmstate_pic_common = { .name = "i8259", .version_id = 1, diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_internal.h index 6954b6ec5f..f742c2a726 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -28,6 +28,7 @@ #include "hw/hw.h" #include "hw/i386/pc.h" #include "hw/isa/isa.h" +#include "hw/intc/intc.h" typedef struct PICCommonState PICCommonState; @@ -76,8 +77,10 @@ struct PICCommonState { }; void pic_reset_common(PICCommonState *s); - ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master); - +void pic_stat_update_irq(int irq, int level); +bool pic_get_statistics(InterruptStatsProvider *obj, + uint64_t **irq_counts, unsigned int *nb_irqs); +void pic_print_info(InterruptStatsProvider *obj, Monitor *mon); #endif /* QEMU_I8259_INTERNAL_H */ -- cgit v1.2.3-55-g7522 From 2cb9f06e3d2c8649166a95e01b05433fa9d14384 Mon Sep 17 00:00:00 2001 From: Sergio Andres Gomez Del Real Date: Wed, 13 Sep 2017 04:05:15 -0500 Subject: apic: add function to apic that will be used by hvf This patch adds the function apic_get_highest_priority_irr to apic.c and exports it through the interface in apic.h for use by hvf. Signed-off-by: Sergio Andres Gomez Del Real Message-Id: <20170913090522.4022-8-Sergio.G.DelReal@gmail.com> Signed-off-by: Paolo Bonzini --- hw/intc/apic.c | 12 ++++++++++++ include/hw/i386/apic.h | 1 + 2 files changed, 13 insertions(+) (limited to 'include/hw') diff --git a/hw/intc/apic.c b/hw/intc/apic.c index fe15fb6024..6fda52b86c 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -305,6 +305,18 @@ static void apic_set_tpr(APICCommonState *s, uint8_t val) } } +int apic_get_highest_priority_irr(DeviceState *dev) +{ + APICCommonState *s; + + if (!dev) { + /* no interrupts */ + return -1; + } + s = APIC_COMMON(dev); + return get_highest_priority_int(s->irr); +} + static uint8_t apic_get_tpr(APICCommonState *s) { apic_sync_vapic(s, SYNC_FROM_VAPIC); diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index ea48ea9389..a9f6c0aa33 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -20,6 +20,7 @@ void apic_init_reset(DeviceState *s); void apic_sipi(DeviceState *s); void apic_poll_irq(DeviceState *d); void apic_designate_bsp(DeviceState *d, bool bsp); +int apic_get_highest_priority_irr(DeviceState *dev); /* pc.c */ DeviceState *cpu_get_current_apic(void); -- cgit v1.2.3-55-g7522 From 4a42fa0ee20b51b326f6494cb50218b52471a261 Mon Sep 17 00:00:00 2001 From: Stefan Berger Date: Tue, 14 Nov 2017 13:42:42 -0500 Subject: acpi: Update TPM2 ACPI table to more recent specs More recent specs of the TPM2 ACPI table add fields for the log area start address and the log area minimum size, which we already use for the TCPA table. Signed-off-by: Stefan Berger Reviewed-by: Marc-André Lureau --- hw/i386/acpi-build.c | 19 ++++++++++++++----- include/hw/acpi/acpi-defs.h | 7 +++++-- 2 files changed, 19 insertions(+), 7 deletions(-) (limited to 'include/hw') diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 5a6dee081c..18b939e469 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2274,16 +2274,25 @@ build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) } static void -build_tpm2(GArray *table_data, BIOSLinker *linker) +build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog) { - Acpi20TPM2 *tpm2_ptr; - - tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); + Acpi20TPM2 *tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr); + unsigned log_addr_size = sizeof(tpm2_ptr->log_area_start_address); + unsigned log_addr_offset = + (char *)&tpm2_ptr->log_area_start_address - table_data->data; tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT); if (TPM_IS_TIS(tpm_find())) { tpm2_ptr->control_area_address = cpu_to_le64(0); tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO); + + tpm2_ptr->log_area_minimum_length = + cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE); + + /* log area start address to be filled by Guest linker */ + bios_linker_loader_add_pointer(linker, + ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size, + ACPI_BUILD_TPMLOG_FILE, 0); } else { g_warn_if_reached(); } @@ -2695,7 +2704,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) if (misc.tpm_version == TPM_VERSION_2_0) { acpi_add_table(table_offsets, tables_blob); - build_tpm2(tables_blob, tables->linker); + build_tpm2(tables_blob, tables->linker, tables->tcpalog); } } if (pcms->numa_nodes) { diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 72be675dd6..80c8099a23 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -558,8 +558,8 @@ typedef struct Acpi20Tcpa Acpi20Tcpa; /* * TPM2 * - * Following Level 00, Rev 00.37 of specs: - * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification + * Following Version 1.2, Revision 8 of specs: + * https://trustedcomputinggroup.org/tcg-acpi-specification/ */ struct Acpi20TPM2 { ACPI_TABLE_HEADER_DEF @@ -567,6 +567,9 @@ struct Acpi20TPM2 { uint16_t reserved; uint64_t control_area_address; uint32_t start_method; + uint8_t start_method_params[12]; + uint32_t log_area_minimum_length; + uint64_t log_area_start_address; } QEMU_PACKED; typedef struct Acpi20TPM2 Acpi20TPM2; -- cgit v1.2.3-55-g7522 From 28edc7c92a7491a9c077fd5b5686e5a226b8138b Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: move QOM macros and typedefs from apb.c to apb.h This also includes the related IOMMUState typedef and defines. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 85 ---------------------------------------------- include/hw/pci-host/apb.h | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 85 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 64025cd8cc..f743a4e312 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -82,91 +82,6 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) #define MAX_IVEC 0x40 #define NO_IRQ_REQUEST (MAX_IVEC + 1) -#define IOMMU_PAGE_SIZE_8K (1ULL << 13) -#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) -#define IOMMU_PAGE_SIZE_64K (1ULL << 16) -#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) - -#define IOMMU_NREGS 3 - -#define IOMMU_CTRL 0x0 -#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) -#define IOMMU_CTRL_MMU_EN (1ULL) - -#define IOMMU_CTRL_TSB_SHIFT 16 - -#define IOMMU_BASE 0x8 -#define IOMMU_FLUSH 0x10 - -#define IOMMU_TTE_DATA_V (1ULL << 63) -#define IOMMU_TTE_DATA_SIZE (1ULL << 61) -#define IOMMU_TTE_DATA_W (1ULL << 1) - -#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL -#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL - -#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL - -#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL - -typedef struct IOMMUState { - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - uint64_t regs[IOMMU_NREGS]; -} IOMMUState; - -#define TYPE_APB "pbm" - -#define APB_DEVICE(obj) \ - OBJECT_CHECK(APBState, (obj), TYPE_APB) - -#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" - -typedef struct APBState { - PCIHostState parent_obj; - - MemoryRegion apb_config; - MemoryRegion pci_config; - MemoryRegion pci_mmio; - MemoryRegion pci_ioport; - uint64_t pci_irq_in; - IOMMUState iommu; - uint32_t pci_control[16]; - uint32_t pci_irq_map[8]; - uint32_t pci_err_irq_map[4]; - uint32_t obio_irq_map[32]; - qemu_irq *pbm_irqs; - qemu_irq *ivec_irqs; - unsigned int irq_request; - uint32_t reset_control; - unsigned int nr_resets; -} APBState; - -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -#define PBM_PCI_BRIDGE(obj) \ - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) - -typedef struct PBMPCIBridge { - /*< private >*/ - PCIBridge parent_obj; - - /* Is this busA with in-built devices (ebus)? */ - bool busA; -} PBMPCIBridge; - static inline void pbm_set_request(APBState *s, unsigned int irq_num) { APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index b19bd55c40..5d39c03bc4 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -2,6 +2,92 @@ #define PCI_HOST_APB_H #include "qemu-common.h" +#include "hw/pci/pci_host.h" + +#define IOMMU_NREGS 3 + +#define IOMMU_PAGE_SIZE_8K (1ULL << 13) +#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) +#define IOMMU_PAGE_SIZE_64K (1ULL << 16) +#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) + +#define IOMMU_CTRL 0x0 +#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) +#define IOMMU_CTRL_MMU_EN (1ULL) + +#define IOMMU_CTRL_TSB_SHIFT 16 + +#define IOMMU_BASE 0x8 +#define IOMMU_FLUSH 0x10 + +#define IOMMU_TTE_DATA_V (1ULL << 63) +#define IOMMU_TTE_DATA_SIZE (1ULL << 61) +#define IOMMU_TTE_DATA_W (1ULL << 1) + +#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL +#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL + +#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL + +#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL + +typedef struct IOMMUState { + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + uint64_t regs[IOMMU_NREGS]; +} IOMMUState; + +#define TYPE_APB "pbm" + +#define APB_DEVICE(obj) \ + OBJECT_CHECK(APBState, (obj), TYPE_APB) + +#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" + +typedef struct APBState { + PCIHostState parent_obj; + + MemoryRegion apb_config; + MemoryRegion pci_config; + MemoryRegion pci_mmio; + MemoryRegion pci_ioport; + uint64_t pci_irq_in; + IOMMUState iommu; + uint32_t pci_control[16]; + uint32_t pci_irq_map[8]; + uint32_t pci_err_irq_map[4]; + uint32_t obio_irq_map[32]; + qemu_irq *pbm_irqs; + qemu_irq *ivec_irqs; + unsigned int irq_request; + uint32_t reset_control; + unsigned int nr_resets; +} APBState; + +typedef struct PBMPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + /* Is this busA with in-built devices (ebus)? */ + bool busA; +} PBMPCIBridge; + +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" +#define PBM_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) PCIBus *pci_apb_init(hwaddr special_base, hwaddr mem_base, -- cgit v1.2.3-55-g7522 From c796eddaad58301611315ae3c16f3ef26ccf207a Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: sun4u: remove pci_ebus_init() function This is initialisation that should really take place in the ebus realize function. As part of this we also rework the ebus IRQ mapping so that instead of having to pass in the array of pbm_irqs, we obtain a reference to them by looking up the APB device during ebus realize. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 4 +--- hw/sparc64/sun4u.c | 29 ++++++++++++++--------------- include/hw/pci-host/apb.h | 3 +-- 3 files changed, 16 insertions(+), 20 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index f743a4e312..b0f80f63eb 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -614,8 +614,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) PCIBus *pci_apb_init(hwaddr special_base, hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB, - qemu_irq **pbm_irqs) + qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB) { DeviceState *dev; SysBusDevice *s; @@ -646,7 +645,6 @@ PCIBus *pci_apb_init(hwaddr special_base, memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio); - *pbm_irqs = d->pbm_irqs; d->ivec_irqs = ivec_irqs; pci_create_simple(phb->bus, 0, "pbm-pci"); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 63b4aaa6eb..f3203ea887 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -230,21 +230,11 @@ static void isa_irq_handler(void *opaque, int n, int level) } /* EBUS (Eight bit bus) bridge */ -static ISABus * -pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) -{ - qemu_irq *isa_irq; - ISABus *isa_bus; - - isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); - isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); - isa_bus_irqs(isa_bus, isa_irq); - return isa_bus; -} - static void ebus_realize(PCIDevice *pci_dev, Error **errp) { EbusState *s = EBUS(pci_dev); + APBState *apb; + qemu_irq *isa_irq; s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), pci_address_space_io(pci_dev), errp); @@ -253,6 +243,15 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) return; } + apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL)); + if (!apb) { + error_setg(errp, "unable to locate APB PCI host bridge"); + return; + } + + isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16); + isa_bus_irqs(s->isa_bus, isa_irq); + pci_dev->config[0x04] = 0x06; // command = bus master, pci mem pci_dev->config[0x05] = 0x00; pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error @@ -443,7 +442,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, PCIDevice *ebus, *pci_dev; ISABus *isa_bus; SysBusDevice *s; - qemu_irq *ivec_irqs, *pbm_irqs; + qemu_irq *ivec_irqs; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *fd[MAX_FD]; DeviceState *dev; @@ -462,7 +461,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, - &pci_busB, &pbm_irqs); + &pci_busB); /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is reserved (leaving no slots free after on-board devices) however slots @@ -474,7 +473,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); qdev_init_nofail(DEVICE(ebus)); - isa_bus = pci_ebus_init(ebus, pbm_irqs); + isa_bus = EBUS(ebus)->isa_bus; i = 0; if (hwdef->console_serial_base) { diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 5d39c03bc4..35d7d5ad7b 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -91,6 +91,5 @@ typedef struct PBMPCIBridge { PCIBus *pci_apb_init(hwaddr special_base, hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3, - qemu_irq **pbm_irqs); + qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3); #endif -- cgit v1.2.3-55-g7522 From 588978c0a1e9f5596a12d124b530bdf698ed9104 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: return APBState from pci_apb_init() rather than PCIBus This is a first step towards removing pci_apb_init() completely. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Artyom Tarasenko --- hw/pci-host/apb.c | 8 ++++---- hw/sparc64/sun4u.c | 6 ++++-- include/hw/pci-host/apb.h | 6 +++--- 3 files changed, 11 insertions(+), 9 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index c7837efb7a..0c709992ec 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -612,9 +612,9 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) pci_bridge_update_mappings(PCI_BRIDGE(br)); } -PCIBus *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB) +APBState *pci_apb_init(hwaddr special_base, + hwaddr mem_base, + qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB) { DeviceState *dev; SysBusDevice *s; @@ -675,7 +675,7 @@ PCIBus *pci_apb_init(hwaddr special_base, qdev_init_nofail(&pci_dev->qdev); *busA = pci_bridge_get_sec_bus(br); - return phb->bus; + return d; } static void pci_pbm_reset(DeviceState *d) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index b441f1ecdb..a64ddc569d 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -482,6 +482,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, Nvram *nvram; unsigned int i; uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; + APBState *apb; PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; @@ -502,8 +503,9 @@ static void sun4uv_init(MemoryRegion *address_space_mem, prom_init(hwdef->prom_addr, bios_name); ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); - pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, - &pci_busB); + apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, + &pci_busB); + pci_bus = PCI_HOST_BRIDGE(apb)->bus; /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is reserved (leaving no slots free after on-board devices) however slots diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 35d7d5ad7b..a4ef51adc8 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -89,7 +89,7 @@ typedef struct PBMPCIBridge { #define PBM_PCI_BRIDGE(obj) \ OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) -PCIBus *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3); +APBState *pci_apb_init(hwaddr special_base, + hwaddr mem_base, + qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3); #endif -- cgit v1.2.3-55-g7522 From 2a4d6af51b8330bfd7a7dd677927b8dd2f5f5f08 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: use gpios to wire up the apb device to the SPARC CPU IRQs Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Artyom Tarasenko --- hw/pci-host/apb.c | 6 ++---- hw/sparc64/sparc64.c | 2 ++ hw/sparc64/sun4u.c | 12 ++++++++---- include/hw/pci-host/apb.h | 6 ++++-- include/hw/sparc/sparc64.h | 2 ++ 5 files changed, 18 insertions(+), 10 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 0c709992ec..c0b97e41bf 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -79,7 +79,6 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) #define RESET_WCMASK 0x98000000 #define RESET_WMASK 0x60000000 -#define MAX_IVEC 0x40 #define NO_IRQ_REQUEST (MAX_IVEC + 1) static inline void pbm_set_request(APBState *s, unsigned int irq_num) @@ -614,7 +613,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) APBState *pci_apb_init(hwaddr special_base, hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **busA, PCIBus **busB) + PCIBus **busA, PCIBus **busB) { DeviceState *dev; SysBusDevice *s; @@ -645,8 +644,6 @@ APBState *pci_apb_init(hwaddr special_base, memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio); - d->ivec_irqs = ivec_irqs; - pci_create_simple(phb->bus, 0, "pbm-pci"); /* APB IOMMU */ @@ -721,6 +718,7 @@ static int pci_pbm_init_device(DeviceState *dev) s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; } s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC); + qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); s->irq_request = NO_IRQ_REQUEST; s->pci_irq_in = 0ULL; diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 9453e2c390..95a06f00b2 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -350,6 +350,8 @@ SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr) uint32_t hstick_frequency = 100 * 1000000; cpu = SPARC_CPU(cpu_create(cpu_type)); + qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq, + "ivec-irq", IVEC_MAX); env = &cpu->env; env->tick = cpu_timer_create("tick", cpu, tick_irq, diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index a64ddc569d..2afd3f28dd 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -486,7 +486,6 @@ static void sun4uv_init(MemoryRegion *address_space_mem, PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; - qemu_irq *ivec_irqs; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DeviceState *dev; FWCfgState *fw_cfg; @@ -502,9 +501,14 @@ static void sun4uv_init(MemoryRegion *address_space_mem, prom_init(hwdef->prom_addr, bios_name); - ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); - apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, - &pci_busB); + apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_busB); + + /* Wire up PCI interrupts to CPU */ + for (i = 0; i < IVEC_MAX; i++) { + qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, + qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); + } + pci_bus = PCI_HOST_BRIDGE(apb)->bus; /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index a4ef51adc8..f7ead680f3 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -50,6 +50,8 @@ typedef struct IOMMUState { uint64_t regs[IOMMU_NREGS]; } IOMMUState; +#define MAX_IVEC 0x40 + #define TYPE_APB "pbm" #define APB_DEVICE(obj) \ @@ -71,7 +73,7 @@ typedef struct APBState { uint32_t pci_err_irq_map[4]; uint32_t obio_irq_map[32]; qemu_irq *pbm_irqs; - qemu_irq *ivec_irqs; + qemu_irq ivec_irqs[MAX_IVEC]; unsigned int irq_request; uint32_t reset_control; unsigned int nr_resets; @@ -91,5 +93,5 @@ typedef struct PBMPCIBridge { APBState *pci_apb_init(hwaddr special_base, hwaddr mem_base, - qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3); + PCIBus **bus2, PCIBus **bus3); #endif diff --git a/include/hw/sparc/sparc64.h b/include/hw/sparc/sparc64.h index ca3bb4be71..5af4344459 100644 --- a/include/hw/sparc/sparc64.h +++ b/include/hw/sparc/sparc64.h @@ -1,4 +1,6 @@ +#define IVEC_MAX 0x40 + SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr); void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level); -- cgit v1.2.3-55-g7522 From 4272ad40189c73324da59047f5232ec795111c4b Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: move the two secondary PCI bridges objects into APBState This enables us to remove these parameters from pci_apb_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 14 +++++--------- hw/sparc64/sun4u.c | 5 ++++- include/hw/pci-host/apb.h | 5 +++-- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index c0b97e41bf..823661a8a6 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -612,8 +612,7 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) } APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - PCIBus **busA, PCIBus **busB) + hwaddr mem_base) { DeviceState *dev; SysBusDevice *s; @@ -621,7 +620,6 @@ APBState *pci_apb_init(hwaddr special_base, APBState *d; IOMMUState *is; PCIDevice *pci_dev; - PCIBridge *br; /* Ultrasparc PBM main bus */ dev = qdev_create(NULL, TYPE_APB); @@ -659,18 +657,16 @@ APBState *pci_apb_init(hwaddr special_base, /* APB secondary busses */ pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, TYPE_PBM_PCI_BRIDGE); - br = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq); + d->bridgeB = PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq); qdev_init_nofail(&pci_dev->qdev); - *busB = pci_bridge_get_sec_bus(br); pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, TYPE_PBM_PCI_BRIDGE); - br = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq); + d->bridgeA = PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq); qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); - *busA = pci_bridge_get_sec_bus(br); return d; } diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 2afd3f28dd..47952befcb 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -27,6 +27,7 @@ #include "cpu.h" #include "hw/hw.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/apb.h" #include "hw/i386/pc.h" @@ -501,7 +502,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, prom_init(hwdef->prom_addr, bios_name); - apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, &pci_busA, &pci_busB); + apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE); /* Wire up PCI interrupts to CPU */ for (i = 0; i < IVEC_MAX; i++) { @@ -510,6 +511,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem, } pci_bus = PCI_HOST_BRIDGE(apb)->bus; + pci_busA = pci_bridge_get_sec_bus(apb->bridgeA); + pci_busB = pci_bridge_get_sec_bus(apb->bridgeB); /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is reserved (leaving no slots free after on-board devices) however slots diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index f7ead680f3..ae15d8ce59 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -68,6 +68,8 @@ typedef struct APBState { MemoryRegion pci_ioport; uint64_t pci_irq_in; IOMMUState iommu; + PCIBridge *bridgeA; + PCIBridge *bridgeB; uint32_t pci_control[16]; uint32_t pci_irq_map[8]; uint32_t pci_err_irq_map[4]; @@ -92,6 +94,5 @@ typedef struct PBMPCIBridge { OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base, - PCIBus **bus2, PCIBus **bus3); + hwaddr mem_base); #endif -- cgit v1.2.3-55-g7522 From cacd05805eeea393ec929fe841f9a68aa2140d92 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: remove pci_apb_init() and instantiate APB device using qdev By making the special_base and mem_base values qdev properties, we can move the remaining parts of pci_apb_init() into the pbm init() and realize() functions. This finally allows us to instantiate the APB directly using standard qdev create/init functions in sun4u.c. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 124 +++++++++++++++++++++++----------------------- hw/sparc64/sun4u.c | 6 ++- include/hw/pci-host/apb.h | 4 +- 3 files changed, 68 insertions(+), 66 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 823661a8a6..787be744a2 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -611,41 +611,62 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) pci_bridge_update_mappings(PCI_BRIDGE(br)); } -APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base) +static void pci_pbm_reset(DeviceState *d) { - DeviceState *dev; - SysBusDevice *s; - PCIHostState *phb; - APBState *d; - IOMMUState *is; + unsigned int i; + APBState *s = APB_DEVICE(d); + + for (i = 0; i < 8; i++) { + s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; + } + for (i = 0; i < 32; i++) { + s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; + } + + s->irq_request = NO_IRQ_REQUEST; + s->pci_irq_in = 0ULL; + + if (s->nr_resets++ == 0) { + /* Power on reset */ + s->reset_control = POR; + } +} + +static const MemoryRegionOps pci_config_ops = { + .read = apb_pci_config_read, + .write = apb_pci_config_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void pci_pbm_realize(DeviceState *dev, Error **errp) +{ + APBState *s = APB_DEVICE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(s); PCIDevice *pci_dev; + IOMMUState *is; - /* Ultrasparc PBM main bus */ - dev = qdev_create(NULL, TYPE_APB); - d = APB_DEVICE(dev); - phb = PCI_HOST_BRIDGE(dev); - phb->bus = pci_register_bus(DEVICE(phb), "pci", - pci_apb_set_irq, pci_apb_map_irq, d, - &d->pci_mmio, - &d->pci_ioport, - 0, 32, TYPE_PCI_BUS); - qdev_init_nofail(dev); - s = SYS_BUS_DEVICE(dev); /* apb_config */ - sysbus_mmio_map(s, 0, special_base); + sysbus_mmio_map(sbd, 0, s->special_base); /* PCI configuration space */ - sysbus_mmio_map(s, 1, special_base + 0x1000000ULL); + sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); /* pci_ioport */ - sysbus_mmio_map(s, 2, special_base + 0x2000000ULL); + sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); - memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); - memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio); + memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); + memory_region_add_subregion(get_system_memory(), s->mem_base, + &s->pci_mmio); + + phb->bus = pci_register_bus(dev, "pci", + pci_apb_set_irq, pci_apb_map_irq, s, + &s->pci_mmio, + &s->pci_ioport, + 0, 32, TYPE_PCI_BUS); pci_create_simple(phb->bus, 0, "pbm-pci"); /* APB IOMMU */ - is = &d->iommu; + is = &s->iommu; memset(is, 0, sizeof(IOMMUState)); memory_region_init_iommu(&is->iommu, sizeof(is->iommu), @@ -657,51 +678,22 @@ APBState *pci_apb_init(hwaddr special_base, /* APB secondary busses */ pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, TYPE_PBM_PCI_BRIDGE); - d->bridgeB = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(d->bridgeB, "pciB", pci_pbm_map_irq); + s->bridgeB = PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbm_map_irq); qdev_init_nofail(&pci_dev->qdev); pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, TYPE_PBM_PCI_BRIDGE); - d->bridgeA = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(d->bridgeA, "pciA", pci_pbm_map_irq); + s->bridgeA = PCI_BRIDGE(pci_dev); + pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbm_map_irq); qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); - - return d; -} - -static void pci_pbm_reset(DeviceState *d) -{ - unsigned int i; - APBState *s = APB_DEVICE(d); - - for (i = 0; i < 8; i++) { - s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; - } - for (i = 0; i < 32; i++) { - s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; - } - - s->irq_request = NO_IRQ_REQUEST; - s->pci_irq_in = 0ULL; - - if (s->nr_resets++ == 0) { - /* Power on reset */ - s->reset_control = POR; - } } -static const MemoryRegionOps pci_config_ops = { - .read = apb_pci_config_read, - .write = apb_pci_config_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static int pci_pbm_init_device(DeviceState *dev) +static void pci_pbm_init(Object *obj) { - APBState *s = APB_DEVICE(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(s); + APBState *s = APB_DEVICE(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); unsigned int i; for (i = 0; i < 8; i++) { @@ -734,8 +726,6 @@ static int pci_pbm_init_device(DeviceState *dev) /* at region 2 */ sysbus_init_mmio(sbd, &s->pci_ioport); - - return 0; } static void pbm_pci_host_realize(PCIDevice *d, Error **errp) @@ -774,12 +764,19 @@ static const TypeInfo pbm_pci_host_info = { }, }; +static Property pbm_pci_host_properties[] = { + DEFINE_PROP_UINT64("special-base", APBState, special_base, 0), + DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void pbm_host_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->init = pci_pbm_init_device; + dc->realize = pci_pbm_realize; dc->reset = pci_pbm_reset; + dc->props = pbm_pci_host_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -787,6 +784,7 @@ static const TypeInfo pbm_host_info = { .name = TYPE_APB, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(APBState), + .instance_init = pci_pbm_init, .class_init = pbm_host_class_init, }; diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 47952befcb..0a30fb8d08 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -502,7 +502,11 @@ static void sun4uv_init(MemoryRegion *address_space_mem, prom_init(hwdef->prom_addr, bios_name); - apb = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE); + /* Init APB (PCI host bridge) */ + apb = APB_DEVICE(qdev_create(NULL, TYPE_APB)); + qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); + qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); + qdev_init_nofail(DEVICE(apb)); /* Wire up PCI interrupts to CPU */ for (i = 0; i < IVEC_MAX; i++) { diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index ae15d8ce59..f0074f7a51 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -62,6 +62,8 @@ typedef struct IOMMUState { typedef struct APBState { PCIHostState parent_obj; + hwaddr special_base; + hwaddr mem_base; MemoryRegion apb_config; MemoryRegion pci_config; MemoryRegion pci_mmio; @@ -93,6 +95,4 @@ typedef struct PBMPCIBridge { #define PBM_PCI_BRIDGE(obj) \ OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) -APBState *pci_apb_init(hwaddr special_base, - hwaddr mem_base); #endif -- cgit v1.2.3-55-g7522 From 33c5eb02c4f51515896a5a13cb68f6f01ce8d0af Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: remove busA property from PBMPCIBridge state Since the previous commit the only remaining use of the qdev busA property is to configure the PCI bridge in front of the onboard ebus devices differently to allow early OpenBIOS serial console access. Instead we can now manually update the PCI configuration for bridge A in pci_pbm_reset() and thus completely remove the busA property from the PBMPCIBridge state. Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko --- hw/pci-host/apb.c | 29 +++++++++++++---------------- include/hw/pci-host/apb.h | 3 --- 2 files changed, 13 insertions(+), 19 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 8bdbbfd214..5562f1adfd 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -581,18 +581,11 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) * the reset value should be zero unless the boot pin is tied high * (which is true) and thus it should be PCI_COMMAND_MEMORY. */ - uint16_t cmd = PCI_COMMAND_MEMORY; PBMPCIBridge *br = PBM_PCI_BRIDGE(dev); pci_bridge_initfn(dev, TYPE_PCI_BUS); - /* If initialising busA, ensure that we allow IO transactions so that - we get the early serial console until OpenBIOS configures the bridge */ - if (br->busA) { - cmd |= PCI_COMMAND_IO; - } - - pci_set_word(dev->config + PCI_COMMAND, cmd); + pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); @@ -608,8 +601,10 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) static void pci_pbm_reset(DeviceState *d) { - unsigned int i; APBState *s = APB_DEVICE(d); + PCIDevice *pci_dev; + unsigned int i; + uint16_t cmd; for (i = 0; i < 8; i++) { s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; @@ -625,6 +620,15 @@ static void pci_pbm_reset(DeviceState *d) /* Power on reset */ s->reset_control = POR; } + + /* As this is the busA PCI bridge which contains the on-board devices + * attached to the ebus, ensure that we initially allow IO transactions + * so that we get the early serial console until OpenBIOS can properly + * configure the PCI bridge itself */ + pci_dev = PCI_DEVICE(s->bridgeA); + cmd = pci_get_word(pci_dev->config + PCI_COMMAND); + pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); + pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); } static const MemoryRegionOps pci_config_ops = { @@ -681,7 +685,6 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp) TYPE_PBM_PCI_BRIDGE); s->bridgeA = PCI_BRIDGE(pci_dev); pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq); - qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); } @@ -783,11 +786,6 @@ static const TypeInfo pbm_host_info = { .class_init = pbm_host_class_init, }; -static Property pbm_pci_properties[] = { - DEFINE_PROP_BOOL("busA", PBMPCIBridge, busA, false), - DEFINE_PROP_END_OF_LIST(), -}; - static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -803,7 +801,6 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset = pci_bridge_reset; dc->vmsd = &vmstate_pci_device; - dc->props = pbm_pci_properties; } static const TypeInfo pbm_pci_bridge_info = { diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index f0074f7a51..dd49437ff1 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -86,9 +86,6 @@ typedef struct APBState { typedef struct PBMPCIBridge { /*< private >*/ PCIBridge parent_obj; - - /* Is this busA with in-built devices (ebus)? */ - bool busA; } PBMPCIBridge; #define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -- cgit v1.2.3-55-g7522 From 4b10c8d7012eea39e96819545eb21d28228831c6 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: ebus: wire up OBIO interrupts to APB pbm via qdev GPIOs This enables us to remove the static array mapping in the ISA IRQ handler (and the embedded reference to the APB device) by formalising the interrupt wiring via the qdev GPIO API. For more clarity we replace the APB OBIO interrupt numbers with constants designating the interrupt source, and rename isa_irq_handler() to ebus_isa_irq_handler(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 2 +- hw/sparc64/sun4u.c | 49 ++++++++++++++++++++++++----------------------- include/hw/pci-host/apb.h | 8 +++++++- 3 files changed, 33 insertions(+), 26 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 5562f1adfd..54edbddb03 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -703,7 +703,7 @@ static void pci_pbm_init(Object *obj) for (i = 0; i < 32; i++) { s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; } - s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC); + qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC); qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); s->irq_request = NO_IRQ_REQUEST; s->pci_irq_in = 0ULL; diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 0a30fb8d08..1456c3370d 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -86,6 +86,7 @@ typedef struct EbusState { PCIDevice parent_obj; ISABus *isa_bus; + qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; uint64_t console_serial_base; MemoryRegion bar0; MemoryRegion bar1; @@ -211,23 +212,15 @@ typedef struct ResetData { uint64_t prom_addr; } ResetData; -static void isa_irq_handler(void *opaque, int n, int level) +static void ebus_isa_irq_handler(void *opaque, int n, int level) { - static const int isa_irq_to_ivec[16] = { - [1] = 0x29, /* keyboard */ - [4] = 0x2b, /* serial */ - [6] = 0x27, /* floppy */ - [7] = 0x22, /* parallel */ - [12] = 0x2a, /* mouse */ - }; - qemu_irq *irqs = opaque; - int ivec; - - assert(n < ARRAY_SIZE(isa_irq_to_ivec)); - ivec = isa_irq_to_ivec[n]; - EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); - if (ivec) { - qemu_set_irq(irqs[ivec], level); + EbusState *s = EBUS(opaque); + qemu_irq irq = s->isa_bus_irqs[n]; + + /* Pass ISA bus IRQs onto their gpio equivalent */ + EBUS_DPRINTF("Set ISA IRQ %d level %d\n", n, level); + if (irq) { + qemu_set_irq(irq, level); } } @@ -235,7 +228,6 @@ static void isa_irq_handler(void *opaque, int n, int level) static void ebus_realize(PCIDevice *pci_dev, Error **errp) { EbusState *s = EBUS(pci_dev); - APBState *apb; DeviceState *dev; qemu_irq *isa_irq; DriveInfo *fd[MAX_FD]; @@ -248,14 +240,11 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) return; } - apb = APB_DEVICE(object_resolve_path_type("", TYPE_APB, NULL)); - if (!apb) { - error_setg(errp, "unable to locate APB PCI host bridge"); - return; - } - - isa_irq = qemu_allocate_irqs(isa_irq_handler, apb->pbm_irqs, 16); + /* ISA bus */ + isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); isa_bus_irqs(s->isa_bus, isa_irq); + qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", + ISA_NUM_IRQS); /* Serial ports */ i = 0; @@ -530,6 +519,18 @@ static void sun4uv_init(MemoryRegion *address_space_mem, hwdef->console_serial_base); qdev_init_nofail(DEVICE(ebus)); + /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */ + qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, + qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ)); + qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, + qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ)); + qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, + qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ)); + qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, + qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ)); + qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, + qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ)); + pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); memset(&macaddr, 0, sizeof(MACAddr)); diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index dd49437ff1..09ebd53f60 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -52,6 +52,13 @@ typedef struct IOMMUState { #define MAX_IVEC 0x40 +/* OBIO IVEC IRQs */ +#define OBIO_LPT_IRQ 0x22 +#define OBIO_FDD_IRQ 0x27 +#define OBIO_KBD_IRQ 0x29 +#define OBIO_MSE_IRQ 0x2a +#define OBIO_SER_IRQ 0x2b + #define TYPE_APB "pbm" #define APB_DEVICE(obj) \ @@ -76,7 +83,6 @@ typedef struct APBState { uint32_t pci_irq_map[8]; uint32_t pci_err_irq_map[4]; uint32_t obio_irq_map[32]; - qemu_irq *pbm_irqs; qemu_irq ivec_irqs[MAX_IVEC]; unsigned int irq_request; uint32_t reset_control; -- cgit v1.2.3-55-g7522 From a5546222e3eafc9b6bc784c1bffbc8e1614d5e5b Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 21 Dec 2017 07:32:57 +0000 Subject: apb: replace OBIO interrupt numbers in pci_pbmA_map_irq() with constants Following on from the previous commit, we can also do the same with with legacy OBIO interrupts in pci_pbmA_map_irq(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Artyom Tarasenko Reviewed-by: Philippe Mathieu-Daudé --- hw/pci-host/apb.c | 4 ++-- include/hw/pci-host/apb.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 54edbddb03..44b08c090e 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -523,10 +523,10 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) switch (PCI_SLOT(pci_dev->devfn)) { case 1: /* Onboard NIC */ - return 0x21; + return OBIO_NIC_IRQ; case 3: /* Onboard IDE */ - return 0x20; + return OBIO_HDD_IRQ; default: /* Normal intno, fall through */ break; diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 09ebd53f60..6194c8cbad 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -53,6 +53,8 @@ typedef struct IOMMUState { #define MAX_IVEC 0x40 /* OBIO IVEC IRQs */ +#define OBIO_HDD_IRQ 0x20 +#define OBIO_NIC_IRQ 0x21 #define OBIO_LPT_IRQ 0x22 #define OBIO_FDD_IRQ 0x27 #define OBIO_KBD_IRQ 0x29 -- cgit v1.2.3-55-g7522 From 1527f4886c88c8ac7faf507122580e964c2259a7 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: sun4m: move IOMMU declarations from sun4m.h to sun4m_iommu.h Also updating the relevant .c files as required. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/dma/sparc32_dma.c | 1 + hw/sparc/sun4m.c | 1 + hw/sparc/sun4m_iommu.c | 1 + include/hw/sparc/sun4m.h | 21 ----------------- include/hw/sparc/sun4m_iommu.h | 51 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 21 deletions(-) create mode 100644 include/hw/sparc/sun4m_iommu.h (limited to 'include/hw') diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index 01afb758b6..c04ad79305 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -29,6 +29,7 @@ #include "hw/hw.h" #include "hw/sparc/sparc32_dma.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "sysemu/dma.h" #include "qapi/error.h" diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index e71648404c..efaff5849d 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -29,6 +29,7 @@ #include "qemu/error-report.h" #include "qemu/timer.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/timer/m48t59.h" #include "hw/sparc/sparc32_dma.h" #include "hw/block/fdc.h" diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 72a9af555f..311c82d2bb 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "hw/sparc/sun4m.h" +#include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" #include "trace.h" diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h index c557b0dd53..9e06467ac2 100644 --- a/include/hw/sparc/sun4m.h +++ b/include/hw/sparc/sun4m.h @@ -8,27 +8,6 @@ /* Devices used by sparc32 system. */ -/* iommu.c */ -#define TYPE_SUN4M_IOMMU "sun4m-iommu" -#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) - -#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" - -#define IOMMU_NREGS (4 * 4096 / 4) - -typedef struct IOMMUState { - SysBusDevice parent_obj; - - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - MemoryRegion iomem; - uint32_t regs[IOMMU_NREGS]; - hwaddr iostart; - qemu_irq irq; - uint32_t version; -} IOMMUState; - /* sparc32_dma.c */ #include "hw/sparc/sparc32_dma.h" diff --git a/include/hw/sparc/sun4m_iommu.h b/include/hw/sparc/sun4m_iommu.h new file mode 100644 index 0000000000..938937eb04 --- /dev/null +++ b/include/hw/sparc/sun4m_iommu.h @@ -0,0 +1,51 @@ +/* + * QEMU Sun4m iommu emulation + * + * Copyright (c) 2003-2005 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SUN4M_IOMMU_H +#define SUN4M_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS (4 * 4096 / 4) + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint32_t regs[IOMMU_NREGS]; + hwaddr iostart; + qemu_irq irq; + uint32_t version; +} IOMMUState; + +#define TYPE_SUN4M_IOMMU "sun4m-iommu" +#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU) + +#define TYPE_SUN4M_IOMMU_MEMORY_REGION "sun4m-iommu-memory-region" + +#endif -- cgit v1.2.3-55-g7522 From f5980f757c028ec68ff8442c418db8462415af2a Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: sun4m: remove include/hw/sparc/sun4m.h and all references to it With the previous commit there is now nothing left in sun4m.h so it can be removed, along with all remaining references to it. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/dma/sparc32_dma.c | 1 - hw/intc/slavio_intctl.c | 1 - hw/net/lance.c | 2 +- hw/sparc/sun4m.c | 1 - hw/sparc/sun4m_iommu.c | 1 - hw/timer/slavio_timer.c | 1 - include/hw/sparc/sun4m.h | 14 -------------- 7 files changed, 1 insertion(+), 20 deletions(-) delete mode 100644 include/hw/sparc/sun4m.h (limited to 'include/hw') diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index c04ad79305..7b00a27de6 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "hw/hw.h" #include "hw/sparc/sparc32_dma.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "sysemu/dma.h" diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index 84e0bee4a9..817e02617e 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "monitor/monitor.h" #include "hw/sysbus.h" #include "hw/intc/intc.h" diff --git a/hw/net/lance.c b/hw/net/lance.c index 23929fd1e6..0028bc525d 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -40,7 +40,7 @@ #include "net/net.h" #include "qemu/timer.h" #include "qemu/sockets.h" -#include "hw/sparc/sun4m.h" +#include "hw/sparc/sparc32_dma.h" #include "hw/net/lance.h" #include "trace.h" #include "sysemu/sysemu.h" diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index efaff5849d..dd0038095b 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -28,7 +28,6 @@ #include "hw/sysbus.h" #include "qemu/error-report.h" #include "qemu/timer.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/timer/m48t59.h" #include "hw/sparc/sparc32_dma.h" diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 311c82d2bb..b677601fc6 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "hw/sparc/sun4m_iommu.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index a8cc9c0148..4694b653a7 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "hw/sparc/sun4m.h" #include "qemu/timer.h" #include "hw/ptimer.h" #include "hw/sysbus.h" diff --git a/include/hw/sparc/sun4m.h b/include/hw/sparc/sun4m.h deleted file mode 100644 index 9e06467ac2..0000000000 --- a/include/hw/sparc/sun4m.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef SUN4M_H -#define SUN4M_H - -#include "qemu-common.h" -#include "exec/hwaddr.h" -#include "qapi/qmp/types.h" -#include "hw/sysbus.h" - -/* Devices used by sparc32 system. */ - -/* sparc32_dma.c */ -#include "hw/sparc/sparc32_dma.h" - -#endif -- cgit v1.2.3-55-g7522 From aea5b071012d3507885724362913d0b71dd6c303 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: apb: QOMify IOMMU This is in preparation to split the IOMMU device out of the APB. As part of this commit we also enforce separation of the IOMMU and APB devices by using a QOM object link to pass the IOMMU reference and accessing the IOMMU registers via a separate memory region mapped into the APB config space rather than directly. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 77 +++++++++++++++++++++++++++++++++++------------ hw/sparc64/sun4u.c | 7 ++++- include/hw/pci-host/apb.h | 8 ++++- 3 files changed, 70 insertions(+), 22 deletions(-) (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 44b08c090e..060e6e6d1c 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -36,6 +36,7 @@ #include "hw/pci-host/apb.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" +#include "qapi/error.h" #include "qemu/log.h" /* debug APB */ @@ -250,8 +251,8 @@ static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, return ret; } -static void iommu_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void iommu_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { IOMMUState *is = opaque; @@ -295,7 +296,7 @@ static void iommu_config_write(void *opaque, hwaddr addr, } } -static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size) +static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) { IOMMUState *is = opaque; uint64_t val; @@ -344,7 +345,6 @@ static void apb_config_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) { APBState *s = opaque; - IOMMUState *is = &s->iommu; APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val); @@ -352,9 +352,6 @@ static void apb_config_writel (void *opaque, hwaddr addr, case 0x30 ... 0x4f: /* DMA error registers */ /* XXX: not implemented yet */ break; - case 0x200 ... 0x217: /* IOMMU */ - iommu_config_write(is, (addr & 0x1f), val, size); - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { unsigned int ino = (addr & 0x3f) >> 3; @@ -426,7 +423,6 @@ static uint64_t apb_config_readl (void *opaque, hwaddr addr, unsigned size) { APBState *s = opaque; - IOMMUState *is = &s->iommu; uint32_t val; switch (addr & 0xffff) { @@ -434,9 +430,6 @@ static uint64_t apb_config_readl (void *opaque, val = 0; /* XXX: not implemented yet */ break; - case 0x200 ... 0x217: /* IOMMU */ - val = iommu_config_read(is, (addr & 0x1f), size); - break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { val = s->pci_irq_map[(addr & 0x3f) >> 3]; @@ -643,7 +636,6 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp) PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(s); PCIDevice *pci_dev; - IOMMUState *is; /* apb_config */ sysbus_mmio_map(sbd, 0, s->special_base); @@ -665,14 +657,9 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp) pci_create_simple(phb->bus, 0, "pbm-pci"); /* APB IOMMU */ - is = &s->iommu; - memset(is, 0, sizeof(IOMMUState)); - - memory_region_init_iommu(&is->iommu, sizeof(is->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(dev), - "iommu-apb", UINT64_MAX); - address_space_init(&is->iommu_as, MEMORY_REGION(&is->iommu), "pbm-as"); - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, is); + memory_region_add_subregion_overlap(&s->apb_config, 0x200, + sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); + pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu); /* APB secondary busses */ pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, @@ -708,6 +695,12 @@ static void pci_pbm_init(Object *obj) s->irq_request = NO_IRQ_REQUEST; s->pci_irq_in = 0ULL; + /* IOMMU */ + object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU, + (Object **) &s->iommu, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + /* apb_config */ memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s, "apb-config", 0x10000); @@ -814,6 +807,49 @@ static const TypeInfo pbm_pci_bridge_info = { }, }; +static const MemoryRegionOps iommu_mem_ops = { + .read = iommu_mem_read, + .write = iommu_mem_write, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void iommu_reset(DeviceState *d) +{ + IOMMUState *s = SUN4U_IOMMU(d); + + memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); +} + +static void iommu_init(Object *obj) +{ + IOMMUState *s = SUN4U_IOMMU(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-apb", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + + memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", + IOMMU_NREGS * sizeof(uint64_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = iommu_reset; +} + +static const TypeInfo pbm_iommu_info = { + .name = TYPE_SUN4U_IOMMU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IOMMUState), + .instance_init = iommu_init, + .class_init = iommu_class_init, +}; + static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data) { IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); @@ -832,6 +868,7 @@ static void pbm_register_types(void) type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); type_register_static(&pbm_pci_bridge_info); + type_register_static(&pbm_iommu_info); type_register_static(&pbm_iommu_memory_region_info); } diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 5d802bdfde..aaee3de03a 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -469,7 +469,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, PCIDevice *ebus, *pci_dev; SysBusDevice *s; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - DeviceState *dev; + DeviceState *iommu, *dev; FWCfgState *fw_cfg; NICInfo *nd; MACAddr macaddr; @@ -478,6 +478,10 @@ static void sun4uv_init(MemoryRegion *address_space_mem, /* init CPUs */ cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); + /* IOMMU */ + iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); + qdev_init_nofail(iommu); + /* set up devices */ ram_init(0, machine->ram_size); @@ -487,6 +491,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, apb = APB_DEVICE(qdev_create(NULL, TYPE_APB)); qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); + object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort); qdev_init_nofail(DEVICE(apb)); /* Wire up PCI interrupts to CPU */ diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 6194c8cbad..33dbc7a8cb 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -44,12 +44,18 @@ #define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL typedef struct IOMMUState { + SysBusDevice parent_obj; + AddressSpace iommu_as; IOMMUMemoryRegion iommu; + MemoryRegion iomem; uint64_t regs[IOMMU_NREGS]; } IOMMUState; +#define TYPE_SUN4U_IOMMU "sun4u-iommu" +#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) + #define MAX_IVEC 0x40 /* OBIO IVEC IRQs */ @@ -78,7 +84,7 @@ typedef struct APBState { MemoryRegion pci_mmio; MemoryRegion pci_ioport; uint64_t pci_irq_in; - IOMMUState iommu; + IOMMUState *iommu; PCIBridge *bridgeA; PCIBridge *bridgeB; uint32_t pci_control[16]; -- cgit v1.2.3-55-g7522 From 0ea833c24999093be6369f9145333bd10acfad76 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: sun4u: split IOMMU device out from apb.c to sun4u_iommu.c By separating the sun4u IOMMU device into new sun4u_iommu.c and sun4m_iommu.h files we noticeably simplify apb.c whilst bringing sun4u in line with all the other IOMMU-supporting architectures. Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/pci-host/apb.c | 273 -------------------------------- hw/sparc64/Makefile.objs | 1 + hw/sparc64/sun4u.c | 1 + hw/sparc64/sun4u_iommu.c | 350 +++++++++++++++++++++++++++++++++++++++++ include/hw/pci-host/apb.h | 57 +------ include/hw/sparc/sun4u_iommu.h | 50 ++++++ 6 files changed, 403 insertions(+), 329 deletions(-) create mode 100644 hw/sparc64/sun4u_iommu.c create mode 100644 include/hw/sparc/sun4u_iommu.h (limited to 'include/hw') diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 060e6e6d1c..3e796fb6fc 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -49,16 +49,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define APB_DPRINTF(fmt, ...) #endif -/* debug IOMMU */ -//#define DEBUG_IOMMU - -#ifdef DEBUG_IOMMU -#define IOMMU_DPRINTF(fmt, ...) \ -do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) -#else -#define IOMMU_DPRINTF(fmt, ...) -#endif - /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", @@ -136,211 +126,6 @@ static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) return &is->iommu_as; } -/* Called from RCU critical section */ -static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) -{ - IOMMUState *is = container_of(iommu, IOMMUState, iommu); - hwaddr baseaddr, offset; - uint64_t tte; - uint32_t tsbsize; - IOMMUTLBEntry ret = { - .target_as = &address_space_memory, - .iova = 0, - .translated_addr = 0, - .addr_mask = ~(hwaddr)0, - .perm = IOMMU_NONE, - }; - - if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { - /* IOMMU disabled, passthrough using standard 8K page */ - ret.iova = addr & IOMMU_PAGE_MASK_8K; - ret.translated_addr = addr; - ret.addr_mask = IOMMU_PAGE_MASK_8K; - ret.perm = IOMMU_RW; - - return ret; - } - - baseaddr = is->regs[IOMMU_BASE >> 3]; - tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; - - if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { - /* 64K */ - switch (tsbsize) { - case 0: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; - break; - case 1: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; - break; - case 2: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; - break; - case 3: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; - break; - case 4: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; - break; - case 5: - offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; - break; - default: - /* Not implemented, error */ - return ret; - } - } else { - /* 8K */ - switch (tsbsize) { - case 0: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; - break; - case 1: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; - break; - case 2: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; - break; - case 3: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; - break; - case 4: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; - break; - case 5: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; - break; - case 6: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; - break; - case 7: - offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; - break; - } - } - - tte = address_space_ldq_be(&address_space_memory, baseaddr + offset, - MEMTXATTRS_UNSPECIFIED, NULL); - - if (!(tte & IOMMU_TTE_DATA_V)) { - /* Invalid mapping */ - return ret; - } - - if (tte & IOMMU_TTE_DATA_W) { - /* Writeable */ - ret.perm = IOMMU_RW; - } else { - ret.perm = IOMMU_RO; - } - - /* Extract phys */ - if (tte & IOMMU_TTE_DATA_SIZE) { - /* 64K */ - ret.iova = addr & IOMMU_PAGE_MASK_64K; - ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K; - ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1); - } else { - /* 8K */ - ret.iova = addr & IOMMU_PAGE_MASK_8K; - ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K; - ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1); - } - - return ret; -} - -static void iommu_mem_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - IOMMUState *is = opaque; - - IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); - - switch (addr) { - case IOMMU_CTRL: - if (size == 4) { - is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; - is->regs[IOMMU_CTRL >> 3] |= val << 32; - } else { - is->regs[IOMMU_CTRL >> 3] = val; - } - break; - case IOMMU_CTRL + 0x4: - is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; - is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL; - break; - case IOMMU_BASE: - if (size == 4) { - is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; - is->regs[IOMMU_BASE >> 3] |= val << 32; - } else { - is->regs[IOMMU_BASE >> 3] = val; - } - break; - case IOMMU_BASE + 0x4: - is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; - is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; - break; - case IOMMU_FLUSH: - case IOMMU_FLUSH + 0x4: - break; - default: - qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register write " - "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", - addr, size, val); - break; - } -} - -static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) -{ - IOMMUState *is = opaque; - uint64_t val; - - switch (addr) { - case IOMMU_CTRL: - if (size == 4) { - val = is->regs[IOMMU_CTRL >> 3] >> 32; - } else { - val = is->regs[IOMMU_CTRL >> 3]; - } - break; - case IOMMU_CTRL + 0x4: - val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; - break; - case IOMMU_BASE: - if (size == 4) { - val = is->regs[IOMMU_BASE >> 3] >> 32; - } else { - val = is->regs[IOMMU_BASE >> 3]; - } - break; - case IOMMU_BASE + 0x4: - val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; - break; - case IOMMU_FLUSH: - case IOMMU_FLUSH + 0x4: - val = 0; - break; - default: - qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register read " - "reg 0x%" HWADDR_PRIx " size 0x%x\n", - addr, size); - val = 0; - break; - } - - IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 - " size: %d\n", addr, val, size); - - return val; -} - static void apb_config_writel (void *opaque, hwaddr addr, uint64_t val, unsigned size) { @@ -807,69 +592,11 @@ static const TypeInfo pbm_pci_bridge_info = { }, }; -static const MemoryRegionOps iommu_mem_ops = { - .read = iommu_mem_read, - .write = iommu_mem_write, - .endianness = DEVICE_BIG_ENDIAN, -}; - -static void iommu_reset(DeviceState *d) -{ - IOMMUState *s = SUN4U_IOMMU(d); - - memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); -} - -static void iommu_init(Object *obj) -{ - IOMMUState *s = SUN4U_IOMMU(obj); - SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - - memory_region_init_iommu(&s->iommu, sizeof(s->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), - "iommu-apb", UINT64_MAX); - address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); - - memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", - IOMMU_NREGS * sizeof(uint64_t)); - sysbus_init_mmio(sbd, &s->iomem); -} - -static void iommu_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->reset = iommu_reset; -} - -static const TypeInfo pbm_iommu_info = { - .name = TYPE_SUN4U_IOMMU, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(IOMMUState), - .instance_init = iommu_init, - .class_init = iommu_class_init, -}; - -static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data) -{ - IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); - - imrc->translate = pbm_translate_iommu; -} - -static const TypeInfo pbm_iommu_memory_region_info = { - .parent = TYPE_IOMMU_MEMORY_REGION, - .name = TYPE_APB_IOMMU_MEMORY_REGION, - .class_init = pbm_iommu_memory_region_class_init, -}; - static void pbm_register_types(void) { type_register_static(&pbm_host_info); type_register_static(&pbm_pci_host_info); type_register_static(&pbm_pci_bridge_info); - type_register_static(&pbm_iommu_info); - type_register_static(&pbm_iommu_memory_region_info); } type_init(pbm_register_types) diff --git a/hw/sparc64/Makefile.objs b/hw/sparc64/Makefile.objs index cf9de21133..117e0ff27d 100644 --- a/hw/sparc64/Makefile.objs +++ b/hw/sparc64/Makefile.objs @@ -1,3 +1,4 @@ obj-y += sparc64.o +obj-y += sun4u_iommu.o obj-y += sun4u.o obj-y += niagara.o \ No newline at end of file diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index aaee3de03a..ec45ec2801 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -29,6 +29,7 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" +#include "hw/pci/pci_host.h" #include "hw/pci-host/apb.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c new file mode 100644 index 0000000000..e5aa817edb --- /dev/null +++ b/hw/sparc64/sun4u_iommu.c @@ -0,0 +1,350 @@ +/* + * QEMU sun4u IOMMU emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/sparc/sun4u_iommu.h" +#include "exec/address-spaces.h" +#include "qapi/error.h" +#include "qemu/log.h" + +/* debug IOMMU */ +//#define DEBUG_IOMMU + +#ifdef DEBUG_IOMMU +#define IOMMU_DPRINTF(fmt, ...) \ +do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) +#else +#define IOMMU_DPRINTF(fmt, ...) +#endif + + +#define IOMMU_PAGE_SIZE_8K (1ULL << 13) +#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) +#define IOMMU_PAGE_SIZE_64K (1ULL << 16) +#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) + +#define IOMMU_CTRL 0x0 +#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) +#define IOMMU_CTRL_MMU_EN (1ULL) + +#define IOMMU_CTRL_TSB_SHIFT 16 + +#define IOMMU_BASE 0x8 +#define IOMMU_FLUSH 0x10 + +#define IOMMU_TTE_DATA_V (1ULL << 63) +#define IOMMU_TTE_DATA_SIZE (1ULL << 61) +#define IOMMU_TTE_DATA_W (1ULL << 1) + +#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL +#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL + +#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL +#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL + +#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL +#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL + + +/* Called from RCU critical section */ +static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, + IOMMUAccessFlags flag) +{ + IOMMUState *is = container_of(iommu, IOMMUState, iommu); + hwaddr baseaddr, offset; + uint64_t tte; + uint32_t tsbsize; + IOMMUTLBEntry ret = { + .target_as = &address_space_memory, + .iova = 0, + .translated_addr = 0, + .addr_mask = ~(hwaddr)0, + .perm = IOMMU_NONE, + }; + + if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { + /* IOMMU disabled, passthrough using standard 8K page */ + ret.iova = addr & IOMMU_PAGE_MASK_8K; + ret.translated_addr = addr; + ret.addr_mask = IOMMU_PAGE_MASK_8K; + ret.perm = IOMMU_RW; + + return ret; + } + + baseaddr = is->regs[IOMMU_BASE >> 3]; + tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; + + if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { + /* 64K */ + switch (tsbsize) { + case 0: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13; + break; + case 1: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13; + break; + case 2: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13; + break; + case 3: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13; + break; + case 4: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13; + break; + case 5: + offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13; + break; + default: + /* Not implemented, error */ + return ret; + } + } else { + /* 8K */ + switch (tsbsize) { + case 0: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10; + break; + case 1: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10; + break; + case 2: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10; + break; + case 3: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10; + break; + case 4: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10; + break; + case 5: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10; + break; + case 6: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10; + break; + case 7: + offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10; + break; + } + } + + tte = address_space_ldq_be(&address_space_memory, baseaddr + offset, + MEMTXATTRS_UNSPECIFIED, NULL); + + if (!(tte & IOMMU_TTE_DATA_V)) { + /* Invalid mapping */ + return ret; + } + + if (tte & IOMMU_TTE_DATA_W) { + /* Writeable */ + ret.perm = IOMMU_RW; + } else { + ret.perm = IOMMU_RO; + } + + /* Extract phys */ + if (tte & IOMMU_TTE_DATA_SIZE) { + /* 64K */ + ret.iova = addr & IOMMU_PAGE_MASK_64K; + ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K; + ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1); + } else { + /* 8K */ + ret.iova = addr & IOMMU_PAGE_MASK_8K; + ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K; + ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1); + } + + return ret; +} + +static void iommu_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + IOMMUState *is = opaque; + + IOMMU_DPRINTF("IOMMU config write: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + switch (addr) { + case IOMMU_CTRL: + if (size == 4) { + is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; + is->regs[IOMMU_CTRL >> 3] |= val << 32; + } else { + is->regs[IOMMU_CTRL >> 3] = val; + } + break; + case IOMMU_CTRL + 0x4: + is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; + is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size == 4) { + is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL; + is->regs[IOMMU_BASE >> 3] |= val << 32; + } else { + is->regs[IOMMU_BASE >> 3] = val; + } + break; + case IOMMU_BASE + 0x4: + is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; + is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; + break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register write " + "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", + addr, size, val); + break; + } +} + +static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + IOMMUState *is = opaque; + uint64_t val; + + switch (addr) { + case IOMMU_CTRL: + if (size == 4) { + val = is->regs[IOMMU_CTRL >> 3] >> 32; + } else { + val = is->regs[IOMMU_CTRL >> 3]; + } + break; + case IOMMU_CTRL + 0x4: + val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL; + break; + case IOMMU_BASE: + if (size == 4) { + val = is->regs[IOMMU_BASE >> 3] >> 32; + } else { + val = is->regs[IOMMU_BASE >> 3]; + } + break; + case IOMMU_BASE + 0x4: + val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; + break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + val = 0; + break; + default: + qemu_log_mask(LOG_UNIMP, + "apb iommu: Unimplemented register read " + "reg 0x%" HWADDR_PRIx " size 0x%x\n", + addr, size); + val = 0; + break; + } + + IOMMU_DPRINTF("IOMMU config read: 0x%" HWADDR_PRIx " val: %" PRIx64 + " size: %d\n", addr, val, size); + + return val; +} + +static const MemoryRegionOps iommu_mem_ops = { + .read = iommu_mem_read, + .write = iommu_mem_write, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void iommu_reset(DeviceState *d) +{ + IOMMUState *s = SUN4U_IOMMU(d); + + memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t)); +} + +static void iommu_init(Object *obj) +{ + IOMMUState *s = SUN4U_IOMMU(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_iommu(&s->iommu, sizeof(s->iommu), + TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-apb", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + + memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", + IOMMU_NREGS * sizeof(uint64_t)); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void iommu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = iommu_reset; +} + +static const TypeInfo pbm_iommu_info = { + .name = TYPE_SUN4U_IOMMU, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IOMMUState), + .instance_init = iommu_init, + .class_init = iommu_class_init, +}; + +static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data) +{ + IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); + + imrc->translate = pbm_translate_iommu; +} + +static const TypeInfo pbm_iommu_memory_region_info = { + .parent = TYPE_IOMMU_MEMORY_REGION, + .name = TYPE_APB_IOMMU_MEMORY_REGION, + .class_init = pbm_iommu_memory_region_class_init, +}; + +static void pbm_register_types(void) +{ + type_register_static(&pbm_iommu_info); + type_register_static(&pbm_iommu_memory_region_info); +} + +type_init(pbm_register_types) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/apb.h index 33dbc7a8cb..604d899b1e 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/apb.h @@ -1,60 +1,7 @@ #ifndef PCI_HOST_APB_H #define PCI_HOST_APB_H -#include "qemu-common.h" -#include "hw/pci/pci_host.h" - -#define IOMMU_NREGS 3 - -#define IOMMU_PAGE_SIZE_8K (1ULL << 13) -#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1)) -#define IOMMU_PAGE_SIZE_64K (1ULL << 16) -#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1)) - -#define IOMMU_CTRL 0x0 -#define IOMMU_CTRL_TBW_SIZE (1ULL << 2) -#define IOMMU_CTRL_MMU_EN (1ULL) - -#define IOMMU_CTRL_TSB_SHIFT 16 - -#define IOMMU_BASE 0x8 -#define IOMMU_FLUSH 0x10 - -#define IOMMU_TTE_DATA_V (1ULL << 63) -#define IOMMU_TTE_DATA_SIZE (1ULL << 61) -#define IOMMU_TTE_DATA_W (1ULL << 1) - -#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL -#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL - -#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL -#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL - -#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL -#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL - -typedef struct IOMMUState { - SysBusDevice parent_obj; - - AddressSpace iommu_as; - IOMMUMemoryRegion iommu; - - MemoryRegion iomem; - uint64_t regs[IOMMU_NREGS]; -} IOMMUState; - -#define TYPE_SUN4U_IOMMU "sun4u-iommu" -#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) +#include "hw/sparc/sun4u_iommu.h" #define MAX_IVEC 0x40 @@ -72,8 +19,6 @@ typedef struct IOMMUState { #define APB_DEVICE(obj) \ OBJECT_CHECK(APBState, (obj), TYPE_APB) -#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" - typedef struct APBState { PCIHostState parent_obj; diff --git a/include/hw/sparc/sun4u_iommu.h b/include/hw/sparc/sun4u_iommu.h new file mode 100644 index 0000000000..bc4506b5b0 --- /dev/null +++ b/include/hw/sparc/sun4u_iommu.h @@ -0,0 +1,50 @@ +/* + * QEMU sun4u IOMMU emulation + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SUN4U_IOMMU_H +#define SUN4U_IOMMU_H + +#include "qemu-common.h" +#include "hw/sysbus.h" + +#define IOMMU_NREGS 3 + +typedef struct IOMMUState { + SysBusDevice parent_obj; + + AddressSpace iommu_as; + IOMMUMemoryRegion iommu; + + MemoryRegion iomem; + uint64_t regs[IOMMU_NREGS]; +} IOMMUState; + +#define TYPE_SUN4U_IOMMU "sun4u-iommu" +#define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) + +#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" + +#endif -- cgit v1.2.3-55-g7522 From 4c9fbc38e3559d7540c8bd5cf76915dd21ccad7f Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 8 Jan 2018 18:16:34 +0000 Subject: sun4u_iommu: update to reflect IOMMU is no longer part of the APB device Signed-off-by: Mark Cave-Ayland Acked-by: Artyom Tarasenko --- hw/sparc64/sun4u_iommu.c | 35 ++++++++++++++++++----------------- include/hw/sparc/sun4u_iommu.h | 2 +- 2 files changed, 19 insertions(+), 18 deletions(-) (limited to 'include/hw') diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index e5aa817edb..612fec4c64 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -81,8 +81,9 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) /* Called from RCU critical section */ -static IOMMUTLBEntry pbm_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) +static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, + hwaddr addr, + IOMMUAccessFlags flag) { IOMMUState *is = container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; @@ -233,7 +234,7 @@ static void iommu_mem_write(void *opaque, hwaddr addr, break; default: qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register write " + "sun4u-iommu: Unimplemented register write " "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n", addr, size, val); break; @@ -272,7 +273,7 @@ static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size) break; default: qemu_log_mask(LOG_UNIMP, - "apb iommu: Unimplemented register read " + "sun4u-iommu: Unimplemented register read " "reg 0x%" HWADDR_PRIx " size 0x%x\n", addr, size); val = 0; @@ -304,9 +305,9 @@ static void iommu_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); memory_region_init_iommu(&s->iommu, sizeof(s->iommu), - TYPE_APB_IOMMU_MEMORY_REGION, OBJECT(s), - "iommu-apb", UINT64_MAX); - address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "pbm-as"); + TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s), + "iommu-sun4u", UINT64_MAX); + address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as"); memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu", IOMMU_NREGS * sizeof(uint64_t)); @@ -320,7 +321,7 @@ static void iommu_class_init(ObjectClass *klass, void *data) dc->reset = iommu_reset; } -static const TypeInfo pbm_iommu_info = { +static const TypeInfo iommu_info = { .name = TYPE_SUN4U_IOMMU, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IOMMUState), @@ -328,23 +329,23 @@ static const TypeInfo pbm_iommu_info = { .class_init = iommu_class_init, }; -static void pbm_iommu_memory_region_class_init(ObjectClass *klass, void *data) +static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void *data) { IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); - imrc->translate = pbm_translate_iommu; + imrc->translate = sun4u_translate_iommu; } -static const TypeInfo pbm_iommu_memory_region_info = { +static const TypeInfo sun4u_iommu_memory_region_info = { .parent = TYPE_IOMMU_MEMORY_REGION, - .name = TYPE_APB_IOMMU_MEMORY_REGION, - .class_init = pbm_iommu_memory_region_class_init, + .name = TYPE_SUN4U_IOMMU_MEMORY_REGION, + .class_init = sun4u_iommu_memory_region_class_init, }; -static void pbm_register_types(void) +static void iommu_register_types(void) { - type_register_static(&pbm_iommu_info); - type_register_static(&pbm_iommu_memory_region_info); + type_register_static(&iommu_info); + type_register_static(&sun4u_iommu_memory_region_info); } -type_init(pbm_register_types) +type_init(iommu_register_types) diff --git a/include/hw/sparc/sun4u_iommu.h b/include/hw/sparc/sun4u_iommu.h index bc4506b5b0..a760172e8e 100644 --- a/include/hw/sparc/sun4u_iommu.h +++ b/include/hw/sparc/sun4u_iommu.h @@ -45,6 +45,6 @@ typedef struct IOMMUState { #define TYPE_SUN4U_IOMMU "sun4u-iommu" #define SUN4U_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4U_IOMMU) -#define TYPE_APB_IOMMU_MEMORY_REGION "pbm-iommu-memory-region" +#define TYPE_SUN4U_IOMMU_MEMORY_REGION "sun4u-iommu-memory-region" #endif -- cgit v1.2.3-55-g7522 From 7709dbf12c0bb9a86c186c2c0f7ae67ce363dc80 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 16 Dec 2017 23:42:14 +0100 Subject: ppc4xx_i2c: Implement basic I2C functions Enough to please U-Boot and make it able to detect SDRAM SPD EEPROMs Signed-off-by: François Revol Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/i2c/ppc4xx_i2c.c | 198 +++++++++++++++++++++++++++++++++++++------- include/hw/i2c/ppc4xx_i2c.h | 3 + 2 files changed, 171 insertions(+), 30 deletions(-) (limited to 'include/hw') diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index 5a6bde951e..e873a445da 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -2,6 +2,8 @@ * PPC4xx I2C controller emulation * * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2012 François Revol + * Copyright (c) 2016 BALATON Zoltan * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,26 +27,118 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" +#include "qemu/log.h" #include "cpu.h" #include "hw/hw.h" #include "hw/i2c/ppc4xx_i2c.h" -/*#define DEBUG_I2C*/ +#define PPC4xx_I2C_MEM_SIZE 0x12 -#define PPC4xx_I2C_MEM_SIZE 0x11 +#define IIC_CNTL_PT (1 << 0) +#define IIC_CNTL_READ (1 << 1) +#define IIC_CNTL_CHT (1 << 2) +#define IIC_CNTL_RPST (1 << 3) + +#define IIC_STS_PT (1 << 0) +#define IIC_STS_ERR (1 << 2) +#define IIC_STS_MDBS (1 << 5) + +#define IIC_EXTSTS_XFRA (1 << 0) + +#define IIC_XTCNTLSS_SRST (1 << 0) + +static void ppc4xx_i2c_reset(DeviceState *s) +{ + PPC4xxI2CState *i2c = PPC4xx_I2C(s); + + /* FIXME: Should also reset bus? + *if (s->address != ADDR_RESET) { + * i2c_end_transfer(s->bus); + *} + */ + + i2c->mdata = 0; + i2c->lmadr = 0; + i2c->hmadr = 0; + i2c->cntl = 0; + i2c->mdcntl = 0; + i2c->sts = 0; + i2c->extsts = 0x8f; + i2c->sdata = 0; + i2c->lsadr = 0; + i2c->hsadr = 0; + i2c->clkdiv = 0; + i2c->intrmsk = 0; + i2c->xfrcnt = 0; + i2c->xtcntlss = 0; + i2c->directcntl = 0x0f; + i2c->intr = 0; +} + +static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c) +{ + return true; +} static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) { PPC4xxI2CState *i2c = PPC4xx_I2C(opaque); uint64_t ret; -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); -#endif switch (addr) { case 0x00: - /*i2c_readbyte(&i2c->mdata);*/ ret = i2c->mdata; + if (ppc4xx_i2c_is_master(i2c)) { + ret = 0xff; + + if (!(i2c->sts & IIC_STS_MDBS)) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read " + "without starting transfer\n", + TYPE_PPC4xx_I2C, __func__); + } else { + int pending = (i2c->cntl >> 4) & 3; + + /* get the next byte */ + int byte = i2c_recv(i2c->bus); + + if (byte < 0) { + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed " + "for device 0x%02x\n", TYPE_PPC4xx_I2C, + __func__, i2c->lmadr); + ret = 0xff; + } else { + ret = byte; + /* Raise interrupt if enabled */ + /*ppc4xx_i2c_raise_interrupt(i2c)*/; + } + + if (!pending) { + i2c->sts &= ~IIC_STS_MDBS; + /*i2c_end_transfer(i2c->bus);*/ + /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/ + } else if (pending) { + /* current smbus implementation doesn't like + multibyte xfer repeated start */ + i2c_end_transfer(i2c->bus); + if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { + /* if non zero is returned, the adress is not valid */ + i2c->sts &= ~IIC_STS_PT; + i2c->sts |= IIC_STS_ERR; + i2c->extsts |= IIC_EXTSTS_XFRA; + } else { + /*i2c->sts |= IIC_STS_PT;*/ + i2c->sts |= IIC_STS_MDBS; + i2c->sts &= ~IIC_STS_ERR; + i2c->extsts = 0; + } + } + pending--; + i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4); + } + } else { + qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n", + TYPE_PPC4xx_I2C, __func__); + } break; case 0x02: ret = i2c->sdata; @@ -88,13 +182,15 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) case 0x10: ret = i2c->directcntl; break; + case 0x11: + ret = i2c->intr; + break; default: - ret = 0x00; + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" + HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + ret = 0; break; } -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " %02" PRIx64 "\n", __func__, addr, ret); -#endif return ret; } @@ -103,26 +199,70 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { PPC4xxI2CState *i2c = opaque; -#ifdef DEBUG_I2C - printf("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", - __func__, addr, value); -#endif + switch (addr) { case 0x00: i2c->mdata = value; - /*i2c_sendbyte(&i2c->mdata);*/ + if (!i2c_bus_busy(i2c->bus)) { + /* assume we start a write transfer */ + if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) { + /* if non zero is returned, the adress is not valid */ + i2c->sts &= ~IIC_STS_PT; + i2c->sts |= IIC_STS_ERR; + i2c->extsts |= IIC_EXTSTS_XFRA; + } else { + i2c->sts |= IIC_STS_PT; + i2c->sts &= ~IIC_STS_ERR; + i2c->extsts = 0; + } + } + if (i2c_bus_busy(i2c->bus)) { + if (i2c_send(i2c->bus, i2c->mdata)) { + /* if the target return non zero then end the transfer */ + i2c->sts &= ~IIC_STS_PT; + i2c->sts |= IIC_STS_ERR; + i2c->extsts |= IIC_EXTSTS_XFRA; + i2c_end_transfer(i2c->bus); + } + } break; case 0x02: i2c->sdata = value; break; case 0x04: i2c->lmadr = value; + if (i2c_bus_busy(i2c->bus)) { + i2c_end_transfer(i2c->bus); + } break; case 0x05: i2c->hmadr = value; break; case 0x06: i2c->cntl = value; + if (i2c->cntl & IIC_CNTL_PT) { + if (i2c->cntl & IIC_CNTL_READ) { + if (i2c_bus_busy(i2c->bus)) { + /* end previous transfer */ + i2c->sts &= ~IIC_STS_PT; + i2c_end_transfer(i2c->bus); + } + if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) { + /* if non zero is returned, the adress is not valid */ + i2c->sts &= ~IIC_STS_PT; + i2c->sts |= IIC_STS_ERR; + i2c->extsts |= IIC_EXTSTS_XFRA; + } else { + /*i2c->sts |= IIC_STS_PT;*/ + i2c->sts |= IIC_STS_MDBS; + i2c->sts &= ~IIC_STS_ERR; + i2c->extsts = 0; + } + } else { + /* we actually already did the write transfer... */ + i2c->sts &= ~IIC_STS_PT; + } + } break; case 0x07: i2c->mdcntl = value & 0xDF; @@ -135,6 +275,7 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, break; case 0x0A: i2c->lsadr = value; + /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/ break; case 0x0B: i2c->hsadr = value; @@ -149,11 +290,23 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, i2c->xfrcnt = value & 0x77; break; case 0x0F: + if (value & IIC_XTCNTLSS_SRST) { + /* Is it actually a full reset? U-Boot sets some regs before */ + ppc4xx_i2c_reset(DEVICE(i2c)); + break; + } i2c->xtcntlss = value; break; case 0x10: i2c->directcntl = value & 0x7; break; + case 0x11: + i2c->intr = value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" + HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + break; } } @@ -167,21 +320,6 @@ static const MemoryRegionOps ppc4xx_i2c_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void ppc4xx_i2c_reset(DeviceState *s) -{ - PPC4xxI2CState *i2c = PPC4xx_I2C(s); - - i2c->mdata = 0x00; - i2c->sdata = 0x00; - i2c->cntl = 0x00; - i2c->mdcntl = 0x00; - i2c->sts = 0x00; - i2c->extsts = 0x00; - i2c->clkdiv = 0x00; - i2c->xfrcnt = 0x00; - i2c->directcntl = 0x0F; -} - static void ppc4xx_i2c_init(Object *o) { PPC4xxI2CState *s = PPC4xx_I2C(o); diff --git a/include/hw/i2c/ppc4xx_i2c.h b/include/hw/i2c/ppc4xx_i2c.h index 3450bda577..3c603071bd 100644 --- a/include/hw/i2c/ppc4xx_i2c.h +++ b/include/hw/i2c/ppc4xx_i2c.h @@ -2,6 +2,8 @@ * PPC4xx I2C controller emulation * * Copyright (c) 2007 Jocelyn Mayer + * Copyright (c) 2012 François Revol + * Copyright (c) 2016 BALATON Zoltan * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -55,6 +57,7 @@ typedef struct PPC4xxI2CState { uint8_t xfrcnt; uint8_t xtcntlss; uint8_t directcntl; + uint8_t intr; } PPC4xxI2CState; #endif /* PPC4XX_I2C_H */ -- cgit v1.2.3-55-g7522 From b168a138a8bc9c18e8140fef614a6b66721497fb Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Fri, 15 Dec 2017 14:56:01 +0100 Subject: ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency The 'pnv' prefix is now used for all and the routines populating the device tree start with 'pnv_dt'. The handler of the PnvXScomInterface is also renamed to 'dt_xscom' which should reflect that it is populating the device tree under the 'xscom@' node of the chip. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 94 ++++++++++++++++++++++------------------------ hw/ppc/pnv_bmc.c | 2 +- hw/ppc/pnv_core.c | 8 ++-- hw/ppc/pnv_lpc.c | 6 +-- hw/ppc/pnv_psi.c | 4 +- hw/ppc/pnv_xscom.c | 10 ++--- include/hw/ppc/pnv.h | 10 ++--- include/hw/ppc/pnv_xscom.h | 4 +- 8 files changed, 67 insertions(+), 71 deletions(-) (limited to 'include/hw') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 94ffc8e137..9475e8479c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -77,8 +77,7 @@ static const char *pnv_chip_core_typename(const PnvChip *o) * that has a different "affinity". In practice, it means one range * per chip. */ -static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, - hwaddr size) +static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) { char *mem_name; uint64_t mem_reg_property[2]; @@ -119,7 +118,7 @@ static int get_cpus_node(void *fdt) * device tree, used in XSCOM to address cores and in interrupt * servers. */ -static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) +static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) { CPUState *cs = CPU(DEVICE(pc->threads)); DeviceClass *dc = DEVICE_GET_CLASS(cs); @@ -228,8 +227,8 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) servers_prop, sizeof(servers_prop)))); } -static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir, - uint32_t nr_threads) +static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, + uint32_t nr_threads) { uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); char *name; @@ -277,13 +276,13 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) return offset; } -static void powernv_populate_chip(PnvChip *chip, void *fdt) +static void pnv_dt_chip(PnvChip *chip, void *fdt) { const char *typename = pnv_chip_core_typename(chip); size_t typesize = object_type_get_instance_size(typename); int i; - pnv_xscom_populate(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0); /* The default LPC bus of a multichip system is on chip 0. It's * recognized by the firmware (skiboot) using a "primary" @@ -298,20 +297,18 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt) for (i = 0; i < chip->nr_cores; i++) { PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); - powernv_create_core_node(chip, pnv_core, fdt); + pnv_dt_core(chip, pnv_core, fdt); /* Interrupt Control Presenters (ICP). One per core. */ - powernv_populate_icp(chip, fdt, pnv_core->pir, - CPU_CORE(pnv_core)->nr_threads); + pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); } if (chip->ram_size) { - powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, - chip->ram_size); + pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } } -static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) +static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) { uint32_t io_base = d->ioport_id; uint32_t io_regs[] = { @@ -331,7 +328,7 @@ static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); } -static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off) +static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) { const char compatible[] = "ns16550\0pnpPNP,501"; uint32_t io_base = d->ioport_id; @@ -362,7 +359,7 @@ static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off) _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); } -static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) +static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) { const char compatible[] = "bt\0ipmi-bt"; uint32_t io_base; @@ -401,17 +398,17 @@ typedef struct ForeachPopulateArgs { int offset; } ForeachPopulateArgs; -static int powernv_populate_isa_device(DeviceState *dev, void *opaque) +static int pnv_dt_isa_device(DeviceState *dev, void *opaque) { ForeachPopulateArgs *args = opaque; ISADevice *d = ISA_DEVICE(dev); if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { - powernv_populate_rtc(d, args->fdt, args->offset); + pnv_dt_rtc(d, args->fdt, args->offset); } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { - powernv_populate_serial(d, args->fdt, args->offset); + pnv_dt_serial(d, args->fdt, args->offset); } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { - powernv_populate_ipmi_bt(d, args->fdt, args->offset); + pnv_dt_ipmi_bt(d, args->fdt, args->offset); } else { error_report("unknown isa device %s@i%x", qdev_fw_name(dev), d->ioport_id); @@ -420,7 +417,7 @@ static int powernv_populate_isa_device(DeviceState *dev, void *opaque) return 0; } -static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) +static void pnv_dt_isa(ISABus *bus, void *fdt, int lpc_offset) { ForeachPopulateArgs args = { .fdt = fdt, @@ -429,14 +426,13 @@ static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) /* ISA devices are not necessarily parented to the ISA bus so we * can not use object_child_foreach() */ - qbus_walk_children(BUS(bus), powernv_populate_isa_device, - NULL, NULL, NULL, &args); + qbus_walk_children(BUS(bus), pnv_dt_isa_device, NULL, NULL, NULL, &args); } -static void *powernv_create_fdt(MachineState *machine) +static void *pnv_dt_create(MachineState *machine) { const char plat_compat[] = "qemu,powernv\0ibm,powernv"; - PnvMachineState *pnv = POWERNV_MACHINE(machine); + PnvMachineState *pnv = PNV_MACHINE(machine); void *fdt; char *buf; int off; @@ -479,15 +475,15 @@ static void *powernv_create_fdt(MachineState *machine) /* Populate device tree for each chip */ for (i = 0; i < pnv->num_chips; i++) { - powernv_populate_chip(pnv->chips[i], fdt); + pnv_dt_chip(pnv->chips[i], fdt); } /* Populate ISA devices on chip 0 */ lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt); - powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); + pnv_dt_isa(pnv->isa_bus, fdt, lpc_offset); if (pnv->bmc) { - pnv_bmc_populate_sensors(pnv->bmc, fdt); + pnv_dt_bmc_sensors(pnv->bmc, fdt); } return fdt; @@ -495,17 +491,17 @@ static void *powernv_create_fdt(MachineState *machine) static void pnv_powerdown_notify(Notifier *n, void *opaque) { - PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine()); + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); if (pnv->bmc) { pnv_bmc_powerdown(pnv->bmc); } } -static void ppc_powernv_reset(void) +static void pnv_reset(void) { MachineState *machine = MACHINE(qdev_get_machine()); - PnvMachineState *pnv = POWERNV_MACHINE(machine); + PnvMachineState *pnv = PNV_MACHINE(machine); void *fdt; Object *obj; @@ -524,7 +520,7 @@ static void ppc_powernv_reset(void) pnv->bmc = IPMI_BMC(obj); } - fdt = powernv_create_fdt(machine); + fdt = pnv_dt_create(machine); /* Pack resulting tree */ _FDT((fdt_pack(fdt))); @@ -552,9 +548,9 @@ static ISABus *pnv_isa_create(PnvChip *chip) return isa_bus; } -static void ppc_powernv_init(MachineState *machine) +static void pnv_init(MachineState *machine) { - PnvMachineState *pnv = POWERNV_MACHINE(machine); + PnvMachineState *pnv = PNV_MACHINE(machine); MemoryRegion *ram; char *fw_filename; long fw_size; @@ -567,7 +563,7 @@ static void ppc_powernv_init(MachineState *machine) } ram = g_new(MemoryRegion, 1); - memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", + memory_region_allocate_system_memory(ram, NULL, "pnv.ram", machine->ram_size); memory_region_add_subregion(get_system_memory(), 0, ram); @@ -974,7 +970,7 @@ static void pnv_chip_class_init(ObjectClass *klass, void *data) static ICSState *pnv_ics_get(XICSFabric *xi, int irq) { - PnvMachineState *pnv = POWERNV_MACHINE(xi); + PnvMachineState *pnv = PNV_MACHINE(xi); int i; for (i = 0; i < pnv->num_chips; i++) { @@ -987,7 +983,7 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) static void pnv_ics_resend(XICSFabric *xi) { - PnvMachineState *pnv = POWERNV_MACHINE(xi); + PnvMachineState *pnv = PNV_MACHINE(xi); int i; for (i = 0; i < pnv->num_chips; i++) { @@ -1021,7 +1017,7 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir) static void pnv_pic_print_info(InterruptStatsProvider *obj, Monitor *mon) { - PnvMachineState *pnv = POWERNV_MACHINE(obj); + PnvMachineState *pnv = PNV_MACHINE(obj); int i; CPUState *cs; @@ -1039,13 +1035,13 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); + visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); } static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - PnvMachineState *pnv = POWERNV_MACHINE(obj); + PnvMachineState *pnv = PNV_MACHINE(obj); uint32_t num_chips; Error *local_err = NULL; @@ -1067,13 +1063,13 @@ static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, pnv->num_chips = num_chips; } -static void powernv_machine_initfn(Object *obj) +static void pnv_machine_initfn(Object *obj) { - PnvMachineState *pnv = POWERNV_MACHINE(obj); + PnvMachineState *pnv = PNV_MACHINE(obj); pnv->num_chips = 1; } -static void powernv_machine_class_props_init(ObjectClass *oc) +static void pnv_machine_class_props_init(ObjectClass *oc) { object_class_property_add(oc, "num-chips", "uint32", pnv_get_num_chips, pnv_set_num_chips, @@ -1083,15 +1079,15 @@ static void powernv_machine_class_props_init(ObjectClass *oc) NULL); } -static void powernv_machine_class_init(ObjectClass *oc, void *data) +static void pnv_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized)"; - mc->init = ppc_powernv_init; - mc->reset = ppc_powernv_reset; + mc->init = pnv_init; + mc->reset = pnv_reset; mc->max_cpus = MAX_CPUS; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for @@ -1104,7 +1100,7 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data) xic->ics_resend = pnv_ics_resend; ispc->print_info = pnv_pic_print_info; - powernv_machine_class_props_init(oc); + pnv_machine_class_props_init(oc); } #define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ @@ -1116,11 +1112,11 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data) static const TypeInfo types[] = { { - .name = TYPE_POWERNV_MACHINE, + .name = TYPE_PNV_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(PnvMachineState), - .instance_init = powernv_machine_initfn, - .class_init = powernv_machine_class_init, + .instance_init = pnv_machine_initfn, + .class_init = pnv_machine_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index 7b60b4c360..b2cf441ee7 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -73,7 +73,7 @@ void pnv_bmc_powerdown(IPMIBmc *bmc) pnv_gen_oem_sel(bmc, SOFT_OFF); } -void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt) +void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt) { int offset; int i; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 03317db853..7e8a76df44 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -37,7 +37,7 @@ static const char *pnv_core_cpu_typename(PnvCore *pc) return cpu_type; } -static void powernv_cpu_reset(void *opaque) +static void pnv_cpu_reset(void *opaque) { PowerPCCPU *cpu = opaque; CPUState *cs = CPU(cpu); @@ -54,7 +54,7 @@ static void powernv_cpu_reset(void *opaque) env->msr |= MSR_HVB; /* Hypervisor mode */ } -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) +static void pnv_cpu_init(PowerPCCPU *cpu, Error **errp) { CPUPPCState *env = &cpu->env; int core_pir; @@ -73,7 +73,7 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); - qemu_register_reset(powernv_cpu_reset, cpu); + qemu_register_reset(pnv_cpu_reset, cpu); } /* @@ -139,7 +139,7 @@ static void pnv_core_realize_child(Object *child, XICSFabric *xi, Error **errp) return; } - powernv_cpu_init(cpu, &local_err); + pnv_cpu_init(cpu, &local_err); if (local_err) { error_propagate(errp, local_err); return; diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index f03a80a29b..b777b78e18 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -92,7 +92,7 @@ enum { #define LPC_HC_REGS_OPB_SIZE 0x00001000 -static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset) +static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { const char compat[] = "ibm,power8-lpc\0ibm,lpc"; char *name; @@ -482,7 +482,7 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); - xdc->populate = pnv_lpc_populate; + xdc->dt_xscom = pnv_lpc_dt_xscom; dc->realize = pnv_lpc_realize; } @@ -515,7 +515,7 @@ type_init(pnv_lpc_register_types) */ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) { - PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine()); + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); uint32_t old_state = pnv->cpld_irqstate; PnvLpcController *lpc = PNV_LPC(opaque); diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 9876c26622..5b969127c3 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -510,7 +510,7 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp) } } -static int pnv_psi_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset) +static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; char *name; @@ -546,7 +546,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); - xdc->populate = pnv_psi_populate; + xdc->dt_xscom = pnv_psi_dt_xscom; dc->realize = pnv_psi_realize; dc->props = pnv_psi_properties; diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 38bc85f117..e51d634f40 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -207,15 +207,15 @@ typedef struct ForeachPopulateArgs { int xscom_offset; } ForeachPopulateArgs; -static int xscom_populate_child(Object *child, void *opaque) +static int xscom_dt_child(Object *child, void *opaque) { if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { ForeachPopulateArgs *args = opaque; PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); - if (xc->populate) { - _FDT((xc->populate(xd, args->fdt, args->xscom_offset))); + if (xc->dt_xscom) { + _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); } } return 0; @@ -224,7 +224,7 @@ static int xscom_populate_child(Object *child, void *opaque) static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; -int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) { uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)), cpu_to_be64(PNV_XSCOM_SIZE) }; @@ -255,7 +255,7 @@ int pnv_xscom_populate(PnvChip *chip, void *fdt, int root_offset) args.fdt = fdt; args.xscom_offset = xscom_offset; - object_child_foreach(OBJECT(chip), xscom_populate_child, &args); + object_child_foreach(OBJECT(chip), xscom_dt_child, &args); return 0; } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 59524cd42b..61896f9fd7 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -26,7 +26,7 @@ #include "hw/ppc/pnv_psi.h" #include "hw/ppc/pnv_occ.h" -#define TYPE_PNV_CHIP "powernv-chip" +#define TYPE_PNV_CHIP "pnv-chip" #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) #define PNV_CHIP_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) @@ -117,9 +117,9 @@ typedef struct PnvChipClass { #define PNV_CHIP_INDEX(chip) \ (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) -#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") -#define POWERNV_MACHINE(obj) \ - OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) +#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") +#define PNV_MACHINE(obj) \ + OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) typedef struct PnvMachineState { /*< private >*/ @@ -144,7 +144,7 @@ typedef struct PnvMachineState { /* * BMC helpers */ -void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); +void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); void pnv_bmc_powerdown(IPMIBmc *bmc); /* diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 38077b4796..7252e219e2 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -36,7 +36,7 @@ typedef struct PnvXScomInterface { typedef struct PnvXScomInterfaceClass { InterfaceClass parent; - int (*populate)(PnvXScomInterface *dev, void *fdt, int offset); + int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset); } PnvXScomInterfaceClass; /* @@ -67,7 +67,7 @@ typedef struct PnvXScomInterfaceClass { #define PNV_XSCOM_OCC_SIZE 0x6000 extern void pnv_xscom_realize(PnvChip *chip, Error **errp); -extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); +extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); -- cgit v1.2.3-55-g7522 From 7bac20dc5111963083686743dee00e0ae4fd976b Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 11 Jan 2018 13:25:35 +0000 Subject: imx_fec: Move Tx frame buffer away from the stack Make Tx frame assembly buffer to be a paort of IMXFECState structure to avoid a concern about having large data buffer on the stack. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 22 +++++++++++----------- include/hw/net/imx_fec.h | 3 +++ 2 files changed, 14 insertions(+), 11 deletions(-) (limited to 'include/hw') diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index eb034ffd0c..56cb72273c 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -405,8 +405,7 @@ static void imx_eth_update(IMXFECState *s) static void imx_fec_do_tx(IMXFECState *s) { int frame_size = 0, descnt = 0; - uint8_t frame[ENET_MAX_FRAME_SIZE]; - uint8_t *ptr = frame; + uint8_t *ptr = s->frame; uint32_t addr = s->tx_descriptor; while (descnt++ < IMX_MAX_DESC) { @@ -431,8 +430,8 @@ static void imx_fec_do_tx(IMXFECState *s) frame_size += len; if (bd.flags & ENET_BD_L) { /* Last buffer in frame. */ - qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size); - ptr = frame; + qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size); + ptr = s->frame; frame_size = 0; s->regs[ENET_EIR] |= ENET_INT_TXF; } @@ -456,8 +455,7 @@ static void imx_fec_do_tx(IMXFECState *s) static void imx_enet_do_tx(IMXFECState *s) { int frame_size = 0, descnt = 0; - uint8_t frame[ENET_MAX_FRAME_SIZE]; - uint8_t *ptr = frame; + uint8_t *ptr = s->frame; uint32_t addr = s->tx_descriptor; while (descnt++ < IMX_MAX_DESC) { @@ -482,13 +480,13 @@ static void imx_enet_do_tx(IMXFECState *s) frame_size += len; if (bd.flags & ENET_BD_L) { if (bd.option & ENET_BD_PINS) { - struct ip_header *ip_hd = PKT_GET_IP_HDR(frame); + struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); if (IP_HEADER_VERSION(ip_hd) == 4) { - net_checksum_calculate(frame, frame_size); + net_checksum_calculate(s->frame, frame_size); } } if (bd.option & ENET_BD_IINS) { - struct ip_header *ip_hd = PKT_GET_IP_HDR(frame); + struct ip_header *ip_hd = PKT_GET_IP_HDR(s->frame); /* We compute checksum only for IPv4 frames */ if (IP_HEADER_VERSION(ip_hd) == 4) { uint16_t csum; @@ -498,8 +496,10 @@ static void imx_enet_do_tx(IMXFECState *s) } } /* Last buffer in frame. */ - qemu_send_packet(qemu_get_queue(s->nic), frame, len); - ptr = frame; + + qemu_send_packet(qemu_get_queue(s->nic), s->frame, len); + ptr = s->frame; + frame_size = 0; if (bd.option & ENET_BD_TX_INT) { s->regs[ENET_EIR] |= ENET_INT_TXF; diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 62ad473b05..67993870a2 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -252,6 +252,9 @@ typedef struct IMXFECState { uint32_t phy_int_mask; bool is_fec; + + /* Buffer used to assemble a Tx frame */ + uint8_t frame[ENET_MAX_FRAME_SIZE]; } IMXFECState; #endif -- cgit v1.2.3-55-g7522 From ff9a7feeab59323d70a9377e9196f042b0647d66 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 11 Jan 2018 13:25:36 +0000 Subject: imx_fec: Use ENET_FTRL to determine truncation length Frame truncation length, TRUNC_FL, is determined by the contents of ENET_FTRL register, so convert the code to use it instead of a hardcoded constant. To avoid the case where TRUNC_FL is greater that ENET_MAX_FRAME_SIZE, increase the value of the latter to its theoretical maximum of 16K. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Signed-off-by: Andrey Smirnov Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 4 ++-- include/hw/net/imx_fec.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'include/hw') diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 56cb72273c..50da91bf9e 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1052,8 +1052,8 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, crc_ptr = (uint8_t *) &crc; /* Huge frames are truncted. */ - if (size > ENET_MAX_FRAME_SIZE) { - size = ENET_MAX_FRAME_SIZE; + if (size > s->regs[ENET_FTRL]) { + size = s->regs[ENET_FTRL]; flags |= ENET_BD_TR | ENET_BD_LG; } diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 67993870a2..a390d704a6 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -86,7 +86,6 @@ #define ENET_TCCR3 393 #define ENET_MAX 400 -#define ENET_MAX_FRAME_SIZE 2032 /* EIR and EIMR */ #define ENET_INT_HB (1 << 31) @@ -155,6 +154,8 @@ #define ENET_RCR_NLC (1 << 30) #define ENET_RCR_GRS (1 << 31) +#define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH) + /* TCR */ #define ENET_TCR_GTS (1 << 0) #define ENET_TCR_FDEN (1 << 2) -- cgit v1.2.3-55-g7522 From ebdd8cddb9e657ef75024b4cc9057dd4ce397a55 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 11 Jan 2018 13:25:37 +0000 Subject: imx_fec: Emulate SHIFT16 in ENETx_RACC Needed to support latest Linux kernel driver which relies on that functionality. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Andrey Smirnov Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 23 +++++++++++++++++++++++ include/hw/net/imx_fec.h | 2 ++ 2 files changed, 25 insertions(+) (limited to 'include/hw') diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 6feda18742..825c879a28 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1037,6 +1037,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, uint8_t *crc_ptr; unsigned int buf_len; size_t size = len; + bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16; FEC_PRINTF("len %d\n", (int)size); @@ -1051,6 +1052,10 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, crc = cpu_to_be32(crc32(~0, buf, size)); crc_ptr = (uint8_t *) &crc; + if (shift16) { + size += 2; + } + /* Huge frames are truncted. */ if (size > s->regs[ENET_FTRL]) { size = s->regs[ENET_FTRL]; @@ -1087,6 +1092,24 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf, buf_len += size - 4; } buf_addr = bd.data; + + if (shift16) { + /* + * If SHIFT16 bit of ENETx_RACC register is set we need to + * align the payload to 4-byte boundary. + */ + const uint8_t zeros[2] = { 0 }; + + dma_memory_write(&address_space_memory, buf_addr, + zeros, sizeof(zeros)); + + buf_addr += sizeof(zeros); + buf_len -= sizeof(zeros); + + /* We only do this once per Ethernet frame */ + shift16 = false; + } + dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); buf += buf_len; if (size < 4) { diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index a390d704a6..af0840a0fa 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -170,6 +170,8 @@ #define ENET_TWFR_TFWR_LENGTH (6) #define ENET_TWFR_STRFWD (1 << 8) +#define ENET_RACC_SHIFT16 BIT(7) + /* Buffer Descriptor. */ typedef struct { uint16_t length; -- cgit v1.2.3-55-g7522 From f93f961c40a31228e3f66e66d99a68937aa242c5 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 11 Jan 2018 13:25:37 +0000 Subject: imx_fec: Add support for multiple Tx DMA rings More recent version of the IP block support more than one Tx DMA ring, so add the code implementing that feature. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Andrey Smirnov Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 133 ++++++++++++++++++++++++++++++++++++++++------- include/hw/net/imx_fec.h | 18 ++++++- 2 files changed, 130 insertions(+), 21 deletions(-) (limited to 'include/hw') diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 825c879a28..77d27f763e 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -196,6 +196,31 @@ static const char *imx_eth_reg_name(IMXFECState *s, uint32_t index) } } +/* + * Versions of this device with more than one TX descriptor save the + * 2nd and 3rd descriptors in a subsection, to maintain migration + * compatibility with previous versions of the device that only + * supported a single descriptor. + */ +static bool imx_eth_is_multi_tx_ring(void *opaque) +{ + IMXFECState *s = IMX_FEC(opaque); + + return s->tx_ring_num > 1; +} + +static const VMStateDescription vmstate_imx_eth_txdescs = { + .name = "imx.fec/txdescs", + .version_id = 1, + .minimum_version_id = 1, + .needed = imx_eth_is_multi_tx_ring, + .fields = (VMStateField[]) { + VMSTATE_UINT32(tx_descriptor[1], IMXFECState), + VMSTATE_UINT32(tx_descriptor[2], IMXFECState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_imx_eth = { .name = TYPE_IMX_FEC, .version_id = 2, @@ -203,15 +228,18 @@ static const VMStateDescription vmstate_imx_eth = { .fields = (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX), VMSTATE_UINT32(rx_descriptor, IMXFECState), - VMSTATE_UINT32(tx_descriptor, IMXFECState), - + VMSTATE_UINT32(tx_descriptor[0], IMXFECState), VMSTATE_UINT32(phy_status, IMXFECState), VMSTATE_UINT32(phy_control, IMXFECState), VMSTATE_UINT32(phy_advertise, IMXFECState), VMSTATE_UINT32(phy_int, IMXFECState), VMSTATE_UINT32(phy_int_mask, IMXFECState), VMSTATE_END_OF_LIST() - } + }, + .subsections = (const VMStateDescription * []) { + &vmstate_imx_eth_txdescs, + NULL + }, }; #define PHY_INT_ENERGYON (1 << 7) @@ -406,7 +434,7 @@ static void imx_fec_do_tx(IMXFECState *s) { int frame_size = 0, descnt = 0; uint8_t *ptr = s->frame; - uint32_t addr = s->tx_descriptor; + uint32_t addr = s->tx_descriptor[0]; while (descnt++ < IMX_MAX_DESC) { IMXFECBufDesc bd; @@ -447,16 +475,47 @@ static void imx_fec_do_tx(IMXFECState *s) } } - s->tx_descriptor = addr; + s->tx_descriptor[0] = addr; imx_eth_update(s); } -static void imx_enet_do_tx(IMXFECState *s) +static void imx_enet_do_tx(IMXFECState *s, uint32_t index) { int frame_size = 0, descnt = 0; + uint8_t *ptr = s->frame; - uint32_t addr = s->tx_descriptor; + uint32_t addr, int_txb, int_txf, tdsr; + size_t ring; + + switch (index) { + case ENET_TDAR: + ring = 0; + int_txb = ENET_INT_TXB; + int_txf = ENET_INT_TXF; + tdsr = ENET_TDSR; + break; + case ENET_TDAR1: + ring = 1; + int_txb = ENET_INT_TXB1; + int_txf = ENET_INT_TXF1; + tdsr = ENET_TDSR1; + break; + case ENET_TDAR2: + ring = 2; + int_txb = ENET_INT_TXB2; + int_txf = ENET_INT_TXF2; + tdsr = ENET_TDSR2; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bogus value for index %x\n", + __func__, index); + abort(); + break; + } + + addr = s->tx_descriptor[ring]; while (descnt++ < IMX_MAX_DESC) { IMXENETBufDesc bd; @@ -502,32 +561,32 @@ static void imx_enet_do_tx(IMXFECState *s) frame_size = 0; if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |= ENET_INT_TXF; + s->regs[ENET_EIR] |= int_txf; } } if (bd.option & ENET_BD_TX_INT) { - s->regs[ENET_EIR] |= ENET_INT_TXB; + s->regs[ENET_EIR] |= int_txb; } bd.flags &= ~ENET_BD_R; /* Write back the modified descriptor. */ imx_enet_write_bd(&bd, addr); /* Advance to the next descriptor. */ if ((bd.flags & ENET_BD_W) != 0) { - addr = s->regs[ENET_TDSR]; + addr = s->regs[tdsr]; } else { addr += sizeof(bd); } } - s->tx_descriptor = addr; + s->tx_descriptor[ring] = addr; imx_eth_update(s); } -static void imx_eth_do_tx(IMXFECState *s) +static void imx_eth_do_tx(IMXFECState *s, uint32_t index) { if (!s->is_fec && (s->regs[ENET_ECR] & ENET_ECR_EN1588)) { - imx_enet_do_tx(s); + imx_enet_do_tx(s, index); } else { imx_fec_do_tx(s); } @@ -585,7 +644,7 @@ static void imx_eth_reset(DeviceState *d) } s->rx_descriptor = 0; - s->tx_descriptor = 0; + memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor)); /* We also reset the PHY */ phy_reset(s); @@ -791,6 +850,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { IMXFECState *s = IMX_FEC(opaque); + const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s); uint32_t index = offset >> 2; FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index), @@ -813,10 +873,18 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, s->regs[index] = 0; } break; - case ENET_TDAR: + case ENET_TDAR1: /* FALLTHROUGH */ + case ENET_TDAR2: /* FALLTHROUGH */ + if (unlikely(single_tx_ring)) { + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: trying to access TDAR2 or TDAR1\n", + TYPE_IMX_FEC, __func__); + return; + } + case ENET_TDAR: /* FALLTHROUGH */ if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { s->regs[index] = ENET_TDAR_TDAR; - imx_eth_do_tx(s); + imx_eth_do_tx(s, index); } s->regs[index] = 0; break; @@ -828,8 +896,12 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, if ((s->regs[index] & ENET_ECR_ETHEREN) == 0) { s->regs[ENET_RDAR] = 0; s->rx_descriptor = s->regs[ENET_RDSR]; - s->regs[ENET_TDAR] = 0; - s->tx_descriptor = s->regs[ENET_TDSR]; + s->regs[ENET_TDAR] = 0; + s->regs[ENET_TDAR1] = 0; + s->regs[ENET_TDAR2] = 0; + s->tx_descriptor[0] = s->regs[ENET_TDSR]; + s->tx_descriptor[1] = s->regs[ENET_TDSR1]; + s->tx_descriptor[2] = s->regs[ENET_TDSR2]; } break; case ENET_MMFR: @@ -907,7 +979,29 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, } else { s->regs[index] = value & ~7; } - s->tx_descriptor = s->regs[index]; + s->tx_descriptor[0] = s->regs[index]; + break; + case ENET_TDSR1: + if (unlikely(single_tx_ring)) { + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: trying to access TDSR1\n", + TYPE_IMX_FEC, __func__); + return; + } + + s->regs[index] = value & ~7; + s->tx_descriptor[1] = s->regs[index]; + break; + case ENET_TDSR2: + if (unlikely(single_tx_ring)) { + qemu_log_mask(LOG_GUEST_ERROR, + "[%s]%s: trying to access TDSR2\n", + TYPE_IMX_FEC, __func__); + return; + } + + s->regs[index] = value & ~7; + s->tx_descriptor[2] = s->regs[index]; break; case ENET_MRBR: s->regs[index] = value & 0x00003ff0; @@ -1203,6 +1297,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp) static Property imx_eth_properties[] = { DEFINE_NIC_PROPERTIES(IMXFECState, conf), + DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index af0840a0fa..91ef8f89a6 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -52,6 +52,8 @@ #define ENET_TFWR 81 #define ENET_FRBR 83 #define ENET_FRSR 84 +#define ENET_TDSR1 89 +#define ENET_TDSR2 92 #define ENET_RDSR 96 #define ENET_TDSR 97 #define ENET_MRBR 98 @@ -66,6 +68,8 @@ #define ENET_FTRL 108 #define ENET_TACC 112 #define ENET_RACC 113 +#define ENET_TDAR1 121 +#define ENET_TDAR2 123 #define ENET_MIIGSK_CFGR 192 #define ENET_MIIGSK_ENR 194 #define ENET_ATCR 256 @@ -105,13 +109,18 @@ #define ENET_INT_WAKEUP (1 << 17) #define ENET_INT_TS_AVAIL (1 << 16) #define ENET_INT_TS_TIMER (1 << 15) +#define ENET_INT_TXF2 (1 << 7) +#define ENET_INT_TXB2 (1 << 6) +#define ENET_INT_TXF1 (1 << 3) +#define ENET_INT_TXB1 (1 << 2) #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \ ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \ ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \ ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \ ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \ - ENET_INT_TS_AVAIL) + ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \ + ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2) /* RDAR */ #define ENET_RDAR_RDAR (1 << 24) @@ -234,6 +243,9 @@ typedef struct { #define ENET_BD_BDU (1 << 31) +#define ENET_TX_RING_NUM 3 + + typedef struct IMXFECState { /*< private >*/ SysBusDevice parent_obj; @@ -246,7 +258,9 @@ typedef struct IMXFECState { uint32_t regs[ENET_MAX]; uint32_t rx_descriptor; - uint32_t tx_descriptor; + + uint32_t tx_descriptor[ENET_TX_RING_NUM]; + uint32_t tx_ring_num; uint32_t phy_status; uint32_t phy_control; -- cgit v1.2.3-55-g7522 From 831858ad9da7eccf4c260c60ed56cff0f1666424 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 11 Jan 2018 13:25:38 +0000 Subject: imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file Some i.MX SoCs (e.g. i.MX7) have FEC registers going as far as offset 0x614, so to avoid getting aborts when accessing those on QEMU, extend the register file to cover FSL_IMX25_FEC_SIZE(16K) of address space instead of just 1K. Cc: Peter Maydell Cc: Jason Wang Cc: Philippe Mathieu-Daudé Cc: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Cc: yurovsky@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Andrey Smirnov Signed-off-by: Peter Maydell --- hw/net/imx_fec.c | 2 +- include/hw/arm/fsl-imx25.h | 1 - include/hw/net/imx_fec.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/hw') diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index c1cf7f9c58..4fb48f62ba 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1281,7 +1281,7 @@ static void imx_eth_realize(DeviceState *dev, Error **errp) SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memory_region_init_io(&s->iomem, OBJECT(dev), &imx_eth_ops, s, - TYPE_IMX_FEC, 0x400); + TYPE_IMX_FEC, FSL_IMX25_FEC_SIZE); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq[0]); sysbus_init_irq(sbd, &s->irq[1]); diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index d0e8e9d956..65a73714ef 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -192,7 +192,6 @@ typedef struct FslIMX25State { #define FSL_IMX25_UART5_ADDR 0x5002C000 #define FSL_IMX25_UART5_SIZE 0x4000 #define FSL_IMX25_FEC_ADDR 0x50038000 -#define FSL_IMX25_FEC_SIZE 0x4000 #define FSL_IMX25_CCM_ADDR 0x53F80000 #define FSL_IMX25_CCM_SIZE 0x4000 #define FSL_IMX25_GPT4_ADDR 0x53F84000 diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h index 91ef8f89a6..7b3faa4019 100644 --- a/include/hw/net/imx_fec.h +++ b/include/hw/net/imx_fec.h @@ -245,6 +245,7 @@ typedef struct { #define ENET_TX_RING_NUM 3 +#define FSL_IMX25_FEC_SIZE 0x4000 typedef struct IMXFECState { /*< private >*/ -- cgit v1.2.3-55-g7522