From 6eaf9cf56f0f6e3faf73273f93cfe3e2e9fd0786 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 19 Jul 2020 23:49:08 -0700 Subject: hw/riscv: sifive_u: Add a dummy L2 cache controller device It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_u.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index aba4d0181f..d3c0c00d10 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -71,6 +71,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2CC, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -86,6 +87,9 @@ enum { }; enum { + SIFIVE_U_L2CC_IRQ0 = 1, + SIFIVE_U_L2CC_IRQ1 = 2, + SIFIVE_U_L2CC_IRQ2 = 3, SIFIVE_U_UART0_IRQ = 4, SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GPIO_IRQ0 = 7, -- cgit v1.2.3-55-g7522 From 224914069d49cd186231000070d99ca04ee0550e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Fri, 24 Jul 2020 22:34:43 -0700 Subject: hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines Once an interrupt has been claimed, but before it has been compelted we shouldn't receive any more pending interrupts. This patche keeps track of this to ensure that we don't see any more interrupts until it is completed. Signed-off-by: Alistair Francis Message-Id: <394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com> --- hw/intc/ibex_plic.c | 17 +++++++++++++++++ include/hw/intc/ibex_plic.h | 1 + 2 files changed, 18 insertions(+) (limited to 'include') diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index 578edd2ce0..669247ef08 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -43,6 +43,14 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level) { int pending_num = irq / 32; + if (s->claimed[pending_num] & 1 << (irq % 32)) { + /* + * The interrupt has been claimed, but not compelted. + * The pending bit can't be set. + */ + return; + } + s->pending[pending_num] |= level << (irq % 32); } @@ -120,6 +128,10 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr, int pending_num = s->claim / 32; s->pending[pending_num] &= ~(1 << (s->claim % 32)); + /* Set the interrupt as claimed, but not compelted */ + s->claimed[pending_num] |= 1 << (s->claim % 32); + + /* Return the current claimed interrupt */ ret = s->claim; /* Update the interrupt status after the claim */ @@ -155,6 +167,10 @@ static void ibex_plic_write(void *opaque, hwaddr addr, /* Interrupt was completed */ s->claim = 0; } + if (s->claimed[value / 32] & 1 << (value % 32)) { + /* This value was already claimed, clear it. */ + s->claimed[value / 32] &= ~(1 << (value % 32)); + } } ibex_plic_update(s); @@ -215,6 +231,7 @@ static void ibex_plic_realize(DeviceState *dev, Error **errp) int i; s->pending = g_new0(uint32_t, s->pending_num); + s->claimed = g_new0(uint32_t, s->pending_num); s->source = g_new0(uint32_t, s->source_num); s->priority = g_new0(uint32_t, s->priority_num); s->enable = g_new0(uint32_t, s->enable_num); diff --git a/include/hw/intc/ibex_plic.h b/include/hw/intc/ibex_plic.h index ddc7909903..d8eb09b258 100644 --- a/include/hw/intc/ibex_plic.h +++ b/include/hw/intc/ibex_plic.h @@ -33,6 +33,7 @@ typedef struct IbexPlicState { MemoryRegion mmio; uint32_t *pending; + uint32_t *claimed; uint32_t *source; uint32_t *priority; uint32_t *enable; -- cgit v1.2.3-55-g7522