From 4fe822e075d6befa3714f7066158678e92cedb8b Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Fri, 27 Sep 2013 18:10:18 +1000 Subject: spapr-rtas: fix h_rtas parameters reading On the real hardware, RTAS is called in real mode and therefore top 4 bits of the address passed in the call are ignored. So does the patch. This converts h_rtas() to use existing rtas_ld() handlers. This fixed rtas_ld()/rtas_st() to ignore top 4 bits. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- include/hw/ppc/spapr.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index e37b41983c..6407c8a467 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -332,14 +332,19 @@ static inline int spapr_allocate_lsi(int hint) return spapr_allocate_irq(hint, true); } +static inline uint64_t ppc64_phys_to_real(uint64_t addr) +{ + return addr & ~0xF000000000000000ULL; +} + static inline uint32_t rtas_ld(target_ulong phys, int n) { - return ldl_be_phys(phys + 4*n); + return ldl_be_phys(ppc64_phys_to_real(phys + 4*n)); } static inline void rtas_st(target_ulong phys, int n, uint32_t val) { - stl_be_phys(phys + 4*n, val); + stl_be_phys(ppc64_phys_to_real(phys + 4*n), val); } typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, -- cgit v1.2.3-55-g7522 From d1b5682d88f72f8662ce6d20e07af3adfbf39ed0 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Thu, 26 Sep 2013 16:18:39 +1000 Subject: xics: add pre_save/post_load dispatchers The upcoming support of in-kernel XICS will redefine migration callbacks for both ICS and ICP so classes and callback pointers are added. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/intc/xics.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++--- include/hw/ppc/xics.h | 26 ++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 666888d527..eeb64f588e 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -190,11 +190,35 @@ static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority) } } +static void icp_dispatch_pre_save(void *opaque) +{ + ICPState *ss = opaque; + ICPStateClass *info = ICP_GET_CLASS(ss); + + if (info->pre_save) { + info->pre_save(ss); + } +} + +static int icp_dispatch_post_load(void *opaque, int version_id) +{ + ICPState *ss = opaque; + ICPStateClass *info = ICP_GET_CLASS(ss); + + if (info->post_load) { + return info->post_load(ss, version_id); + } + + return 0; +} + static const VMStateDescription vmstate_icp_server = { .name = "icp/server", .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, + .pre_save = icp_dispatch_pre_save, + .post_load = icp_dispatch_post_load, .fields = (VMStateField []) { /* Sanity check */ VMSTATE_UINT32(xirr, ICPState), @@ -229,6 +253,7 @@ static TypeInfo icp_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(ICPState), .class_init = icp_class_init, + .class_size = sizeof(ICPStateClass), }; /* @@ -390,10 +415,9 @@ static void ics_reset(DeviceState *dev) } } -static int ics_post_load(void *opaque, int version_id) +static int ics_post_load(ICSState *ics, int version_id) { int i; - ICSState *ics = opaque; for (i = 0; i < ics->icp->nr_servers; i++) { icp_resend(ics->icp, i); @@ -402,6 +426,28 @@ static int ics_post_load(void *opaque, int version_id) return 0; } +static void ics_dispatch_pre_save(void *opaque) +{ + ICSState *ics = opaque; + ICSStateClass *info = ICS_GET_CLASS(ics); + + if (info->pre_save) { + info->pre_save(ics); + } +} + +static int ics_dispatch_post_load(void *opaque, int version_id) +{ + ICSState *ics = opaque; + ICSStateClass *info = ICS_GET_CLASS(ics); + + if (info->post_load) { + return info->post_load(ics, version_id); + } + + return 0; +} + static const VMStateDescription vmstate_ics_irq = { .name = "ics/irq", .version_id = 1, @@ -421,7 +467,8 @@ static const VMStateDescription vmstate_ics = { .version_id = 1, .minimum_version_id = 1, .minimum_version_id_old = 1, - .post_load = ics_post_load, + .pre_save = ics_dispatch_pre_save, + .post_load = ics_dispatch_post_load, .fields = (VMStateField []) { /* Sanity check */ VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), @@ -446,10 +493,12 @@ static int ics_realize(DeviceState *dev) static void ics_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ICSStateClass *isc = ICS_CLASS(klass); dc->init = ics_realize; dc->vmsd = &vmstate_ics; dc->reset = ics_reset; + isc->post_load = ics_post_load; } static TypeInfo ics_info = { @@ -457,6 +506,7 @@ static TypeInfo ics_info = { .parent = TYPE_DEVICE, .instance_size = sizeof(ICSState), .class_init = ics_class_init, + .class_size = sizeof(ICSStateClass), }; /* diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 66364c5faf..6e3b605550 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -42,7 +42,9 @@ * that yet) */ typedef struct XICSState XICSState; +typedef struct ICPStateClass ICPStateClass; typedef struct ICPState ICPState; +typedef struct ICSStateClass ICSStateClass; typedef struct ICSState ICSState; typedef struct ICSIRQState ICSIRQState; @@ -59,6 +61,18 @@ struct XICSState { #define TYPE_ICP "icp" #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) +#define ICP_CLASS(klass) \ + OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) +#define ICP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) + +struct ICPStateClass { + DeviceClass parent_class; + + void (*pre_save)(ICPState *s); + int (*post_load)(ICPState *s, int version_id); +}; + struct ICPState { /*< private >*/ DeviceState parent_obj; @@ -72,6 +86,18 @@ struct ICPState { #define TYPE_ICS "ics" #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) +#define ICS_CLASS(klass) \ + OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) +#define ICS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) + +struct ICSStateClass { + DeviceClass parent_class; + + void (*pre_save)(ICSState *s); + int (*post_load)(ICSState *s, int version_id); +}; + struct ICSState { /*< private >*/ DeviceState parent_obj; -- cgit v1.2.3-55-g7522 From 5a3d7b23ba41b4884b43b6bc936ea18f999d5c6b Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Thu, 26 Sep 2013 16:18:42 +1000 Subject: xics: split to xics and xics-common The upcoming XICS-KVM support will use bits of emulated XICS code. So this introduces new level of hierarchy - "xics-common" class. Both emulated XICS and XICS-KVM will inherit from it and override class callbacks when required. The new "xics-common" class implements: 1. replaces static "nr_irqs" and "nr_servers" properties with the dynamic ones and adds callbacks to be executed when properties are set. 2. xics_cpu_setup() callback renamed to xics_common_cpu_setup() as it is a common part for both XICS'es 3. xics_reset() renamed to xics_common_reset() for the same reason. The emulated XICS changes: 1. the part of xics_realize() which creates ICPs is moved to the "nr_servers" property callback as realize() is too late to create/initialize devices and instance_init() is too early to create devices as the number of child devices comes via the "nr_servers" property. 2. added ics_initfn() which does a little part of what xics_realize() did. Signed-off-by: Alexey Kardashevskiy Reviewed-by: Alexander Graf Signed-off-by: Alexander Graf --- hw/intc/xics.c | 156 +++++++++++++++++++++++++++++++++++++++++++------- hw/ppc/spapr.c | 2 +- include/hw/ppc/xics.h | 20 +++++++ 3 files changed, 157 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index c90eb0aa12..5ed2618769 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -30,6 +30,7 @@ #include "hw/ppc/spapr.h" #include "hw/ppc/xics.h" #include "qemu/error-report.h" +#include "qapi/visitor.h" void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) { @@ -55,9 +56,12 @@ void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) } } -static void xics_reset(DeviceState *d) +/* + * XICS Common class - parent for emulated XICS and KVM-XICS + */ +static void xics_common_reset(DeviceState *d) { - XICSState *icp = XICS(d); + XICSState *icp = XICS_COMMON(d); int i; for (i = 0; i < icp->nr_servers; i++) { @@ -67,6 +71,99 @@ static void xics_reset(DeviceState *d) device_reset(DEVICE(icp->ics)); } +static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, + void *opaque, const char *name, Error **errp) +{ + XICSState *icp = XICS_COMMON(obj); + int64_t value = icp->nr_irqs; + + visit_type_int(v, &value, name, errp); +} + +static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, + void *opaque, const char *name, Error **errp) +{ + XICSState *icp = XICS_COMMON(obj); + XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); + Error *error = NULL; + int64_t value; + + visit_type_int(v, &value, name, &error); + if (error) { + error_propagate(errp, error); + return; + } + if (icp->nr_irqs) { + error_setg(errp, "Number of interrupts is already set to %u", + icp->nr_irqs); + return; + } + + assert(info->set_nr_irqs); + assert(icp->ics); + info->set_nr_irqs(icp, value, errp); +} + +static void xics_prop_get_nr_servers(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + XICSState *icp = XICS_COMMON(obj); + int64_t value = icp->nr_servers; + + visit_type_int(v, &value, name, errp); +} + +static void xics_prop_set_nr_servers(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + XICSState *icp = XICS_COMMON(obj); + XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); + Error *error = NULL; + int64_t value; + + visit_type_int(v, &value, name, &error); + if (error) { + error_propagate(errp, error); + return; + } + if (icp->nr_servers) { + error_setg(errp, "Number of servers is already set to %u", + icp->nr_servers); + return; + } + + assert(info->set_nr_servers); + info->set_nr_servers(icp, value, errp); +} + +static void xics_common_initfn(Object *obj) +{ + object_property_add(obj, "nr_irqs", "int", + xics_prop_get_nr_irqs, xics_prop_set_nr_irqs, + NULL, NULL, NULL); + object_property_add(obj, "nr_servers", "int", + xics_prop_get_nr_servers, xics_prop_set_nr_servers, + NULL, NULL, NULL); +} + +static void xics_common_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->reset = xics_common_reset; +} + +static const TypeInfo xics_common_info = { + .name = TYPE_XICS_COMMON, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XICSState), + .class_size = sizeof(XICSStateClass), + .instance_init = xics_common_initfn, + .class_init = xics_common_class_init, +}; + /* * ICP: Presentation layer */ @@ -479,6 +576,13 @@ static const VMStateDescription vmstate_ics = { }, }; +static void ics_initfn(Object *obj) +{ + ICSState *ics = ICS(obj); + + ics->offset = XICS_IRQ_BASE; +} + static void ics_realize(DeviceState *dev, Error **errp) { ICSState *ics = ICS(dev); @@ -509,6 +613,7 @@ static const TypeInfo ics_info = { .instance_size = sizeof(ICSState), .class_init = ics_class_init, .class_size = sizeof(ICSStateClass), + .instance_init = ics_initfn, }; /* @@ -689,10 +794,31 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr, * XICS */ +static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp) +{ + icp->nr_irqs = icp->ics->nr_irqs = nr_irqs; +} + +static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, + Error **errp) +{ + int i; + + icp->nr_servers = nr_servers; + + icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); + for (i = 0; i < icp->nr_servers; i++) { + char buffer[32]; + object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); + snprintf(buffer, sizeof(buffer), "icp[%d]", i); + object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), + errp); + } +} + static void xics_realize(DeviceState *dev, Error **errp) { XICSState *icp = XICS(dev); - ICSState *ics = icp->ics; Error *error = NULL; int i; @@ -712,21 +838,13 @@ static void xics_realize(DeviceState *dev, Error **errp) spapr_register_hypercall(H_XIRR, h_xirr); spapr_register_hypercall(H_EOI, h_eoi); - ics->nr_irqs = icp->nr_irqs; - ics->offset = XICS_IRQ_BASE; - ics->icp = icp; object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); if (error) { error_propagate(errp, error); return; } - icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); for (i = 0; i < icp->nr_servers; i++) { - char buffer[32]; - object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); - snprintf(buffer, sizeof(buffer), "icp[%d]", i); - object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), NULL); object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); if (error) { error_propagate(errp, error); @@ -741,33 +859,31 @@ static void xics_initfn(Object *obj) xics->ics = ICS(object_new(TYPE_ICS)); object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); + xics->ics->icp = xics; } -static Property xics_properties[] = { - DEFINE_PROP_UINT32("nr_servers", XICSState, nr_servers, -1), - DEFINE_PROP_UINT32("nr_irqs", XICSState, nr_irqs, -1), - DEFINE_PROP_END_OF_LIST(), -}; - static void xics_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + XICSStateClass *xsc = XICS_CLASS(oc); dc->realize = xics_realize; - dc->props = xics_properties; - dc->reset = xics_reset; + xsc->set_nr_irqs = xics_set_nr_irqs; + xsc->set_nr_servers = xics_set_nr_servers; } static const TypeInfo xics_info = { .name = TYPE_XICS, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_XICS_COMMON, .instance_size = sizeof(XICSState), + .class_size = sizeof(XICSStateClass), .class_init = xics_class_init, .instance_init = xics_initfn, }; static void xics_register_types(void) { + type_register_static(&xics_common_info); type_register_static(&xics_info); type_register_static(&ics_info); type_register_static(&icp_info); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a276377496..f65dadc356 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -161,7 +161,7 @@ static XICSState *try_create_xics(const char *type, int nr_servers, return NULL; } - return XICS(dev); + return XICS_COMMON(dev); } static XICSState *xics_system_init(int nr_servers, int nr_irqs) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 6e3b605550..7e702a0068 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -29,9 +29,21 @@ #include "hw/sysbus.h" +#define TYPE_XICS_COMMON "xics-common" +#define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON) + #define TYPE_XICS "xics" #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) +#define XICS_COMMON_CLASS(klass) \ + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) +#define XICS_CLASS(klass) \ + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS) +#define XICS_COMMON_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON) +#define XICS_GET_CLASS(obj) \ + OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS) + #define XICS_IPI 0x2 #define XICS_BUID 0x1 #define XICS_IRQ_BASE (XICS_BUID << 12) @@ -41,6 +53,7 @@ * (the kernel implementation supports more but we don't exploit * that yet) */ +typedef struct XICSStateClass XICSStateClass; typedef struct XICSState XICSState; typedef struct ICPStateClass ICPStateClass; typedef struct ICPState ICPState; @@ -48,6 +61,13 @@ typedef struct ICSStateClass ICSStateClass; typedef struct ICSState ICSState; typedef struct ICSIRQState ICSIRQState; +struct XICSStateClass { + DeviceClass parent_class; + + void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp); + void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp); +}; + struct XICSState { /*< private >*/ SysBusDevice parent_obj; -- cgit v1.2.3-55-g7522 From 5eb92ccc3f23f958c0d21bed7c22abe6c1f1adda Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Thu, 26 Sep 2013 16:18:43 +1000 Subject: xics: add cpu_setup callback This adds a cpu_setup callback to the XICS device class (as XICS-KVM will do it different), xics_cpu_setup() will call it if it is set. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/intc/xics.c | 5 +++++ include/hw/ppc/xics.h | 1 + 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 5ed2618769..1c6e6f5454 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -37,9 +37,14 @@ void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; ICPState *ss = &icp->ss[cs->cpu_index]; + XICSStateClass *info = XICS_COMMON_GET_CLASS(icp); assert(cs->cpu_index < icp->nr_servers); + if (info->cpu_setup) { + info->cpu_setup(icp, cpu); + } + switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_POWER7: ss->output = env->irq_inputs[POWER7_INPUT_INT]; diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 7e702a0068..343bba80f8 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -64,6 +64,7 @@ typedef struct ICSIRQState ICSIRQState; struct XICSStateClass { DeviceClass parent_class; + void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu); void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp); void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **errp); }; -- cgit v1.2.3-55-g7522 From 11ad93f68195f68cc94d988f2aa50b4d190ee52a Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 26 Sep 2013 16:18:44 +1000 Subject: xics-kvm: Support for in-kernel XICS interrupt controller Recent (host) kernels support emulating the PAPR defined "XICS" interrupt controller system within KVM. This patch allows qemu to initialize and configure the in-kernel XICS, and keep its state in sync with qemu's XICS state as necessary. This should give considerable performance improvements. e.g. on a simple IPI ping-pong test between hardware threads, using qemu XICS gives us around 5,000 irqs/second, whereas the in-kernel XICS gives us around 70,000 irqs/s on the same hardware configuration. Signed-off-by: David Gibson [Mike Qiu : fixed mistype which caused ics_set_kvm_state() to fail] Signed-off-by: Alexey Kardashevskiy Reviewed-by: Alexander Graf Signed-off-by: Alexander Graf --- default-configs/ppc64-softmmu.mak | 1 + hw/intc/Makefile.objs | 1 + hw/intc/xics_kvm.c | 488 ++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr.c | 21 +- include/hw/ppc/xics.h | 10 + 5 files changed, 520 insertions(+), 1 deletion(-) create mode 100644 hw/intc/xics_kvm.c (limited to 'include') diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak index 975112acf7..fb34a9b074 100644 --- a/default-configs/ppc64-softmmu.mak +++ b/default-configs/ppc64-softmmu.mak @@ -46,6 +46,7 @@ CONFIG_E500=y CONFIG_OPENPIC_KVM=$(and $(CONFIG_E500),$(CONFIG_KVM)) # For pSeries CONFIG_XICS=$(CONFIG_PSERIES) +CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) # For PReP CONFIG_I82378=y CONFIG_I8259=y diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 2851eed25f..47ac44264c 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -23,3 +23,4 @@ obj-$(CONFIG_OMAP) += omap_intc.o obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o obj-$(CONFIG_SH4) += sh_intc.o obj-$(CONFIG_XICS) += xics.o +obj-$(CONFIG_XICS_KVM) += xics_kvm.o diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c new file mode 100644 index 0000000000..a2ccafa2d3 --- /dev/null +++ b/hw/intc/xics_kvm.c @@ -0,0 +1,488 @@ +/* + * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator + * + * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics, in-kernel emulation + * + * Copyright (c) 2013 David Gibson, IBM Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "hw/hw.h" +#include "trace.h" +#include "hw/ppc/spapr.h" +#include "hw/ppc/xics.h" +#include "kvm_ppc.h" +#include "qemu/config-file.h" +#include "qemu/error-report.h" + +#include + +typedef struct KVMXICSState { + XICSState parent_obj; + + uint32_t set_xive_token; + uint32_t get_xive_token; + uint32_t int_off_token; + uint32_t int_on_token; + int kernel_xics_fd; +} KVMXICSState; + +/* + * ICP-KVM + */ +static void icp_get_kvm_state(ICPState *ss) +{ + uint64_t state; + struct kvm_one_reg reg = { + .id = KVM_REG_PPC_ICP_STATE, + .addr = (uintptr_t)&state, + }; + int ret; + + /* ICP for this CPU thread is not in use, exiting */ + if (!ss->cs) { + return; + } + + ret = kvm_vcpu_ioctl(ss->cs, KVM_GET_ONE_REG, ®); + if (ret != 0) { + error_report("Unable to retrieve KVM interrupt controller state" + " for CPU %d: %s", ss->cs->cpu_index, strerror(errno)); + exit(1); + } + + ss->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT; + ss->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT) + & KVM_REG_PPC_ICP_MFRR_MASK; + ss->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT) + & KVM_REG_PPC_ICP_PPRI_MASK; +} + +static int icp_set_kvm_state(ICPState *ss, int version_id) +{ + uint64_t state; + struct kvm_one_reg reg = { + .id = KVM_REG_PPC_ICP_STATE, + .addr = (uintptr_t)&state, + }; + int ret; + + /* ICP for this CPU thread is not in use, exiting */ + if (!ss->cs) { + return 0; + } + + state = ((uint64_t)ss->xirr << KVM_REG_PPC_ICP_XISR_SHIFT) + | ((uint64_t)ss->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT) + | ((uint64_t)ss->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT); + + ret = kvm_vcpu_ioctl(ss->cs, KVM_SET_ONE_REG, ®); + if (ret != 0) { + error_report("Unable to restore KVM interrupt controller state (0x%" + PRIx64 ") for CPU %d: %s", state, ss->cs->cpu_index, + strerror(errno)); + return ret; + } + + return 0; +} + +static void icp_kvm_reset(DeviceState *dev) +{ + ICPState *icp = ICP(dev); + + icp->xirr = 0; + icp->pending_priority = 0xff; + icp->mfrr = 0xff; + + /* Make all outputs are deasserted */ + qemu_set_irq(icp->output, 0); + + icp_set_kvm_state(icp, 1); +} + +static void icp_kvm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ICPStateClass *icpc = ICP_CLASS(klass); + + dc->reset = icp_kvm_reset; + icpc->pre_save = icp_get_kvm_state; + icpc->post_load = icp_set_kvm_state; +} + +static const TypeInfo icp_kvm_info = { + .name = TYPE_KVM_ICP, + .parent = TYPE_ICP, + .instance_size = sizeof(ICPState), + .class_init = icp_kvm_class_init, + .class_size = sizeof(ICPStateClass), +}; + +/* + * ICS-KVM + */ +static void ics_get_kvm_state(ICSState *ics) +{ + KVMXICSState *icpkvm = KVM_XICS(ics->icp); + uint64_t state; + struct kvm_device_attr attr = { + .flags = 0, + .group = KVM_DEV_XICS_GRP_SOURCES, + .addr = (uint64_t)(uintptr_t)&state, + }; + int i; + + for (i = 0; i < ics->nr_irqs; i++) { + ICSIRQState *irq = &ics->irqs[i]; + int ret; + + attr.attr = i + ics->offset; + + ret = ioctl(icpkvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr); + if (ret != 0) { + error_report("Unable to retrieve KVM interrupt controller state" + " for IRQ %d: %s", i + ics->offset, strerror(errno)); + exit(1); + } + + irq->server = state & KVM_XICS_DESTINATION_MASK; + irq->saved_priority = (state >> KVM_XICS_PRIORITY_SHIFT) + & KVM_XICS_PRIORITY_MASK; + /* + * To be consistent with the software emulation in xics.c, we + * split out the masked state + priority that we get from the + * kernel into 'current priority' (0xff if masked) and + * 'saved priority' (if masked, this is the priority the + * interrupt had before it was masked). Masking and unmasking + * are done with the ibm,int-off and ibm,int-on RTAS calls. + */ + if (state & KVM_XICS_MASKED) { + irq->priority = 0xff; + } else { + irq->priority = irq->saved_priority; + } + + if (state & KVM_XICS_PENDING) { + if (state & KVM_XICS_LEVEL_SENSITIVE) { + irq->status |= XICS_STATUS_ASSERTED; + } else { + /* + * A pending edge-triggered interrupt (or MSI) + * must have been rejected previously when we + * first detected it and tried to deliver it, + * so mark it as pending and previously rejected + * for consistency with how xics.c works. + */ + irq->status |= XICS_STATUS_MASKED_PENDING + | XICS_STATUS_REJECTED; + } + } + } +} + +static int ics_set_kvm_state(ICSState *ics, int version_id) +{ + KVMXICSState *icpkvm = KVM_XICS(ics->icp); + uint64_t state; + struct kvm_device_attr attr = { + .flags = 0, + .group = KVM_DEV_XICS_GRP_SOURCES, + .addr = (uint64_t)(uintptr_t)&state, + }; + int i; + + for (i = 0; i < ics->nr_irqs; i++) { + ICSIRQState *irq = &ics->irqs[i]; + int ret; + + attr.attr = i + ics->offset; + + state = irq->server; + state |= (uint64_t)(irq->saved_priority & KVM_XICS_PRIORITY_MASK) + << KVM_XICS_PRIORITY_SHIFT; + if (irq->priority != irq->saved_priority) { + assert(irq->priority == 0xff); + state |= KVM_XICS_MASKED; + } + + if (ics->islsi[i]) { + state |= KVM_XICS_LEVEL_SENSITIVE; + if (irq->status & XICS_STATUS_ASSERTED) { + state |= KVM_XICS_PENDING; + } + } else { + if (irq->status & XICS_STATUS_MASKED_PENDING) { + state |= KVM_XICS_PENDING; + } + } + + ret = ioctl(icpkvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr); + if (ret != 0) { + error_report("Unable to restore KVM interrupt controller state" + " for IRQs %d: %s", i + ics->offset, strerror(errno)); + return ret; + } + } + + return 0; +} + +static void ics_kvm_set_irq(void *opaque, int srcno, int val) +{ + ICSState *ics = opaque; + struct kvm_irq_level args; + int rc; + + args.irq = srcno + ics->offset; + if (!ics->islsi[srcno]) { + if (!val) { + return; + } + args.level = KVM_INTERRUPT_SET; + } else { + args.level = val ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; + } + rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args); + if (rc < 0) { + perror("kvm_irq_line"); + } +} + +static void ics_kvm_reset(DeviceState *dev) +{ + ics_set_kvm_state(ICS(dev), 1); +} + +static void ics_kvm_realize(DeviceState *dev, Error **errp) +{ + ICSState *ics = ICS(dev); + + if (!ics->nr_irqs) { + error_setg(errp, "Number of interrupts needs to be greater 0"); + return; + } + ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState)); + ics->islsi = g_malloc0(ics->nr_irqs * sizeof(bool)); + ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs); +} + +static void ics_kvm_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ICSStateClass *icsc = ICS_CLASS(klass); + + dc->realize = ics_kvm_realize; + dc->reset = ics_kvm_reset; + icsc->pre_save = ics_get_kvm_state; + icsc->post_load = ics_set_kvm_state; +} + +static const TypeInfo ics_kvm_info = { + .name = TYPE_KVM_ICS, + .parent = TYPE_ICS, + .instance_size = sizeof(ICSState), + .class_init = ics_kvm_class_init, +}; + +/* + * XICS-KVM + */ +static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu) +{ + CPUState *cs; + ICPState *ss; + KVMXICSState *icpkvm = KVM_XICS(icp); + + cs = CPU(cpu); + ss = &icp->ss[cs->cpu_index]; + + assert(cs->cpu_index < icp->nr_servers); + if (icpkvm->kernel_xics_fd == -1) { + abort(); + } + + if (icpkvm->kernel_xics_fd != -1) { + int ret; + struct kvm_enable_cap xics_enable_cap = { + .cap = KVM_CAP_IRQ_XICS, + .flags = 0, + .args = {icpkvm->kernel_xics_fd, cs->cpu_index, 0, 0}, + }; + + ss->cs = cs; + + ret = kvm_vcpu_ioctl(ss->cs, KVM_ENABLE_CAP, &xics_enable_cap); + if (ret < 0) { + error_report("Unable to connect CPU%d to kernel XICS: %s", + cs->cpu_index, strerror(errno)); + exit(1); + } + } +} + +static void xics_kvm_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp) +{ + icp->nr_irqs = icp->ics->nr_irqs = nr_irqs; +} + +static void xics_kvm_set_nr_servers(XICSState *icp, uint32_t nr_servers, + Error **errp) +{ + int i; + + icp->nr_servers = nr_servers; + + icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState)); + for (i = 0; i < icp->nr_servers; i++) { + char buffer[32]; + object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_KVM_ICP); + snprintf(buffer, sizeof(buffer), "icp[%d]", i); + object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]), + errp); + } +} + +static void rtas_dummy(PowerPCCPU *cpu, sPAPREnvironment *spapr, + uint32_t token, + uint32_t nargs, target_ulong args, + uint32_t nret, target_ulong rets) +{ + error_report("pseries: %s must never be called for in-kernel XICS", + __func__); +} + +static void xics_kvm_realize(DeviceState *dev, Error **errp) +{ + KVMXICSState *icpkvm = KVM_XICS(dev); + XICSState *icp = XICS_COMMON(dev); + int i, rc; + Error *error = NULL; + struct kvm_create_device xics_create_device = { + .type = KVM_DEV_TYPE_XICS, + .flags = 0, + }; + + if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_IRQ_XICS)) { + error_setg(errp, + "KVM and IRQ_XICS capability must be present for in-kernel XICS"); + goto fail; + } + + icpkvm->set_xive_token = spapr_rtas_register("ibm,set-xive", rtas_dummy); + icpkvm->get_xive_token = spapr_rtas_register("ibm,get-xive", rtas_dummy); + icpkvm->int_off_token = spapr_rtas_register("ibm,int-off", rtas_dummy); + icpkvm->int_on_token = spapr_rtas_register("ibm,int-on", rtas_dummy); + + rc = kvmppc_define_rtas_kernel_token(icpkvm->set_xive_token, + "ibm,set-xive"); + if (rc < 0) { + error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,set-xive"); + goto fail; + } + + rc = kvmppc_define_rtas_kernel_token(icpkvm->get_xive_token, + "ibm,get-xive"); + if (rc < 0) { + error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,get-xive"); + goto fail; + } + + rc = kvmppc_define_rtas_kernel_token(icpkvm->int_on_token, "ibm,int-on"); + if (rc < 0) { + error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-on"); + goto fail; + } + + rc = kvmppc_define_rtas_kernel_token(icpkvm->int_off_token, "ibm,int-off"); + if (rc < 0) { + error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-off"); + goto fail; + } + + /* Create the kernel ICP */ + rc = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &xics_create_device); + if (rc < 0) { + error_setg_errno(errp, -rc, "Error on KVM_CREATE_DEVICE for XICS"); + goto fail; + } + + icpkvm->kernel_xics_fd = xics_create_device.fd; + + object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); + if (error) { + error_propagate(errp, error); + goto fail; + } + + assert(icp->nr_servers); + for (i = 0; i < icp->nr_servers; i++) { + object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error); + if (error) { + error_propagate(errp, error); + goto fail; + } + } + return; + +fail: + kvmppc_define_rtas_kernel_token(0, "ibm,set-xive"); + kvmppc_define_rtas_kernel_token(0, "ibm,get-xive"); + kvmppc_define_rtas_kernel_token(0, "ibm,int-on"); + kvmppc_define_rtas_kernel_token(0, "ibm,int-off"); +} + +static void xics_kvm_initfn(Object *obj) +{ + XICSState *xics = XICS_COMMON(obj); + + xics->ics = ICS(object_new(TYPE_KVM_ICS)); + object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); + xics->ics->icp = xics; +} + +static void xics_kvm_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + XICSStateClass *xsc = XICS_COMMON_CLASS(oc); + + dc->realize = xics_kvm_realize; + xsc->cpu_setup = xics_kvm_cpu_setup; + xsc->set_nr_irqs = xics_kvm_set_nr_irqs; + xsc->set_nr_servers = xics_kvm_set_nr_servers; +} + +static const TypeInfo xics_kvm_info = { + .name = TYPE_KVM_XICS, + .parent = TYPE_XICS_COMMON, + .instance_size = sizeof(KVMXICSState), + .class_init = xics_kvm_class_init, + .instance_init = xics_kvm_initfn, +}; + +static void xics_kvm_register_types(void) +{ + type_register_static(&xics_kvm_info); + type_register_static(&ics_kvm_info); + type_register_static(&icp_kvm_info); +} + +type_init(xics_kvm_register_types) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f65dadc356..c0613e467c 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -168,7 +168,26 @@ static XICSState *xics_system_init(int nr_servers, int nr_irqs) { XICSState *icp = NULL; - icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); + if (kvm_enabled()) { + QemuOpts *machine_opts = qemu_get_machine_opts(); + bool irqchip_allowed = qemu_opt_get_bool(machine_opts, + "kernel_irqchip", true); + bool irqchip_required = qemu_opt_get_bool(machine_opts, + "kernel_irqchip", false); + if (irqchip_allowed) { + icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); + } + + if (irqchip_required && !icp) { + perror("Failed to create in-kernel XICS\n"); + abort(); + } + } + + if (!icp) { + icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); + } + if (!icp) { perror("Failed to create XICS\n"); abort(); diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 343bba80f8..0d7673de94 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -35,6 +35,9 @@ #define TYPE_XICS "xics" #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) +#define TYPE_KVM_XICS "xics-kvm" +#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS) + #define XICS_COMMON_CLASS(klass) \ OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) #define XICS_CLASS(klass) \ @@ -82,6 +85,9 @@ struct XICSState { #define TYPE_ICP "icp" #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) +#define TYPE_KVM_ICP "icp-kvm" +#define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) + #define ICP_CLASS(klass) \ OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) #define ICP_GET_CLASS(obj) \ @@ -98,6 +104,7 @@ struct ICPState { /*< private >*/ DeviceState parent_obj; /*< public >*/ + CPUState *cs; uint32_t xirr; uint8_t pending_priority; uint8_t mfrr; @@ -107,6 +114,9 @@ struct ICPState { #define TYPE_ICS "ics" #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) +#define TYPE_KVM_ICS "icskvm" +#define KVM_ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_KVM_ICS) + #define ICS_CLASS(klass) \ OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) #define ICS_GET_CLASS(obj) \ -- cgit v1.2.3-55-g7522 From 5d87e4b74a0100fbb7970edaa3449eb04b06f782 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 26 Sep 2013 16:18:46 +1000 Subject: xics: Implement H_XIRR_X This implements H_XIRR_X hypercall in addition to H_XIRR as it is mandatory for PAPR+ and there is no way for the guest to detect whether it is supported or not so just add it. As the Partition Adjunct Option is not supported at the moment, the CPPR parameter of the hypercall is ignored. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- hw/intc/xics.c | 14 ++++++++++++++ include/hw/ppc/spapr.h | 1 + 2 files changed, 15 insertions(+) (limited to 'include') diff --git a/hw/intc/xics.c b/hw/intc/xics.c index eb932762b3..a333305d3d 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -27,6 +27,7 @@ #include "hw/hw.h" #include "trace.h" +#include "qemu/timer.h" #include "hw/ppc/spapr.h" #include "hw/ppc/xics.h" #include "qemu/error-report.h" @@ -679,6 +680,18 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr, return H_SUCCESS; } +static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPREnvironment *spapr, + target_ulong opcode, target_ulong *args) +{ + CPUState *cs = CPU(cpu); + ICPState *ss = &spapr->icp->ss[cs->cpu_index]; + uint32_t xirr = icp_accept(ss); + + args[0] = xirr; + args[1] = cpu_get_real_ticks(); + return H_SUCCESS; +} + static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { @@ -853,6 +866,7 @@ static void xics_realize(DeviceState *dev, Error **errp) spapr_register_hypercall(H_CPPR, h_cppr); spapr_register_hypercall(H_IPI, h_ipi); spapr_register_hypercall(H_XIRR, h_xirr); + spapr_register_hypercall(H_XIRR_X, h_xirr_x); spapr_register_hypercall(H_EOI, h_eoi); spapr_register_hypercall(H_IPOLL, h_ipoll); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 6407c8a467..5ae0b58ed9 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -283,6 +283,7 @@ typedef struct sPAPREnvironment { #define H_GET_EM_PARMS 0x2B8 #define H_SET_MPP 0x2D0 #define H_GET_MPP 0x2D4 +#define H_XIRR_X 0x2FC #define H_SET_MODE 0x31C #define MAX_HCALL_OPCODE H_SET_MODE -- cgit v1.2.3-55-g7522 From e62fbc54d459d4cc8e91dc0938383a7f4c13768c Mon Sep 17 00:00:00 2001 From: Aneesh Kumar K.V Date: Tue, 1 Oct 2013 21:49:33 +0530 Subject: target-ppc: dump-guest-memory support This patch add support for dumping guest memory using dump-guest-memory monitor command. Before patch: (qemu) dump-guest-memory testcrash this feature or command is not currently supported (qemu) After patch: (qemu) dump-guest-memory testcrash (qemu) crash was able to read the file crash> bt PID: 0 TASK: c000000000c0d0d0 CPU: 0 COMMAND: "swapper/0" R0: 0000000028000084 R1: c000000000cafa50 R2: c000000000cb05b0 R3: 0000000000000000 R4: c000000000bc4cb0 R5: 0000000000000000 R6: 001efe93b8000000 R7: 0000000000000000 R8: 0000000000000000 R9: b000000000001032 R10: 0000000000000001 R11: 0001eb2117e00d55 .... ... NOTE: Currently crash tools doesn't look at ELF notes in the dump on ppc64. Signed-off-by: Aneesh Kumar K.V Signed-off-by: Alexander Graf --- include/elf.h | 3 + target-ppc/Makefile.objs | 2 +- target-ppc/arch_dump.c | 253 ++++++++++++++++++++++++++++++++++++++++++++ target-ppc/cpu-qom.h | 5 +- target-ppc/translate_init.c | 4 + 5 files changed, 265 insertions(+), 2 deletions(-) create mode 100644 target-ppc/arch_dump.c (limited to 'include') diff --git a/include/elf.h b/include/elf.h index 58bfbf8817..b818091c7b 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1359,6 +1359,9 @@ typedef struct elf64_shdr { #define NT_S390_TODPREG 0x303 /* s390 TOD programmable register */ #define NT_S390_TODCMP 0x302 /* s390 TOD clock comparator register */ #define NT_S390_TIMER 0x301 /* s390 timer register */ +#define NT_PPC_VMX 0x100 /* PowerPC Altivec/VMX registers */ +#define NT_PPC_SPE 0x101 /* PowerPC SPE/EVR registers */ +#define NT_PPC_VSX 0x102 /* PowerPC VSX registers */ /* Note header in a PT_NOTE section */ diff --git a/target-ppc/Makefile.objs b/target-ppc/Makefile.objs index 94d6d0c43b..3cb23e0f11 100644 --- a/target-ppc/Makefile.objs +++ b/target-ppc/Makefile.objs @@ -2,7 +2,7 @@ obj-y += cpu-models.o obj-y += translate.o ifeq ($(CONFIG_SOFTMMU),y) obj-y += machine.o mmu_helper.o mmu-hash32.o -obj-$(TARGET_PPC64) += mmu-hash64.o +obj-$(TARGET_PPC64) += mmu-hash64.o arch_dump.o endif obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o diff --git a/target-ppc/arch_dump.c b/target-ppc/arch_dump.c new file mode 100644 index 0000000000..17fd4c6fb1 --- /dev/null +++ b/target-ppc/arch_dump.c @@ -0,0 +1,253 @@ +/* + * writing ELF notes for ppc64 arch + * + * + * Copyright IBM, Corp. 2013 + * + * Authors: + * Aneesh Kumar K.V + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + */ + +#include "cpu.h" +#include "elf.h" +#include "exec/cpu-all.h" +#include "sysemu/dump.h" +#include "sysemu/kvm.h" + +struct PPC64UserRegStruct { + uint64_t gpr[32]; + uint64_t nip; + uint64_t msr; + uint64_t orig_gpr3; + uint64_t ctr; + uint64_t link; + uint64_t xer; + uint64_t ccr; + uint64_t softe; + uint64_t trap; + uint64_t dar; + uint64_t dsisr; + uint64_t result; +} QEMU_PACKED; + +struct PPC64ElfPrstatus { + char pad1[112]; + struct PPC64UserRegStruct pr_reg; + uint64_t pad2[4]; +} QEMU_PACKED; + + +struct PPC64ElfFpregset { + uint64_t fpr[32]; + uint64_t fpscr; +} QEMU_PACKED; + + +struct PPC64ElfVmxregset { + ppc_avr_t avr[32]; + ppc_avr_t vscr; + union { + ppc_avr_t unused; + uint32_t value; + } vrsave; +} QEMU_PACKED; + +struct PPC64ElfVsxregset { + uint64_t vsr[32]; +} QEMU_PACKED; + +struct PPC64ElfSperegset { + uint32_t evr[32]; + uint64_t spe_acc; + uint32_t spe_fscr; +} QEMU_PACKED; + +typedef struct noteStruct { + Elf64_Nhdr hdr; + char name[5]; + char pad3[3]; + union { + struct PPC64ElfPrstatus prstatus; + struct PPC64ElfFpregset fpregset; + struct PPC64ElfVmxregset vmxregset; + struct PPC64ElfVsxregset vsxregset; + struct PPC64ElfSperegset speregset; + } contents; +} QEMU_PACKED Note; + + +static void ppc64_write_elf64_prstatus(Note *note, PowerPCCPU *cpu) +{ + int i; + uint64_t cr; + struct PPC64ElfPrstatus *prstatus; + struct PPC64UserRegStruct *reg; + + note->hdr.n_type = cpu_to_be32(NT_PRSTATUS); + + prstatus = ¬e->contents.prstatus; + memset(prstatus, 0, sizeof(*prstatus)); + reg = &prstatus->pr_reg; + + for (i = 0; i < 32; i++) { + reg->gpr[i] = cpu_to_be64(cpu->env.gpr[i]); + } + reg->nip = cpu_to_be64(cpu->env.nip); + reg->msr = cpu_to_be64(cpu->env.msr); + reg->ctr = cpu_to_be64(cpu->env.ctr); + reg->link = cpu_to_be64(cpu->env.lr); + reg->xer = cpu_to_be64(cpu_read_xer(&cpu->env)); + + cr = 0; + for (i = 0; i < 8; i++) { + cr |= (cpu->env.crf[i] & 15) << (4 * (7 - i)); + } + reg->ccr = cpu_to_be64(cr); +} + +static void ppc64_write_elf64_fpregset(Note *note, PowerPCCPU *cpu) +{ + int i; + struct PPC64ElfFpregset *fpregset; + + note->hdr.n_type = cpu_to_be32(NT_PRFPREG); + + fpregset = ¬e->contents.fpregset; + memset(fpregset, 0, sizeof(*fpregset)); + + for (i = 0; i < 32; i++) { + fpregset->fpr[i] = cpu_to_be64(cpu->env.fpr[i]); + } + fpregset->fpscr = cpu_to_be64(cpu->env.fpscr); +} + +static void ppc64_write_elf64_vmxregset(Note *note, PowerPCCPU *cpu) +{ + int i; + struct PPC64ElfVmxregset *vmxregset; + + note->hdr.n_type = cpu_to_be32(NT_PPC_VMX); + vmxregset = ¬e->contents.vmxregset; + memset(vmxregset, 0, sizeof(*vmxregset)); + + for (i = 0; i < 32; i++) { + vmxregset->avr[i].u64[0] = cpu_to_be64(cpu->env.avr[i].u64[0]); + vmxregset->avr[i].u64[1] = cpu_to_be64(cpu->env.avr[i].u64[1]); + } + vmxregset->vscr.u32[3] = cpu_to_be32(cpu->env.vscr); +} +static void ppc64_write_elf64_vsxregset(Note *note, PowerPCCPU *cpu) +{ + int i; + struct PPC64ElfVsxregset *vsxregset; + + note->hdr.n_type = cpu_to_be32(NT_PPC_VSX); + vsxregset = ¬e->contents.vsxregset; + memset(vsxregset, 0, sizeof(*vsxregset)); + + for (i = 0; i < 32; i++) { + vsxregset->vsr[i] = cpu_to_be64(cpu->env.vsr[i]); + } +} +static void ppc64_write_elf64_speregset(Note *note, PowerPCCPU *cpu) +{ + struct PPC64ElfSperegset *speregset; + note->hdr.n_type = cpu_to_be32(NT_PPC_SPE); + speregset = ¬e->contents.speregset; + memset(speregset, 0, sizeof(*speregset)); + + speregset->spe_acc = cpu_to_be64(cpu->env.spe_acc); + speregset->spe_fscr = cpu_to_be32(cpu->env.spe_fscr); +} + +struct NoteFuncDescStruct { + int contents_size; + void (*note_contents_func)(Note *note, PowerPCCPU *cpu); +} note_func[] = { + {sizeof(((Note *)0)->contents.prstatus), ppc64_write_elf64_prstatus}, + {sizeof(((Note *)0)->contents.fpregset), ppc64_write_elf64_fpregset}, + {sizeof(((Note *)0)->contents.vmxregset), ppc64_write_elf64_vmxregset}, + {sizeof(((Note *)0)->contents.vsxregset), ppc64_write_elf64_vsxregset}, + {sizeof(((Note *)0)->contents.speregset), ppc64_write_elf64_speregset}, + { 0, NULL} +}; + +typedef struct NoteFuncDescStruct NoteFuncDesc; + +int cpu_get_dump_info(ArchDumpInfo *info, + const struct GuestPhysBlockList *guest_phys_blocks) +{ + /* + * Currently only handling PPC64 big endian. + */ + info->d_machine = EM_PPC64; + info->d_endian = ELFDATA2MSB; + info->d_class = ELFCLASS64; + + return 0; +} + +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) +{ + int name_size = 8; /* "CORE" or "QEMU" rounded */ + size_t elf_note_size = 0; + int note_head_size; + NoteFuncDesc *nf; + + if (class != ELFCLASS64) { + return -1; + } + assert(machine == EM_PPC64); + + note_head_size = sizeof(Elf64_Nhdr); + + for (nf = note_func; nf->note_contents_func; nf++) { + elf_note_size = elf_note_size + note_head_size + name_size + + nf->contents_size; + } + + return (elf_note_size) * nr_cpus; +} + +static int ppc64_write_all_elf64_notes(const char *note_name, + WriteCoreDumpFunction f, + PowerPCCPU *cpu, int id, + void *opaque) +{ + Note note; + int ret = -1; + int note_size; + NoteFuncDesc *nf; + + for (nf = note_func; nf->note_contents_func; nf++) { + note.hdr.n_namesz = cpu_to_be32(sizeof(note.name)); + note.hdr.n_descsz = cpu_to_be32(nf->contents_size); + strncpy(note.name, note_name, sizeof(note.name)); + + (*nf->note_contents_func)(¬e, cpu); + + note_size = sizeof(note) - sizeof(note.contents) + nf->contents_size; + ret = f(¬e, note_size, opaque); + if (ret < 0) { + return -1; + } + } + return 0; +} + +int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + return ppc64_write_all_elf64_notes("CORE", f, cpu, cpuid, opaque); +} + +int ppc64_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, + CPUState *cpu, void *opaque) +{ + return 0; +} diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index f3c710a9e5..827e5dd0e1 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -108,7 +108,10 @@ void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); - +int ppc64_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, + CPUState *cpu, void *opaque); +int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, + int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY extern const struct VMStateDescription vmstate_ppc_cpu; #endif diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 807dab3bd9..f778eaa95d 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8572,6 +8572,10 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; +#if defined(TARGET_PPC64) + cc->write_elf64_note = ppc64_cpu_write_elf64_note; + cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote; +#endif #endif cc->gdb_num_core_regs = 71; -- cgit v1.2.3-55-g7522 From 3bbf37f2692652cc9d48030a9e7f34e2207429f6 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 15 Oct 2013 18:33:37 +0200 Subject: spapr: Use DeviceClass::fw_name for device tree CPU node Instead of relying on cpu_model, obtain the device tree node label per CPU. Use DeviceClass::fw_name as source. Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN". As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name, obsoleting sPAPREnvironment::cpu_model, and spapr_create_fdt_skel() can drop its cpu_model argument. Signed-off-by: Prerna Saxena Signed-off-by: Andreas Färber Signed-off-by: Alexander Graf --- hw/ppc/spapr.c | 26 ++++++-------------------- include/hw/ppc/spapr.h | 1 - target-ppc/translate_init.c | 2 ++ 3 files changed, 8 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c0613e467c..f76b355150 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -204,9 +204,8 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) int smt = kvmppc_smt_threads(); uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; - assert(spapr->cpu_model); - CPU_FOREACH(cpu) { + DeviceClass *dc = DEVICE_GET_CLASS(cpu); uint32_t associativity[] = {cpu_to_be32(0x5), cpu_to_be32(0x0), cpu_to_be32(0x0), @@ -218,7 +217,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) continue; } - snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model, + snprintf(cpu_model, 32, "/cpus/%s@%x", dc->fw_name, cpu->cpu_index); offset = fdt_path_offset(fdt, cpu_model); @@ -288,8 +287,7 @@ static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, } while (0) -static void *spapr_create_fdt_skel(const char *cpu_model, - hwaddr initrd_base, +static void *spapr_create_fdt_skel(hwaddr initrd_base, hwaddr initrd_size, hwaddr kernel_size, bool little_endian, @@ -306,7 +304,6 @@ static void *spapr_create_fdt_skel(const char *cpu_model, char qemu_hypertas_prop[] = "hcall-memop1"; uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; - char *modelname; int i, smt = kvmppc_smt_threads(); unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; @@ -365,18 +362,10 @@ static void *spapr_create_fdt_skel(const char *cpu_model, _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); - modelname = g_strdup(cpu_model); - - for (i = 0; i < strlen(modelname); i++) { - modelname[i] = toupper(modelname[i]); - } - - /* This is needed during FDT finalization */ - spapr->cpu_model = g_strdup(modelname); - CPU_FOREACH(cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; + DeviceClass *dc = DEVICE_GET_CLASS(cs); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); int index = cs->cpu_index; uint32_t servers_prop[smp_threads]; @@ -393,7 +382,7 @@ static void *spapr_create_fdt_skel(const char *cpu_model, continue; } - nodename = g_strdup_printf("%s@%x", modelname, index); + nodename = g_strdup_printf("%s@%x", dc->fw_name, index); _FDT((fdt_begin_node(fdt, nodename))); @@ -477,8 +466,6 @@ static void *spapr_create_fdt_skel(const char *cpu_model, _FDT((fdt_end_node(fdt))); } - g_free(modelname); - _FDT((fdt_end_node(fdt))); /* RTAS */ @@ -1363,8 +1350,7 @@ static void ppc_spapr_init(QEMUMachineInitArgs *args) &savevm_htab_handlers, spapr); /* Prepare the device tree */ - spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, - initrd_base, initrd_size, + spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, kernel_size, kernel_le, boot_device, kernel_cmdline, spapr->epow_irq); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 5ae0b58ed9..fdaab2de52 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -29,7 +29,6 @@ typedef struct sPAPREnvironment { target_ulong entry_point; uint32_t next_irq; uint64_t rtc_offset; - char *cpu_model; bool has_graphics; uint32_t epow_irq; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 9e29caaab2..47825ac543 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8587,6 +8587,8 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #else cc->gdb_core_xml_file = "power-core.xml"; #endif + + dc->fw_name = "PowerPC,UNKNOWN"; } static const TypeInfo ppc_cpu_type_info = { -- cgit v1.2.3-55-g7522