From 333b9c8a684c58f6711521e446e4b26de5addadc Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Mon, 16 Jul 2018 17:18:41 +0100 Subject: aspeed: Implement write-1-{set, clear} for AST2500 strapping The AST2500 SoC family changes the runtime behaviour of the hardware strapping register (SCU70) to write-1-set/write-1-clear, with write-1-clear implemented on the "read-only" SoC revision register (SCU7C). For the the AST2400, the hardware strapping is runtime-configured with read-modify-write semantics. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Message-id: 20180709143524.17480-1-andrew@aj.id.au Signed-off-by: Peter Maydell --- include/hw/misc/aspeed_scu.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index f662c38188..38996adc59 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -41,6 +41,8 @@ typedef struct AspeedSCUState { #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U +#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) + extern bool is_supported_silicon_rev(uint32_t silicon_rev); #define ASPEED_SCU_PROT_KEY 0x1688A8A8 -- cgit v1.2.3-55-g7522