From 45fefe7c4d9bfc5a4a222d3d2c8244531e87130f Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Sun, 6 May 2018 15:20:05 +0100 Subject: uninorth: remove token register from uninorth device >From observation of various OS sources it can be seen that the token register introduced in 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" is not required, since the only register currently implemented is the uninorth hardware version which is read-only. Remove the token register implementation and instead return the uninorth version corresponding to the hardware. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- include/hw/pci-host/uninorth.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h index f6654bad9b..2a1cf9f284 100644 --- a/include/hw/pci-host/uninorth.h +++ b/include/hw/pci-host/uninorth.h @@ -29,6 +29,9 @@ #include "hw/ppc/openpic.h" +/* UniNorth version */ +#define UNINORTH_VERSION_10A 0x7 + #define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost" #define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost" #define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost" @@ -57,7 +60,6 @@ typedef struct UNINState { SysBusDevice parent_obj; MemoryRegion mem; - int token[1]; } UNINState; #define TYPE_UNI_NORTH "uni-north" -- cgit v1.2.3-55-g7522 From 0c1272cc7c72dfe0ef66be8f283cf67c74b58586 Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Sun, 6 May 2018 17:29:49 +1000 Subject: osdep: powerpc64 align memory to allow 2MB radix THP page tables This allows KVM with the Book3S radix MMU mode to take advantage of THP and install larger pages in the partition scope page tables (the host translation). Signed-off-by: Nicholas Piggin Signed-off-by: David Gibson --- include/qemu/osdep.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index afc28e5903..9ed62423c0 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -367,7 +367,8 @@ void qemu_anon_ram_free(void *ptr, size_t size); #endif #if defined(__linux__) && \ - (defined(__x86_64__) || defined(__arm__) || defined(__aarch64__)) + (defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) \ + || defined(__powerpc64__)) /* Use 2 MiB alignment so transparent hugepages can be used by KVM. Valgrind does not support alignments larger than 1 MiB, therefore we need special code which handles running on Valgrind. */ -- cgit v1.2.3-55-g7522 From 5b64db9754bde0b8e0329ce77d3647a0a2f6da56 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 7 Jun 2018 17:59:55 +0100 Subject: ppc: add missing FW_CFG_PPC_NVRAM_FLAT definition This is used in OpenBIOS to define the memory layout of the NVRAM device. Whilst currently left at its default value, add the missing definition to ensure it is reserved. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- include/hw/ppc/ppc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index ff0ac306be..b18ef3eefb 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -100,6 +100,7 @@ enum { #define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07) #define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08) #define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09) +#define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a) #define PPC_SERIAL_MM_BAUDBASE 399193 -- cgit v1.2.3-55-g7522 From 2e3e5c7e92452900e2bb5143c5fb6d47c0897a34 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 7 Jun 2018 18:17:49 +0100 Subject: cuda: embed mos6522_cuda device directly rather than using QOM object link Examining the migration stream it can be seen that the mos6522 device state is being stored separately rather than as part of the CUDA device which is incorrect (and likely to cause issues if another mos6522 device is added to the machine). Resolve this by embedding the mos6522_cuda device directly within the CUDA device rather than using a QOM object link to reference the device separately. Note that we also bump the version in vmstate_cuda to reflect this change: this isn't particularly important for the moment as the Mac machine migration isn't 100% reliable due to issues migrating the timebase under TCG. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 44 ++++++++++++++++++-------------------------- hw/misc/mos6522.c | 2 +- include/hw/misc/macio/cuda.h | 27 ++++++++++++--------------- include/hw/misc/mos6522.h | 2 ++ 4 files changed, 33 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index bd9b862034..8aba2e63ec 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -65,7 +65,7 @@ static void cuda_receive_packet_from_host(CUDAState *s, static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) { MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); - CUDAState *cs = mcs->cuda; + CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup */ uint64_t tb_diff = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), @@ -78,7 +78,7 @@ static uint64_t cuda_get_counter_value(MOS6522State *s, MOS6522Timer *ti) static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) { MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); - CUDAState *cs = mcs->cuda; + CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); uint64_t load_time = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cs->tb_frequency, NANOSECONDS_PER_SECOND); @@ -88,7 +88,7 @@ static uint64_t cuda_get_load_time(MOS6522State *s, MOS6522Timer *ti) static void cuda_set_sr_int(void *opaque) { CUDAState *s = opaque; - MOS6522CUDAState *mcs = s->mos6522_cuda; + MOS6522CUDAState *mcs = &s->mos6522_cuda; MOS6522State *ms = MOS6522(mcs); MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); @@ -97,7 +97,7 @@ static void cuda_set_sr_int(void *opaque) static void cuda_delay_set_sr_int(CUDAState *s) { - MOS6522CUDAState *mcs = s->mos6522_cuda; + MOS6522CUDAState *mcs = &s->mos6522_cuda; MOS6522State *ms = MOS6522(mcs); MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); int64_t expire; @@ -117,7 +117,7 @@ static void cuda_delay_set_sr_int(CUDAState *s) /* NOTE: TIP and TREQ are negated */ static void cuda_update(CUDAState *s) { - MOS6522CUDAState *mcs = s->mos6522_cuda; + MOS6522CUDAState *mcs = &s->mos6522_cuda; MOS6522State *ms = MOS6522(mcs); int packet_received, len; @@ -462,7 +462,7 @@ static void cuda_receive_packet_from_host(CUDAState *s, static uint64_t mos6522_cuda_read(void *opaque, hwaddr addr, unsigned size) { CUDAState *s = opaque; - MOS6522CUDAState *mcs = s->mos6522_cuda; + MOS6522CUDAState *mcs = &s->mos6522_cuda; MOS6522State *ms = MOS6522(mcs); addr = (addr >> 9) & 0xf; @@ -473,7 +473,7 @@ static void mos6522_cuda_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { CUDAState *s = opaque; - MOS6522CUDAState *mcs = s->mos6522_cuda; + MOS6522CUDAState *mcs = &s->mos6522_cuda; MOS6522State *ms = MOS6522(mcs); addr = (addr >> 9) & 0xf; @@ -492,9 +492,11 @@ static const MemoryRegionOps mos6522_cuda_ops = { static const VMStateDescription vmstate_cuda = { .name = "cuda", - .version_id = 4, - .minimum_version_id = 4, + .version_id = 5, + .minimum_version_id = 5, .fields = (VMStateField[]) { + VMSTATE_STRUCT(mos6522_cuda.parent_obj, CUDAState, 0, vmstate_mos6522, + MOS6522State), VMSTATE_UINT8(last_b, CUDAState), VMSTATE_UINT8(last_acr, CUDAState), VMSTATE_INT32(data_in_size, CUDAState), @@ -530,12 +532,8 @@ static void cuda_realize(DeviceState *dev, Error **errp) DeviceState *d; struct tm tm; - d = qdev_create(NULL, TYPE_MOS6522_CUDA); - object_property_set_link(OBJECT(d), OBJECT(s), "cuda", errp); - qdev_init_nofail(d); - s->mos6522_cuda = MOS6522_CUDA(d); - /* Pass IRQ from 6522 */ + d = DEVICE(&s->mos6522_cuda); ms = MOS6522(d); sbd = SYS_BUS_DEVICE(s); sysbus_pass_irq(sbd, SYS_BUS_DEVICE(ms)); @@ -556,6 +554,10 @@ static void cuda_init(Object *obj) CUDAState *s = CUDA(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + object_initialize(&s->mos6522_cuda, sizeof(s->mos6522_cuda), + TYPE_MOS6522_CUDA); + qdev_set_parent_bus(DEVICE(&s->mos6522_cuda), sysbus_get_default()); + memory_region_init_io(&s->mem, obj, &mos6522_cuda_ops, s, "cuda", 0x2000); sysbus_init_mmio(sbd, &s->mem); @@ -590,8 +592,9 @@ static const TypeInfo cuda_type_info = { static void mos6522_cuda_portB_write(MOS6522State *s) { MOS6522CUDAState *mcs = container_of(s, MOS6522CUDAState, parent_obj); + CUDAState *cs = container_of(mcs, CUDAState, mos6522_cuda); - cuda_update(mcs->cuda); + cuda_update(cs); } static void mos6522_cuda_realize(DeviceState *dev, Error **errp) @@ -605,16 +608,6 @@ static void mos6522_cuda_realize(DeviceState *dev, Error **errp) ms->timers[1].frequency = (SCALE_US * 6000) / 4700; } -static void mos6522_cuda_init(Object *obj) -{ - MOS6522CUDAState *s = MOS6522_CUDA(obj); - - object_property_add_link(obj, "cuda", TYPE_CUDA, - (Object **) &s->cuda, - qdev_prop_allow_set_link_before_realize, - 0, NULL); -} - static void mos6522_cuda_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -632,7 +625,6 @@ static const TypeInfo mos6522_cuda_type_info = { .name = TYPE_MOS6522_CUDA, .parent = TYPE_MOS6522, .instance_size = sizeof(MOS6522CUDAState), - .instance_init = mos6522_cuda_init, .class_init = mos6522_cuda_class_init, }; diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index bcb306d357..524a250329 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -390,7 +390,7 @@ static const VMStateDescription vmstate_mos6522_timer = { } }; -static const VMStateDescription vmstate_mos6522 = { +const VMStateDescription vmstate_mos6522 = { .name = "mos6522", .version_id = 0, .minimum_version_id = 0, diff --git a/include/hw/misc/macio/cuda.h b/include/hw/misc/macio/cuda.h index 494b709579..7dad469142 100644 --- a/include/hw/misc/macio/cuda.h +++ b/include/hw/misc/macio/cuda.h @@ -54,12 +54,21 @@ #define CUDA_TIMER_TICKLE 0x24 #define CUDA_COMBINED_FORMAT_IIC 0x25 + +/* MOS6522 CUDA */ +typedef struct MOS6522CUDAState { + /*< private >*/ + MOS6522State parent_obj; +} MOS6522CUDAState; + +#define TYPE_MOS6522_CUDA "mos6522-cuda" +#define MOS6522_CUDA(obj) OBJECT_CHECK(MOS6522CUDAState, (obj), \ + TYPE_MOS6522_CUDA) + /* Cuda */ #define TYPE_CUDA "cuda" #define CUDA(obj) OBJECT_CHECK(CUDAState, (obj), TYPE_CUDA) -typedef struct MOS6522CUDAState MOS6522CUDAState; - typedef struct CUDAState { /*< private >*/ SysBusDevice parent_obj; @@ -67,7 +76,7 @@ typedef struct CUDAState { MemoryRegion mem; ADBBusState adb_bus; - MOS6522CUDAState *mos6522_cuda; + MOS6522CUDAState mos6522_cuda; uint32_t tick_offset; uint64_t tb_frequency; @@ -92,16 +101,4 @@ typedef struct CUDAState { QEMUTimer *adb_poll_timer; } CUDAState; -/* MOS6522 CUDA */ -struct MOS6522CUDAState { - /*< private >*/ - MOS6522State parent_obj; - - CUDAState *cuda; -}; - -#define TYPE_MOS6522_CUDA "mos6522-cuda" -#define MOS6522_CUDA(obj) OBJECT_CHECK(MOS6522CUDAState, (obj), \ - TYPE_MOS6522_CUDA) - #endif /* CUDA_H */ diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index a53c161b00..cb0fd7db78 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -146,6 +146,8 @@ typedef struct MOS6522DeviceClass { #define MOS6522_DEVICE_GET_CLASS(obj) \ OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522) +extern const VMStateDescription vmstate_mos6522; + uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size); void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size); -- cgit v1.2.3-55-g7522 From d638fd5c9681dbb8915147365520888c64f39dac Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Thu, 7 Jun 2018 18:17:50 +0100 Subject: mos6522: move timer frequency initialisation to mos6522_reset The 6522 VIA timer frequency cannot be set by altering registers within the device itself and hence it is a fixed property of the machine. Move the initialisation of the timer frequency to the mos6522 reset function and ensure that any subclasses always call the parent reset function so that it isn't required to store the timer frequency within vmstate_mos6522_timer itself. By moving the frequency initialisation to the device reset function then we find that the realize function for both mos6522 and mos6522_cuda becomes obsolete and can simply be removed. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/misc/macio/cuda.c | 6 +++--- hw/misc/mos6522.c | 13 +++---------- include/hw/misc/mos6522.h | 2 +- 3 files changed, 7 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 8aba2e63ec..9651ed9744 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -597,12 +597,12 @@ static void mos6522_cuda_portB_write(MOS6522State *s) cuda_update(cs); } -static void mos6522_cuda_realize(DeviceState *dev, Error **errp) +static void mos6522_cuda_reset(DeviceState *dev) { MOS6522State *ms = MOS6522(dev); MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms); - mdc->parent_realize(dev, errp); + mdc->parent_reset(dev); ms->timers[0].frequency = CUDA_TIMER_FREQ; ms->timers[1].frequency = (SCALE_US * 6000) / 4700; @@ -613,7 +613,7 @@ static void mos6522_cuda_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); - dc->realize = mos6522_cuda_realize; + dc->reset = mos6522_cuda_reset; mdc->portB_write = mos6522_cuda_portB_write; mdc->get_timer1_counter_value = cuda_get_counter_value; mdc->get_timer2_counter_value = cuda_get_counter_value; diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 524a250329..2f58b9707f 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -427,18 +427,12 @@ static void mos6522_reset(DeviceState *dev) /* s->ier = T1_INT | SR_INT; */ s->anh = 0; + s->timers[0].frequency = s->frequency; s->timers[0].latch = 0xffff; set_counter(s, &s->timers[0], 0xffff); - s->timers[1].latch = 0xffff; -} - -static void mos6522_realize(DeviceState *dev, Error **errp) -{ - MOS6522State *s = MOS6522(dev); - - s->timers[0].frequency = s->frequency; s->timers[1].frequency = s->frequency; + s->timers[1].latch = 0xffff; } static void mos6522_init(Object *obj) @@ -469,11 +463,10 @@ static void mos6522_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc); - dc->realize = mos6522_realize; dc->reset = mos6522_reset; dc->vmsd = &vmstate_mos6522; dc->props = mos6522_properties; - mdc->parent_realize = dc->realize; + mdc->parent_reset = dc->reset; mdc->set_sr_int = mos6522_set_sr_int; mdc->portB_write = mos6522_portB_write; mdc->portA_write = mos6522_portA_write; diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index cb0fd7db78..f52b41920b 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -130,7 +130,7 @@ typedef struct MOS6522State { typedef struct MOS6522DeviceClass { DeviceClass parent_class; - DeviceRealize parent_realize; + DeviceReset parent_reset; void (*set_sr_int)(MOS6522State *dev); void (*portB_write)(MOS6522State *dev); void (*portA_write)(MOS6522State *dev); -- cgit v1.2.3-55-g7522 From d61c2857037e6211667a52563742af798d4c0332 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 11 Jun 2018 19:12:10 +0200 Subject: ppc/pnv: fix LPC HC firmware address space A specific MemoryRegion is required for the LPC HC Firmware address space. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_lpc.c | 4 +++- include/hw/ppc/pnv_lpc.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 2317d1e62c..402c4fefa8 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -79,6 +79,7 @@ enum { #define ISA_IO_SIZE 0x00010000 #define ISA_MEM_SIZE 0x10000000 +#define ISA_FW_SIZE 0x10000000 #define LPC_IO_OPB_ADDR 0xd0010000 #define LPC_IO_OPB_SIZE 0x00010000 #define LPC_MEM_OPB_ADDR 0xe0010000 @@ -429,6 +430,7 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) */ memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); + memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE); /* Create windows from the OPB space to the ISA space */ memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", @@ -440,7 +442,7 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, &lpc->opb_isa_mem); memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", - &lpc->isa_mem, 0, LPC_FW_OPB_SIZE); + &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, &lpc->opb_isa_fw); diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h index 023b4f0fec..53fdd5bb64 100644 --- a/include/hw/ppc/pnv_lpc.h +++ b/include/hw/ppc/pnv_lpc.h @@ -38,6 +38,7 @@ typedef struct PnvLpcController { /* ISA IO and Memory space */ MemoryRegion isa_io; MemoryRegion isa_mem; + MemoryRegion isa_fw; /* Windows from OPB to ISA (aliases) */ MemoryRegion opb_isa_io; -- cgit v1.2.3-55-g7522