From 40061ac0bc5bdfcfa1234dbf8e2a880fd9fc4c2e Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Fri, 14 Dec 2018 00:19:12 +0000 Subject: sifive_uart: Implement interrupt pending register The watermark bits are set in the interrupt pending register according to the configuration of txcnt and rxcnt in the txctrl and rxctrl registers. Since the UART TX does not implement a FIFO, the txwm bit is set as long as the TX watermark level is greater than zero. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- include/hw/riscv/sifive_uart.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h index 504f18a60f..c8dc1c57fd 100644 --- a/include/hw/riscv/sifive_uart.h +++ b/include/hw/riscv/sifive_uart.h @@ -43,6 +43,9 @@ enum { SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ }; +#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) +#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) + #define TYPE_SIFIVE_UART "riscv.sifive.uart" #define SIFIVE_UART(obj) \ -- cgit v1.2.3-55-g7522