From ecce0369b864e3c505b89942cd8cc23a62a4386f Mon Sep 17 00:00:00 2001 From: Nikunj A Dadhania Date: Sun, 30 Oct 2016 08:44:55 +0530 Subject: bitops: fix rol/ror when shift is zero All the variants for rol/ror have a bug in case where the shift == 0. For example rol32, would generate: return (word << 0) | (word >> 32); Which though works, would be flagged as a runtime error on clang's sanitizer. Suggested-by: Richard Henderson Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- include/qemu/bitops.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 98fb005aba..1881284cb5 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -218,7 +218,7 @@ static inline unsigned long hweight_long(unsigned long w) */ static inline uint8_t rol8(uint8_t word, unsigned int shift) { - return (word << shift) | (word >> (8 - shift)); + return (word << shift) | (word >> ((8 - shift) & 7)); } /** @@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift) */ static inline uint8_t ror8(uint8_t word, unsigned int shift) { - return (word >> shift) | (word << (8 - shift)); + return (word >> shift) | (word << ((8 - shift) & 7)); } /** @@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift) */ static inline uint16_t rol16(uint16_t word, unsigned int shift) { - return (word << shift) | (word >> (16 - shift)); + return (word << shift) | (word >> ((16 - shift) & 15)); } /** @@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift) */ static inline uint16_t ror16(uint16_t word, unsigned int shift) { - return (word >> shift) | (word << (16 - shift)); + return (word >> shift) | (word << ((16 - shift) & 15)); } /** @@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift) */ static inline uint32_t rol32(uint32_t word, unsigned int shift) { - return (word << shift) | (word >> (32 - shift)); + return (word << shift) | (word >> ((32 - shift) & 31)); } /** @@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift) */ static inline uint32_t ror32(uint32_t word, unsigned int shift) { - return (word >> shift) | (word << (32 - shift)); + return (word >> shift) | (word << ((32 - shift) & 31)); } /** @@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift) */ static inline uint64_t rol64(uint64_t word, unsigned int shift) { - return (word << shift) | (word >> (64 - shift)); + return (word << shift) | (word >> ((64 - shift) & 63)); } /** @@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift) */ static inline uint64_t ror64(uint64_t word, unsigned int shift) { - return (word >> shift) | (word << (64 - shift)); + return (word >> shift) | (word << ((64 - shift) & 63)); } /** -- cgit v1.2.3-55-g7522 From ec575aa0ae8caf1c7af66dad753d1d19a958a8c5 Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 7 Nov 2016 19:03:02 +0100 Subject: ppc/pnv: fix compile breakage on old gcc PnvChip is defined twice and this can confuse old compilers : CC ppc64-softmmu/hw/ppc/pnv_xscom.o In file included from qemu.git/hw/ppc/pnv.c:29: qemu.git/include/hw/ppc/pnv.h:60: error: redefinition of typedef ‘PnvChip’ qemu.git/include/hw/ppc/pnv_xscom.h:24: note: previous declaration of ‘PnvChip’ was here make[1]: *** [hw/ppc/pnv.o] Error 1 make[1]: *** Waiting for unfinished jobs.... Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_core.c | 1 + hw/ppc/pnv_lpc.c | 3 ++- hw/ppc/pnv_xscom.c | 2 +- include/hw/ppc/pnv.h | 1 - include/hw/ppc/pnv_xscom.h | 2 -- 5 files changed, 4 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 2acda9637d..76ce854b0c 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -24,6 +24,7 @@ #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_xscom.h" static void powernv_cpu_reset(void *opaque) { diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 00dbd8b07b..0e2117f0f5 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -23,8 +23,9 @@ #include "qapi/error.h" #include "qemu/log.h" -#include "hw/ppc/pnv_lpc.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_lpc.h" +#include "hw/ppc/pnv_xscom.h" #include "hw/ppc/fdt.h" #include diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 5aaa264bd7..f46646141a 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -25,8 +25,8 @@ #include "hw/sysbus.h" #include "hw/ppc/fdt.h" -#include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_xscom.h" #include diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 02ac1c5f42..7bee658733 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -21,7 +21,6 @@ #include "hw/boards.h" #include "hw/sysbus.h" -#include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_lpc.h" #define TYPE_PNV_CHIP "powernv-chip" diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index c0a2fbb9f6..41a5127a19 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -21,8 +21,6 @@ #include "qom/object.h" -typedef struct PnvChip PnvChip; - typedef struct PnvXScomInterface { Object parent; } PnvXScomInterface; -- cgit v1.2.3-55-g7522 From ad521238b458a6d54ab672ed3f94d5edaa786d5c Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 14 Nov 2016 10:12:55 +0100 Subject: ppc/pnv: add a 'xscom_core_base' field to PnvChipClass The XSCOM addresses for the core registers are encoded in a slightly different way on POWER8 and POWER9. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 8 +++++++- include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_xscom.h | 5 ++--- 3 files changed, 10 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6af34241f2..e777958154 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -521,6 +521,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->cores_mask = POWER8E_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; k->xscom_base = 0x003fc0000000000ull; + k->xscom_core_base = 0x10000000ull; dc->desc = "PowerNV Chip POWER8E"; } @@ -542,6 +543,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->cores_mask = POWER8_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; k->xscom_base = 0x003fc0000000000ull; + k->xscom_core_base = 0x10000000ull; dc->desc = "PowerNV Chip POWER8"; } @@ -563,6 +565,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->cores_mask = POWER8_CORE_MASK; k->core_pir = pnv_chip_core_pir_p8; k->xscom_base = 0x003fc0000000000ull; + k->xscom_core_base = 0x10000000ull; dc->desc = "PowerNV Chip POWER8NVL"; } @@ -584,6 +587,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->cores_mask = POWER9_CORE_MASK; k->core_pir = pnv_chip_core_pir_p9; k->xscom_base = 0x00603fc00000000ull; + k->xscom_core_base = 0x0ull; dc->desc = "PowerNV Chip POWER9"; } @@ -691,7 +695,9 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp) object_unref(OBJECT(pnv_core)); /* Each core has an XSCOM MMIO region */ - pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid), + pnv_xscom_add_subregion(chip, + PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base, + core_hwid), &PNV_CORE(pnv_core)->xscom_regs); i++; } diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7bee658733..df98a72006 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -69,6 +69,7 @@ typedef struct PnvChipClass { uint64_t cores_mask; hwaddr xscom_base; + hwaddr xscom_core_base; uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); } PnvChipClass; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 41a5127a19..0faa1847bf 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -40,7 +40,7 @@ typedef struct PnvXScomInterfaceClass { } PnvXScomInterfaceClass; /* - * Layout of the XSCOM PCB addresses of EX core 1 + * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8) * * GPIO 0x1100xxxx * SCOM 0x1101xxxx @@ -54,8 +54,7 @@ typedef struct PnvXScomInterfaceClass { * PCB SLAVE 0x110Fxxxx */ -#define PNV_XSCOM_EX_BASE 0x10000000 -#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i) << 24)) +#define PNV_XSCOM_EX_CORE_BASE(base, i) (base | (((uint64_t)i) << 24)) #define PNV_XSCOM_EX_CORE_SIZE 0x100000 #define PNV_XSCOM_LPC_BASE 0xb0020 -- cgit v1.2.3-55-g7522