From 42bff4772ef96d901772240b10eda6d66ef771a1 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Tue, 7 Jun 2016 22:28:42 +1000 Subject: Add PowerPC AT_HWCAP2 definitions We need the PPC_FEATURE2_HAS_HTM bit in a subsequent patch, so add the PowerPC AT_HWCAP2 definitions. Signed-off-by: Anton Blanchard Signed-off-by: David Gibson --- include/elf.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/elf.h b/include/elf.h index 28d448bbcc..8533b2a8b0 100644 --- a/include/elf.h +++ b/include/elf.h @@ -477,6 +477,19 @@ typedef struct { #define PPC_FEATURE_TRUE_LE 0x00000002 #define PPC_FEATURE_PPC_LE 0x00000001 +/* Bits present in AT_HWCAP2 for PowerPC. */ + +#define PPC_FEATURE2_ARCH_2_07 0x80000000 +#define PPC_FEATURE2_HAS_HTM 0x40000000 +#define PPC_FEATURE2_HAS_DSCR 0x20000000 +#define PPC_FEATURE2_HAS_EBB 0x10000000 +#define PPC_FEATURE2_HAS_ISEL 0x08000000 +#define PPC_FEATURE2_HAS_TAR 0x04000000 +#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 +#define PPC_FEATURE2_HTM_NOSC 0x01000000 +#define PPC_FEATURE2_ARCH_3_00 0x00800000 +#define PPC_FEATURE2_HAS_IEEE128 0x00400000 + /* Bits present in AT_HWCAP for Sparc. */ #define HWCAP_SPARC_FLUSH 0x00000001 -- cgit v1.2.3-55-g7522 From bc9ca5958d084222cdb233619dfc5046c81fb76d Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Fri, 10 Jun 2016 19:26:37 +0100 Subject: macio: call dma_memory_unmap() at the end of each DMA transfer This ensures that the underlying memory is marked dirty once the transfer is complete and resolves cache coherency problems under MacOS 9. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/ide/macio.c | 46 ++++++++++++++++++++++++++-------------------- include/hw/ppc/mac_dbdma.h | 5 +++++ 2 files changed, 31 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 78c10a0406..fa57352fc8 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -66,8 +66,7 @@ static void pmac_dma_read(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; int64_t sector_num; int nsector; uint64_t align = BDRV_SECTOR_SIZE; @@ -84,9 +83,10 @@ static void pmac_dma_read(BlockBackend *blk, sector_num, nsector); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_FROM_DEVICE); + io->dir = DMA_DIRECTION_FROM_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); if (offset & (align - 1)) { head_bytes = offset & (align - 1); @@ -100,7 +100,7 @@ static void pmac_dma_read(BlockBackend *blk, offset = offset & ~(align - 1); } - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); if ((offset + bytes) & (align - 1)) { tail_bytes = (offset + bytes) & (align - 1); @@ -130,8 +130,7 @@ static void pmac_dma_write(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; int64_t sector_num; int nsector; uint64_t align = BDRV_SECTOR_SIZE; @@ -149,9 +148,10 @@ static void pmac_dma_write(BlockBackend *blk, sector_num, nsector); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_TO_DEVICE); + io->dir = DMA_DIRECTION_TO_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); if (offset & (align - 1)) { head_bytes = offset & (align - 1); @@ -163,7 +163,7 @@ static void pmac_dma_write(BlockBackend *blk, blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align); qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes); - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); bytes += offset & (align - 1); offset = offset & ~(align - 1); @@ -181,7 +181,7 @@ static void pmac_dma_write(BlockBackend *blk, blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align); if (!unaligned_head) { - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); } qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes, @@ -193,7 +193,7 @@ static void pmac_dma_write(BlockBackend *blk, } if (!unaligned_head && !unaligned_tail) { - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); } s->io_buffer_size -= io->len; @@ -214,18 +214,18 @@ static void pmac_dma_trim(BlockBackend *blk, DBDMA_io *io = opaque; MACIOIDEState *m = io->opaque; IDEState *s = idebus_active_if(&m->bus); - dma_addr_t dma_addr, dma_len; - void *mem; + dma_addr_t dma_addr; qemu_iovec_destroy(&io->iov); qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1); dma_addr = io->addr; - dma_len = io->len; - mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len, - DMA_DIRECTION_TO_DEVICE); + io->dir = DMA_DIRECTION_TO_DEVICE; + io->dma_len = io->len; + io->dma_mem = dma_memory_map(&address_space_memory, dma_addr, &io->dma_len, + io->dir); - qemu_iovec_add(&io->iov, mem, io->len); + qemu_iovec_add(&io->iov, io->dma_mem, io->len); s->io_buffer_size -= io->len; s->io_buffer_index += io->len; io->len = 0; @@ -285,6 +285,9 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int ret) return; done: + dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, + io->dir, io->dma_len); + if (ret < 0) { block_acct_failed(blk_get_stats(s->blk), &s->acct); } else { @@ -351,6 +354,9 @@ static void pmac_ide_transfer_cb(void *opaque, int ret) return; done: + dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len, + io->dir, io->dma_len); + if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) { if (ret < 0) { block_acct_failed(blk_get_stats(s->blk), &s->acct); diff --git a/include/hw/ppc/mac_dbdma.h b/include/hw/ppc/mac_dbdma.h index 0cce4e8bb4..d15a6ccf3e 100644 --- a/include/hw/ppc/mac_dbdma.h +++ b/include/hw/ppc/mac_dbdma.h @@ -24,6 +24,7 @@ #include "exec/memory.h" #include "qemu/iov.h" +#include "sysemu/dma.h" typedef struct DBDMA_io DBDMA_io; @@ -44,6 +45,10 @@ struct DBDMA_io { uint8_t head_remainder[0x200]; uint8_t tail_remainder[0x200]; QEMUIOVector iov; + /* DMA request */ + void *dma_mem; + dma_addr_t dma_len; + DMADirection dir; }; /* -- cgit v1.2.3-55-g7522 From d0e5a8f2937de66778d94c20a8fc5cf43501fa04 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Fri, 10 Jun 2016 10:44:48 +0530 Subject: spapr: Ensure all LMBs are represented in ibm,dynamic-memory Memory hotplug can fail for some combinations of RAM and maxmem when DDW is enabled in the presence of devices like nec-usb-xhci. DDW depends on maximum addressable memory returned by guest and this value is currently being calculated wrongly by the guest kernel routine memory_hotplug_max(). While there is an attempt to fix the guest kernel, this patch works around the problem within QEMU itself. memory_hotplug_max() routine in the guest kernel arrives at max addressable memory by multiplying lmb-size with the lmb-count obtained from ibm,dynamic-memory property. There are two assumptions here: - All LMBs are part of ibm,dynamic memory: This is not true for PowerKVM where only hot-pluggable LMBs are present in this property. - The memory area comprising of RAM and hotplug region is contiguous: This needn't be true always for PowerKVM as there can be gap between boot time RAM and hotplug region. To work around this guest kernel bug, ensure that ibm,dynamic-memory has information about all the LMBs (RMA, boot-time LMBs, future hotpluggable LMBs, and dummy LMBs to cover the gap between RAM and hotpluggable region). RMA is represented separately by memory@0 node. Hence mark RMA LMBs and also the LMBs for the gap b/n RAM and hotpluggable region as reserved and as having no valid DRC so that these LMBs are not considered by the guest. Signed-off-by: Bharata B Rao Reviewed-by: Michael Roth Reviewed-by: Nathan Fontenot Signed-off-by: David Gibson --- hw/ppc/spapr.c | 57 ++++++++++++++++++++++++++++++++------------------ include/hw/ppc/spapr.h | 6 ++++-- 2 files changed, 41 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 0636642341..9a4a803b17 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -762,14 +762,17 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) int ret, i, offset; uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; - uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; + uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; + uint32_t nr_lmbs = (spapr->hotplug_memory.base + + memory_region_size(&spapr->hotplug_memory.mr)) / + lmb_size; uint32_t *int_buf, *cur_index, buf_len; int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; /* - * Don't create the node if there are no DR LMBs. + * Don't create the node if there is no hotpluggable memory */ - if (!nr_lmbs) { + if (machine->ram_size == machine->maxram_size) { return 0; } @@ -803,26 +806,40 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) int_buf[0] = cpu_to_be32(nr_lmbs); cur_index++; for (i = 0; i < nr_lmbs; i++) { - sPAPRDRConnector *drc; - sPAPRDRConnectorClass *drck; - uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; + uint64_t addr = i * lmb_size; uint32_t *dynamic_memory = cur_index; - drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, - addr/lmb_size); - g_assert(drc); - drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); - - dynamic_memory[0] = cpu_to_be32(addr >> 32); - dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); - dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); - dynamic_memory[3] = cpu_to_be32(0); /* reserved */ - dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); - if (addr < machine->ram_size || - memory_region_present(get_system_memory(), addr)) { - dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); + if (i >= hotplug_lmb_start) { + sPAPRDRConnector *drc; + sPAPRDRConnectorClass *drck; + + drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); + g_assert(drc); + drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); + + dynamic_memory[0] = cpu_to_be32(addr >> 32); + dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); + dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); + dynamic_memory[3] = cpu_to_be32(0); /* reserved */ + dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); + if (memory_region_present(get_system_memory(), addr)) { + dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); + } else { + dynamic_memory[5] = cpu_to_be32(0); + } } else { - dynamic_memory[5] = cpu_to_be32(0); + /* + * LMB information for RMA, boot time RAM and gap b/n RAM and + * hotplug memory region -- all these are marked as reserved + * and as having no valid DRC. + */ + dynamic_memory[0] = cpu_to_be32(addr >> 32); + dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); + dynamic_memory[2] = cpu_to_be32(0); + dynamic_memory[3] = cpu_to_be32(0); /* reserved */ + dynamic_memory[4] = cpu_to_be32(-1); + dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | + SPAPR_LMB_FLAGS_DRC_INVALID); } cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 971df3d0df..3ac85c07d7 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -620,9 +620,11 @@ int spapr_rng_populate_dt(void *fdt); #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 /* - * This flag value defines the LMB as assigned in ibm,dynamic-memory - * property under ibm,dynamic-reconfiguration-memory node. + * Defines for flag value in ibm,dynamic-memory property under + * ibm,dynamic-reconfiguration-memory node. */ #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 +#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 +#define SPAPR_LMB_FLAGS_RESERVED 0x00000080 #endif /* !defined (__HW_SPAPR_H__) */ -- cgit v1.2.3-55-g7522