From b3793b8a9183d6019f557263bbddd647e1918394 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: Remove tabs Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: <2d9b2c470ec022cc85a25b3e5de337b5e794f7f6.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sh4/sh.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index becb596979..3d5ba598d0 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -44,25 +44,25 @@ typedef struct { uint16_t portbmask_trigger; /* Return 0 if no action was taken */ int (*port_change_cb) (uint16_t porta, uint16_t portb, - uint16_t * periph_pdtra, - uint16_t * periph_portdira, - uint16_t * periph_pdtrb, - uint16_t * periph_portdirb); + uint16_t * periph_pdtra, + uint16_t * periph_portdira, + uint16_t * periph_pdtrb, + uint16_t * periph_portdirb); } sh7750_io_device; int sh7750_register_io_device(struct SH7750State *s, - sh7750_io_device * device); + sh7750_io_device * device); /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) void sh_serial_init(MemoryRegion *sysmem, hwaddr base, int feat, uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source); + qemu_irq eri_source, + qemu_irq rxi_source, + qemu_irq txi_source, + qemu_irq tei_source, + qemu_irq bri_source); /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); -- cgit v1.2.3-55-g7522 From f94bff1337ff525e2ff458b8e4cd57f9561acde3 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/sh4: Coding style: White space fixes Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Yoshinori Sato Message-Id: <91698c54fa493a4cfe93546211206439787d4b78.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 23 ++++++++++------------- hw/intc/sh_intc.c | 39 +++++++++++++++++++++++---------------- hw/pci-host/sh_pci.c | 10 ++++------ hw/sh4/r2d.c | 39 ++++++++++++++++++++------------------- hw/sh4/sh7750.c | 26 +++++++++++++------------- hw/sh4/sh7750_regnames.c | 5 +++-- hw/sh4/sh7750_regs.h | 18 +++++++++--------- hw/sh4/shix.c | 2 +- hw/timer/sh_timer.c | 22 ++++++++++++++++------ include/hw/sh4/sh.h | 10 +++++----- 10 files changed, 104 insertions(+), 90 deletions(-) (limited to 'include') diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 05ae8e84ce..3fdb9f9a99 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -75,7 +75,7 @@ typedef struct { qemu_irq bri; } sh_serial_state; -static void sh_serial_clear_fifo(sh_serial_state * s) +static void sh_serial_clear_fifo(sh_serial_state *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); s->rx_cnt = 0; @@ -93,7 +93,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, printf("sh_serial: write offs=0x%02x val=0x%02x\n", offs, val); #endif - switch(offs) { + switch (offs) { case 0x00: /* SMR */ s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff); return; @@ -131,7 +131,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, #endif } if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { + switch (offs) { case 0x10: /* FSR */ if (!(val & (1 << 6))) s->flags &= ~SH_SERIAL_FLAG_TEND; @@ -178,9 +178,8 @@ static void sh_serial_write(void *opaque, hwaddr offs, case 0x24: /* LSR */ return; } - } - else { - switch(offs) { + } else { + switch (offs) { #if 0 case 0x0c: ret = s->dr; @@ -207,7 +206,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, uint32_t ret = ~0; #if 0 - switch(offs) { + switch (offs) { case 0x00: ret = s->smr; break; @@ -223,7 +222,7 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, } #endif if (s->feat & SH_SERIAL_FEAT_SCIF) { - switch(offs) { + switch (offs) { case 0x00: /* SMR */ ret = s->smr; break; @@ -270,9 +269,8 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, ret = 0; break; } - } - else { - switch(offs) { + } else { + switch (offs) { #if 0 case 0x0c: ret = s->dr; @@ -397,8 +395,7 @@ void sh_serial_init(MemoryRegion *sysmem, if (feat & SH_SERIAL_FEAT_SCIF) { s->fcr = 0; - } - else { + } else { s->dr = 0xff; } diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index 84eec7d4ba..67005081e3 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -71,18 +71,18 @@ void sh_intc_toggle_source(struct intc_source *source, enable_changed == -1 ? "disabled " : "", source->pending ? "pending" : ""); #endif - } + } } -static void sh_intc_set_irq (void *opaque, int n, int level) +static void sh_intc_set_irq(void *opaque, int n, int level) { - struct intc_desc *desc = opaque; - struct intc_source *source = &(desc->sources[n]); + struct intc_desc *desc = opaque; + struct intc_source *source = &(desc->sources[n]); - if (level && !source->asserted) - sh_intc_toggle_source(source, 0, 1); - else if (!level && source->asserted) - sh_intc_toggle_source(source, 0, -1); + if (level && !source->asserted) + sh_intc_toggle_source(source, 0, 1); + else if (!level && source->asserted) + sh_intc_toggle_source(source, 0, -1); } int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) @@ -236,7 +236,7 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset, printf("sh_intc_read 0x%lx\n", (unsigned long) offset); #endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, + sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); return *valuep; } @@ -257,14 +257,20 @@ static void sh_intc_write(void *opaque, hwaddr offset, printf("sh_intc_write 0x%lx 0x%08x\n", (unsigned long) offset, value); #endif - sh_intc_locate(desc, (unsigned long)offset, &valuep, + sh_intc_locate(desc, (unsigned long)offset, &valuep, &enum_ids, &first, &width, &mode); switch (mode) { - case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; - case INTC_MODE_DUAL_SET: value |= *valuep; break; - case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break; - default: abort(); + case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: + break; + case INTC_MODE_DUAL_SET: + value |= *valuep; + break; + case INTC_MODE_DUAL_CLR: + value = *valuep & ~value; + break; + default: + abort(); } for (k = 0; k <= first; k++) { @@ -465,7 +471,7 @@ int sh_intc_init(MemoryRegion *sysmem, } desc->irqs = qemu_allocate_irqs(sh_intc_set_irq, desc, nr_sources); - + memory_region_init_io(&desc->iomem, NULL, &sh_intc_ops, desc, "interrupt-controller", 0x100000000ULL); @@ -507,7 +513,8 @@ void sh_intc_set_irl(void *opaque, int n, int level) int i, irl = level ^ 15; for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { if (i == irl) - sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); + sh_intc_toggle_source(s, s->enable_count ? 0 : 1, + s->asserted ? 0 : 1); else if (s->asserted) sh_intc_toggle_source(s, 0, -1); diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 08c1562e22..719d6ca2a6 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -49,13 +49,12 @@ struct SHPCIState { uint32_t iobr; }; -static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, - unsigned size) +static void sh_pci_reg_write(void *p, hwaddr addr, uint64_t val, unsigned size) { SHPCIState *pcic = p; PCIHostState *phb = PCI_HOST_BRIDGE(pcic); - switch(addr) { + switch (addr) { case 0 ... 0xfc: stl_le_p(pcic->dev->config + addr, val); break; @@ -75,13 +74,12 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val, } } -static uint64_t sh_pci_reg_read (void *p, hwaddr addr, - unsigned size) +static uint64_t sh_pci_reg_read(void *p, hwaddr addr, unsigned size) { SHPCIState *pcic = p; PCIHostState *phb = PCI_HOST_BRIDGE(pcic); - switch(addr) { + switch (addr) { case 0 ... 0xfc: return ldl_le_p(pcic->dev->config + addr); case 0x1c0: diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 46f1fae48c..216d6e24a1 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -96,19 +96,19 @@ enum r2d_fpga_irq { }; static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { - [CF_IDE] = { 1, 1<<9 }, - [CF_CD] = { 2, 1<<8 }, - [PCI_INTA] = { 9, 1<<14 }, - [PCI_INTB] = { 10, 1<<13 }, - [PCI_INTC] = { 3, 1<<12 }, - [PCI_INTD] = { 0, 1<<11 }, - [SM501] = { 4, 1<<10 }, - [KEY] = { 5, 1<<6 }, - [RTC_A] = { 6, 1<<5 }, - [RTC_T] = { 7, 1<<4 }, - [SDCARD] = { 8, 1<<7 }, - [EXT] = { 11, 1<<0 }, - [TP] = { 12, 1<<15 }, + [CF_IDE] = { 1, 1 << 9 }, + [CF_CD] = { 2, 1 << 8 }, + [PCI_INTA] = { 9, 1 << 14 }, + [PCI_INTB] = { 10, 1 << 13 }, + [PCI_INTC] = { 3, 1 << 12 }, + [PCI_INTD] = { 0, 1 << 11 }, + [SM501] = { 4, 1 << 10 }, + [KEY] = { 5, 1 << 6 }, + [RTC_A] = { 6, 1 << 5 }, + [RTC_T] = { 7, 1 << 4 }, + [SDCARD] = { 8, 1 << 7 }, + [EXT] = { 11, 1 << 0 }, + [TP] = { 12, 1 << 15 }, }; static void update_irl(r2d_fpga_t *fpga) @@ -306,7 +306,7 @@ static void r2d_init(MachineState *machine) /* NIC: rtl8139 on-board, and 2 slots. */ for (i = 0; i < nb_nics; i++) pci_nic_init_nofail(&nd_table[i], pci_bus, - "rtl8139", i==0 ? "2" : NULL); + "rtl8139", i == 0 ? "2" : NULL); /* USB keyboard */ usb_create_simple(usb_bus_find(-1), "usb-kbd"); @@ -321,8 +321,8 @@ static void r2d_init(MachineState *machine) SDRAM_BASE + LINUX_LOAD_OFFSET, INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); if (kernel_size < 0) { - fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); - exit(1); + fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); + exit(1); } /* initialization which should be done by firmware */ @@ -330,7 +330,8 @@ static void r2d_init(MachineState *machine) MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ - reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ + /* Start from P2 area */ + reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; } if (initrd_filename) { @@ -341,8 +342,8 @@ static void r2d_init(MachineState *machine) SDRAM_SIZE - INITRD_LOAD_OFFSET); if (initrd_size < 0) { - fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); - exit(1); + fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); + exit(1); } /* initialization which should be done by firmware */ diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 2539924b00..1e61f9f1c8 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -78,7 +78,7 @@ typedef struct SH7750State { struct intc_desc intc; } SH7750State; -static inline int has_bcr3_and_bcr4(SH7750State * s) +static inline int has_bcr3_and_bcr4(SH7750State *s) { return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; } @@ -87,7 +87,7 @@ static inline int has_bcr3_and_bcr4(SH7750State * s) * I/O ports */ -int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) +int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device) { int i; @@ -102,7 +102,7 @@ int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) static uint16_t portdir(uint32_t v) { -#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) +#define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) return EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | @@ -114,7 +114,7 @@ static uint16_t portdir(uint32_t v) static uint16_t portpullup(uint32_t v) { -#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) +#define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) return ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | @@ -123,26 +123,26 @@ static uint16_t portpullup(uint32_t v) ODDPORTMASK(1) | ODDPORTMASK(0); } -static uint16_t porta_lines(SH7750State * s) +static uint16_t porta_lines(SH7750State *s) { return (s->portdira & s->pdtra) | /* CPU */ (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ } -static uint16_t portb_lines(SH7750State * s) +static uint16_t portb_lines(SH7750State *s) { return (s->portdirb & s->pdtrb) | /* CPU */ (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ } -static void gen_port_interrupts(SH7750State * s) +static void gen_port_interrupts(SH7750State *s) { /* XXXXX interrupts not generated */ } -static void porta_changed(SH7750State * s, uint16_t prev) +static void porta_changed(SH7750State *s, uint16_t prev) { uint16_t currenta, changes; int i, r = 0; @@ -171,7 +171,7 @@ static void porta_changed(SH7750State * s, uint16_t prev) gen_port_interrupts(s); } -static void portb_changed(SH7750State * s, uint16_t prev) +static void portb_changed(SH7750State *s, uint16_t prev) { uint16_t currentb, changes; int i, r = 0; @@ -228,7 +228,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) case SH7750_BCR2_A7: return s->bcr2; case SH7750_BCR3_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("word read", addr); return s->bcr3; case SH7750_FRQCR_A7: @@ -263,7 +263,7 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) case SH7750_BCR1_A7: return s->bcr1; case SH7750_BCR4_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("long read", addr); return s->bcr4; case SH7750_WCR1_A7: @@ -332,7 +332,7 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr, s->bcr2 = mem_value; return; case SH7750_BCR3_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("word write", addr); s->bcr3 = mem_value; return; @@ -384,7 +384,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, s->bcr1 = mem_value; return; case SH7750_BCR4_A7: - if(!has_bcr3_and_bcr4(s)) + if (!has_bcr3_and_bcr4(s)) error_access("long write", addr); s->bcr4 = mem_value; return; diff --git a/hw/sh4/sh7750_regnames.c b/hw/sh4/sh7750_regnames.c index b1f112df3e..37b3acd620 100644 --- a/hw/sh4/sh7750_regnames.c +++ b/hw/sh4/sh7750_regnames.c @@ -81,14 +81,15 @@ static regname_t regnames[] = { REGNAME(SH7750_BCR3_A7) REGNAME(SH7750_BCR4_A7) REGNAME(SH7750_SDMR2_A7) - REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL} + REGNAME(SH7750_SDMR3_A7) + { (uint32_t)-1, NULL } }; const char *regname(uint32_t addr) { unsigned int i; - for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) { + for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) { if (regnames[i].regaddr == addr) return regnames[i].regname; } diff --git a/hw/sh4/sh7750_regs.h b/hw/sh4/sh7750_regs.h index bd12b0532d..beb571d5e9 100644 --- a/hw/sh4/sh7750_regs.h +++ b/hw/sh4/sh7750_regs.h @@ -1015,7 +1015,7 @@ */ /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ -#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ +#define SH7750_SAR_REGOFS(n) (0xA00000 + ((n) * 16)) /* offset */ #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) #define SH7750_SAR0 SH7750_SAR(0) @@ -1028,7 +1028,7 @@ #define SH7750_SAR3_A7 SH7750_SAR_A7(3) /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ -#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ +#define SH7750_DAR_REGOFS(n) (0xA00004 + ((n) * 16)) /* offset */ #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) #define SH7750_DAR0 SH7750_DAR(0) @@ -1041,7 +1041,7 @@ #define SH7750_DAR3_A7 SH7750_DAR_A7(3) /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ -#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ +#define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n) * 16)) /* offset */ #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) #define SH7750_DMATCR0_P4 SH7750_DMATCR(0) @@ -1054,7 +1054,7 @@ #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ -#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ +#define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n) * 16)) /* offset */ #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) #define SH7750_CHCR0 SH7750_CHCR(0) @@ -1208,9 +1208,9 @@ #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRA_PBNPUP(n) (1 << ((n) * 2 + 1)) /* Bit n is not pulled up */ #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ +#define SH7750_PCTRA_PBOUT(n) (1 << ((n) * 2)) /* Bit n is an output */ /* Port Data Register A - PDTRA(half) */ #define SH7750_PDTRA_REGOFS 0x800030 /* offset */ @@ -1225,16 +1225,16 @@ #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ -#define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ +#define SH7750_PCTRB_PBNPUP(n) (1 << ((n - 16) * 2 + 1)) /* Bit n is not pulled up */ #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ -#define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ +#define SH7750_PCTRB_PBOUT(n) (1 << ((n - 16) * 2)) /* Bit n is an output */ /* Port Data Register B - PDTRB(half) */ #define SH7750_PDTRB_REGOFS 0x800044 /* offset */ #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) -#define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) +#define SH7750_PDTRB_BIT(n) (1 << ((n) - 16)) /* GPIO Interrupt Control Register - GPIOIC(half) */ #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index 6b39de417f..aa812512f0 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -48,7 +48,7 @@ static void shix_init(MachineState *machine) MemoryRegion *rom = g_new(MemoryRegion, 1); MemoryRegion *sdram = g_new(MemoryRegion, 2); const char *bios_name = machine->firmware ?: BIOS_FILENAME; - + cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); /* Allocate memory space */ diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 4f765b339b..01afcbd2b0 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -55,7 +55,7 @@ static void sh_timer_update(sh_timer_state *s) int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); if (new_level != s->old_level) - qemu_set_irq (s->irq, new_level); + qemu_set_irq(s->irq, new_level); s->old_level = s->int_level; s->int_level = new_level; @@ -113,11 +113,21 @@ static void sh_timer_write(void *opaque, hwaddr offset, freq = s->freq; /* ??? Need to recalculate expiry time after changing divisor. */ switch (value & TIMER_TCR_TPSC) { - case 0: freq >>= 2; break; - case 1: freq >>= 4; break; - case 2: freq >>= 6; break; - case 3: freq >>= 8; break; - case 4: freq >>= 10; break; + case 0: + freq >>= 2; + break; + case 1: + freq >>= 4; + break; + case 2: + freq >>= 6; + break; + case 3: + freq >>= 8; + break; + case 4: + freq >>= 10; + break; case 6: case 7: if (s->feat & TIMER_FEAT_EXTCLK) { diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 3d5ba598d0..366cedcda0 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -44,14 +44,14 @@ typedef struct { uint16_t portbmask_trigger; /* Return 0 if no action was taken */ int (*port_change_cb) (uint16_t porta, uint16_t portb, - uint16_t * periph_pdtra, - uint16_t * periph_portdira, - uint16_t * periph_pdtrb, - uint16_t * periph_portdirb); + uint16_t *periph_pdtra, + uint16_t *periph_portdira, + uint16_t *periph_pdtrb, + uint16_t *periph_portdirb); } sh7750_io_device; int sh7750_register_io_device(struct SH7750State *s, - sh7750_io_device * device); + sh7750_io_device *device); /* sh_serial.c */ #define SH_SERIAL_FEAT_SCIF (1 << 0) -- cgit v1.2.3-55-g7522 From beeb520925d54f5c69c66656a96dc68de0eec9a4 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/char/sh_serial: QOM-ify Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: <92902ba34fdf2c8c62232365fbb6531b1036d557.1635541329.git.balaton@eik.bme.hu> [PMD: Use g_strdup() to initialize DeviceState::id] Signed-off-by: Philippe Mathieu-Daudé --- hw/char/sh_serial.c | 98 ++++++++++++++++++++++++++++++++--------------------- hw/sh4/sh7750.c | 56 ++++++++++++++++++++++-------- include/hw/sh4/sh.h | 9 +---- 3 files changed, 101 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 80a548d19d..808d4ebae7 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -26,7 +26,11 @@ */ #include "qemu/osdep.h" +#include "hw/sysbus.h" #include "hw/irq.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "hw/sh4/sh.h" #include "chardev/char-fe.h" #include "qapi/error.h" @@ -42,10 +46,10 @@ #define SH_RX_FIFO_LENGTH (16) -typedef struct { - MemoryRegion iomem; - MemoryRegion iomem_p4; - MemoryRegion iomem_a7; +OBJECT_DECLARE_SIMPLE_TYPE(SHSerialState, SH_SERIAL) + +struct SHSerialState { + SysBusDevice parent; uint8_t smr; uint8_t brr; uint8_t scr; @@ -59,8 +63,7 @@ typedef struct { uint8_t rx_tail; uint8_t rx_head; - int freq; - int feat; + uint8_t feat; int flags; int rtrg; @@ -73,7 +76,11 @@ typedef struct { qemu_irq txi; qemu_irq tei; qemu_irq bri; -} SHSerialState; +}; + +typedef struct {} SHSerialStateClass; + +OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE) static void sh_serial_clear_fifo(SHSerialState *s) { @@ -381,8 +388,10 @@ static const MemoryRegionOps sh_serial_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void sh_serial_reset(SHSerialState *s) +static void sh_serial_reset(DeviceState *dev) { + SHSerialState *s = SH_SERIAL(dev); + s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; s->rtrg = 1; @@ -400,33 +409,21 @@ static void sh_serial_reset(SHSerialState *s) sh_serial_clear_fifo(s); } -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source) +static void sh_serial_realize(DeviceState *d, Error **errp) { - SHSerialState *s = g_malloc0(sizeof(*s)); - - s->feat = feat; - sh_serial_reset(s); - - memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s, - "serial", 0x100000000ULL); - - memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4); - - memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem, - 0, 0x28); - memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7); - - if (chr) { - qemu_chr_fe_init(&s->chr, chr, &error_abort); + SHSerialState *s = SH_SERIAL(d); + MemoryRegion *iomem = g_malloc(sizeof(*iomem)); + + assert(d->id); + memory_region_init_io(iomem, OBJECT(d), &sh_serial_ops, s, d->id, 0x28); + sysbus_init_mmio(SYS_BUS_DEVICE(d), iomem); + qdev_init_gpio_out_named(d, &s->eri, "eri", 1); + qdev_init_gpio_out_named(d, &s->rxi, "rxi", 1); + qdev_init_gpio_out_named(d, &s->txi, "txi", 1); + qdev_init_gpio_out_named(d, &s->tei, "tei", 1); + qdev_init_gpio_out_named(d, &s->bri, "bri", 1); + + if (qemu_chr_fe_backend_connected(&s->chr)) { qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1, sh_serial_receive1, sh_serial_event, NULL, s, NULL, true); @@ -435,9 +432,32 @@ void sh_serial_init(MemoryRegion *sysmem, timer_init_ns(&s->fifo_timeout_timer, QEMU_CLOCK_VIRTUAL, sh_serial_timeout_int, s); s->etu = NANOSECONDS_PER_SECOND / 9600; - s->eri = eri_source; - s->rxi = rxi_source; - s->txi = txi_source; - s->tei = tei_source; - s->bri = bri_source; +} + +static void sh_serial_finalize(Object *obj) +{ + SHSerialState *s = SH_SERIAL(obj); + + timer_del(&s->fifo_timeout_timer); +} + +static void sh_serial_init(Object *obj) +{ +} + +static Property sh_serial_properties[] = { + DEFINE_PROP_CHR("chardev", SHSerialState, chr), + DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void sh_serial_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + device_class_set_props(dc, sh_serial_properties); + dc->realize = sh_serial_realize; + dc->reset = sh_serial_reset; + /* Reason: part of SuperH CPU/SoC, needs to be wired up */ + dc->user_creatable = false; } diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 6c702d627c..f7d21f6170 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -24,9 +24,13 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/sysbus.h" #include "hw/irq.h" #include "hw/sh4/sh.h" #include "sysemu/sysemu.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "sh7750_regs.h" #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" @@ -762,6 +766,9 @@ static const MemoryRegionOps sh7750_mmct_ops = { SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) { SH7750State *s; + DeviceState *dev; + SysBusDevice *sb; + MemoryRegion *mr, *alias; s = g_malloc0(sizeof(SH7750State)); s->cpu = cpu; @@ -807,21 +814,40 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) cpu->env.intc_handle = &s->intc; - sh_serial_init(sysmem, 0x1fe00000, - 0, s->periph_freq, serial_hd(0), - s->intc.irqs[SCI1_ERI], - s->intc.irqs[SCI1_RXI], - s->intc.irqs[SCI1_TXI], - s->intc.irqs[SCI1_TEI], - NULL); - sh_serial_init(sysmem, 0x1fe80000, - SH_SERIAL_FEAT_SCIF, - s->periph_freq, serial_hd(1), - s->intc.irqs[SCIF_ERI], - s->intc.irqs[SCIF_RXI], - s->intc.irqs[SCIF_TXI], - NULL, - s->intc.irqs[SCIF_BRI]); + /* SCI */ + dev = qdev_new(TYPE_SH_SERIAL); + dev->id = g_strdup("sci"); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + sb = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sb, &error_fatal); + sysbus_mmio_map(sb, 0, 0xffe00000); + alias = g_malloc(sizeof(*alias)); + mr = sysbus_mmio_get_region(sb, 0); + memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias); + qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); + qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); + qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); + qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); + + /* SCIF */ + dev = qdev_new(TYPE_SH_SERIAL); + dev->id = g_strdup("scif"); + qdev_prop_set_chr(dev, "chardev", serial_hd(1)); + qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF); + sb = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(sb, &error_fatal); + sysbus_mmio_map(sb, 0, 0xffe80000); + alias = g_malloc(sizeof(*alias)); + mr = sysbus_mmio_get_region(sb, 0); + memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr, + 0, memory_region_size(mr)); + memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias); + qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); + qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); + qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); + qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); tmu012_init(sysmem, 0x1fd80000, TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, diff --git a/include/hw/sh4/sh.h b/include/hw/sh4/sh.h index 366cedcda0..ec716cdd45 100644 --- a/include/hw/sh4/sh.h +++ b/include/hw/sh4/sh.h @@ -54,15 +54,8 @@ int sh7750_register_io_device(struct SH7750State *s, sh7750_io_device *device); /* sh_serial.c */ +#define TYPE_SH_SERIAL "sh-serial" #define SH_SERIAL_FEAT_SCIF (1 << 0) -void sh_serial_init(MemoryRegion *sysmem, - hwaddr base, int feat, - uint32_t freq, Chardev *chr, - qemu_irq eri_source, - qemu_irq rxi_source, - qemu_irq txi_source, - qemu_irq tei_source, - qemu_irq bri_source); /* sh7750.c */ qemu_irq sh7750_irl(struct SH7750State *s); -- cgit v1.2.3-55-g7522 From 9b12fb10b731d8d9cbb6cc0bf200d1c48de7f20d Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Fri, 29 Oct 2021 23:02:09 +0200 Subject: hw/intc/sh_intc: Inline and drop sh_intc_source() function This function is very simple and provides no advantage. Call sites become simpler without it so just write it in line and drop the separate function. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/sh_intc.c | 54 ++++++++++++++++++++---------------------------- hw/sh4/sh7750.c | 4 ++-- include/hw/sh4/sh_intc.h | 2 +- 3 files changed, 25 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index e6e01428f9..9995213cb0 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -262,33 +262,22 @@ static const MemoryRegionOps sh_intc_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) -{ - if (id) { - return &desc->sources[id]; - } - return NULL; -} - static void sh_intc_register_source(struct intc_desc *desc, intc_enum source, struct intc_group *groups, int nr_groups) { unsigned int i, k; - struct intc_source *s; + intc_enum id; if (desc->mask_regs) { for (i = 0; i < desc->nr_mask_regs; i++) { struct intc_mask_reg *mr = &desc->mask_regs[i]; for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { - if (mr->enum_ids[k] != source) { - continue; - } - s = sh_intc_source(desc, mr->enum_ids[k]); - if (s) { - s->enable_max++; + id = mr->enum_ids[k]; + if (id && id == source) { + desc->sources[id].enable_max++; } } } @@ -299,12 +288,9 @@ static void sh_intc_register_source(struct intc_desc *desc, struct intc_prio_reg *pr = &desc->prio_regs[i]; for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { - if (pr->enum_ids[k] != source) { - continue; - } - s = sh_intc_source(desc, pr->enum_ids[k]); - if (s) { - s->enable_max++; + id = pr->enum_ids[k]; + if (id && id == source) { + desc->sources[id].enable_max++; } } } @@ -315,12 +301,9 @@ static void sh_intc_register_source(struct intc_desc *desc, struct intc_group *gr = &groups[i]; for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { - if (gr->enum_ids[k] != source) { - continue; - } - s = sh_intc_source(desc, gr->enum_ids[k]); - if (s) { - s->enable_max++; + id = gr->enum_ids[k]; + if (id && id == source) { + desc->sources[id].enable_max++; } } } @@ -335,14 +318,16 @@ void sh_intc_register_sources(struct intc_desc *desc, int nr_groups) { unsigned int i, k; + intc_enum id; struct intc_source *s; for (i = 0; i < nr_vectors; i++) { struct intc_vect *vect = &vectors[i]; sh_intc_register_source(desc, vect->enum_id, groups, nr_groups); - s = sh_intc_source(desc, vect->enum_id); - if (s) { + id = vect->enum_id; + if (id) { + s = &desc->sources[id]; s->vect = vect->vect; trace_sh_intc_register("source", vect->enum_id, s->vect, s->enable_count, s->enable_max); @@ -353,14 +338,16 @@ void sh_intc_register_sources(struct intc_desc *desc, for (i = 0; i < nr_groups; i++) { struct intc_group *gr = &groups[i]; - s = sh_intc_source(desc, gr->enum_id); + id = gr->enum_id; + s = &desc->sources[id]; s->next_enum_id = gr->enum_ids[0]; for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { if (!gr->enum_ids[k]) { continue; } - s = sh_intc_source(desc, gr->enum_ids[k - 1]); + id = gr->enum_ids[k - 1]; + s = &desc->sources[id]; s->next_enum_id = gr->enum_ids[k]; } trace_sh_intc_register("group", gr->enum_id, 0xffff, @@ -462,7 +449,10 @@ void sh_intc_set_irl(void *opaque, int n, int level) { struct intc_source *s = opaque; int i, irl = level ^ 15; - for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { + intc_enum id = s->next_enum_id; + + for (i = 0; id; id = s->next_enum_id, i++) { + s = &s->parent->sources[id]; if (i == irl) { sh_intc_toggle_source(s, s->enable_count ? 0 : 1, s->asserted ? 0 : 1); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index f7d21f6170..43dfb6497b 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -899,6 +899,6 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) qemu_irq sh7750_irl(SH7750State *s) { - sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ - return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0); + sh_intc_toggle_source(&s->intc.sources[IRL], 1, 0); /* enable */ + return qemu_allocate_irq(sh_intc_set_irl, &s->intc.sources[IRL], 0); } diff --git a/include/hw/sh4/sh_intc.h b/include/hw/sh4/sh_intc.h index 65f3425057..f62d5c5e13 100644 --- a/include/hw/sh4/sh_intc.h +++ b/include/hw/sh4/sh_intc.h @@ -58,7 +58,7 @@ struct intc_desc { }; int sh_intc_get_pending_vector(struct intc_desc *desc, int imask); -struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id); + void sh_intc_toggle_source(struct intc_source *source, int enable_adj, int assert_adj); -- cgit v1.2.3-55-g7522