From c59f781e3bcca4a80aef5d229488fd45dbfdbd9a Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Tue, 9 Mar 2021 12:01:28 +0100 Subject: hw/misc: Model KCS devices in the Aspeed LPC controller Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host. Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register. The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500. Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + include/hw/misc/aspeed_lpc.h | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 42c64bd28b..9359d6da33 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -132,6 +132,7 @@ enum { ASPEED_DEV_SDRAM, ASPEED_DEV_XDMA, ASPEED_DEV_EMMC, + ASPEED_DEV_KCS, }; #endif /* ASPEED_SOC_H */ diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h index 0fbb7f68be..df418cfcd3 100644 --- a/include/hw/misc/aspeed_lpc.h +++ b/include/hw/misc/aspeed_lpc.h @@ -12,10 +12,22 @@ #include "hw/sysbus.h" +#include + #define TYPE_ASPEED_LPC "aspeed.lpc" #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) -#define ASPEED_LPC_NR_REGS (0x260 >> 2) +#define ASPEED_LPC_NR_REGS (0x260 >> 2) + +enum aspeed_lpc_subdevice { + aspeed_lpc_kcs_1 = 0, + aspeed_lpc_kcs_2, + aspeed_lpc_kcs_3, + aspeed_lpc_kcs_4, + aspeed_lpc_ibt, +}; + +#define ASPEED_LPC_NR_SUBDEVS 5 typedef struct AspeedLPCState { /* */ @@ -25,6 +37,9 @@ typedef struct AspeedLPCState { MemoryRegion iomem; qemu_irq irq; + qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS]; + uint32_t subdevice_irqs_pending; + uint32_t regs[ASPEED_LPC_NR_REGS]; uint32_t hicr7; } AspeedLPCState; -- cgit v1.2.3-55-g7522