From dbcabeeb54e9101307cf6225b9311a3ceaab7d1a Mon Sep 17 00:00:00 2001 From: Cédric Le Goater Date: Mon, 17 Oct 2016 19:22:16 +0100 Subject: aspeed: extend the number of host SPI controllers The AST2500 SoC has two. Let's prepare ground for the next changes which will add the required definitions for the second host SPI controller. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell --- include/hw/arm/aspeed_soc.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 7359e25fce..f26a9f0439 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -20,6 +20,8 @@ #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" +#define ASPEED_SPIS_NUM 2 + typedef struct AspeedSoCState { /*< private >*/ DeviceState parent; @@ -32,7 +34,7 @@ typedef struct AspeedSoCState { AspeedI2CState i2c; AspeedSCUState scu; AspeedSMCState fmc; - AspeedSMCState spi; + AspeedSMCState spi[ASPEED_SPIS_NUM]; AspeedSDMCState sdmc; } AspeedSoCState; @@ -44,6 +46,8 @@ typedef struct AspeedSoCInfo { const char *cpu_model; uint32_t silicon_rev; hwaddr sdram_base; + int spis_num; + const hwaddr *spi_bases; } AspeedSoCInfo; typedef struct AspeedSoCClass { -- cgit v1.2.3-55-g7522