From 5d2eaa02501c9a75a221caa443553d3cc6077cfd Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 20:30:49 +0000 Subject: uninorth: move uninorth definitions into uninorth.h Signed-off-by: Mark Cave-Ayland [dwg: Added hw/hw.h #include as suggested by Philippe Mathieu-Daudé] Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- include/hw/pci-host/uninorth.h | 51 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/hw/pci-host/uninorth.h (limited to 'include') diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h new file mode 100644 index 0000000000..0366376a3b --- /dev/null +++ b/include/hw/pci-host/uninorth.h @@ -0,0 +1,51 @@ +/* + * QEMU Uninorth PCI host (for all Mac99 and newer machines) + * + * Copyright (c) 2006 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef UNINORTH_H +#define UNINORTH_H + +#include "hw/hw.h" + +#define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost" +#define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost" +#define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost" +#define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost" + +#define UNI_NORTH_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE) +#define UNI_NORTH_AGP_HOST_BRIDGE(obj) \ + OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE) +#define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \ + OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE) +#define U3_AGP_HOST_BRIDGE(obj) \ + OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE) + +typedef struct UNINState { + PCIHostState parent_obj; + + MemoryRegion pci_mmio; + MemoryRegion pci_hole; +} UNINState; + +#endif /* UNINORTH_H */ -- cgit v1.2.3-55-g7522 From a5ed75fe2e6625b2ab9ed0694d7a5c95a74b84f7 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 22:01:54 +0000 Subject: heathrow: remove obsolete heathow_init() function Instead wire up heathrow to the CPU and grackle PCI host using qdev GPIOs. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/intc/heathrow_pic.c | 23 +++++------------------ hw/ppc/mac.h | 4 ---- hw/ppc/mac_oldworld.c | 20 ++++++++++++-------- include/hw/intc/heathrow_pic.h | 2 +- 4 files changed, 18 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c index 393fdd7326..b8b997deca 100644 --- a/hw/intc/heathrow_pic.c +++ b/hw/intc/heathrow_pic.c @@ -172,27 +172,14 @@ static void heathrow_init(Object *obj) HeathrowState *s = HEATHROW(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s, - "heathrow-pic", 0x1000); - sysbus_init_mmio(sbd, &s->mem); -} - -DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs, - qemu_irq **pic_irqs) -{ - DeviceState *d; - HeathrowState *s; - - d = qdev_create(NULL, TYPE_HEATHROW); - qdev_init_nofail(d); - - s = HEATHROW(d); /* only 1 CPU */ - s->irqs = irqs[0]; + qdev_init_gpio_out(DEVICE(obj), s->irqs, 1); - *pic_irqs = qemu_allocate_irqs(heathrow_set_irq, s, HEATHROW_NUM_IRQS); + qdev_init_gpio_in(DEVICE(obj), heathrow_set_irq, HEATHROW_NUM_IRQS); - return d; + memory_region_init_io(&s->mem, OBJECT(s), &heathrow_ops, s, + "heathrow-pic", 0x1000); + sysbus_init_mmio(sbd, &s->mem); } static void heathrow_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index fcf13cb757..d661515e9d 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -77,10 +77,6 @@ void macio_ide_register_dma(MACIOIDEState *ide); void macio_init(PCIDevice *dev, MemoryRegion *pic_mem); -/* Heathrow PIC */ -DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs, - qemu_irq **pic_irqs); - /* Grackle PCI */ #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost" PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 10e291ca22..9bd4ece16d 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -84,7 +84,7 @@ static void ppc_heathrow_init(MachineState *machine) PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; - qemu_irq *pic, **heathrow_irqs; + qemu_irq *pic; int linux_boot, i; MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); @@ -227,16 +227,15 @@ static void ppc_heathrow_init(MachineState *machine) memory_region_add_subregion(sysmem, 0xfe000000, isa); /* XXX: we register only 1 output pin for heathrow PIC */ - heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); - heathrow_irqs[0] = - g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); + pic_dev = qdev_create(NULL, TYPE_HEATHROW); + qdev_init_nofail(pic_dev); + /* Connect the heathrow PIC outputs to the 6xx bus */ for (i = 0; i < smp_cpus; i++) { switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_6xx: - heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); - heathrow_irqs[i][0] = - ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; + qdev_connect_gpio_out(pic_dev, 0, + ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); break; default: error_report("Bus model not supported on OldWorld Mac machine"); @@ -244,6 +243,11 @@ static void ppc_heathrow_init(MachineState *machine) } } + pic = g_new0(qemu_irq, HEATHROW_NUM_IRQS); + for (i = 0; i < HEATHROW_NUM_IRQS; i++) { + pic[i] = qdev_get_gpio_in(pic_dev, i); + } + /* Timebase Frequency */ if (kvm_enabled()) { tbfreq = kvmppc_get_tbfreq(); @@ -256,7 +260,7 @@ static void ppc_heathrow_init(MachineState *machine) error_report("Only 6xx bus is supported on heathrow machine"); exit(1); } - pic_dev = heathrow_pic_init(1, heathrow_irqs, &pic); + pci_bus = pci_grackle_init(0xfec00000, pic, get_system_memory(), get_system_io()); diff --git a/include/hw/intc/heathrow_pic.h b/include/hw/intc/heathrow_pic.h index bc3ffaab87..56c2ef339f 100644 --- a/include/hw/intc/heathrow_pic.h +++ b/include/hw/intc/heathrow_pic.h @@ -41,7 +41,7 @@ typedef struct HeathrowState { MemoryRegion mem; HeathrowPICState pics[2]; - qemu_irq *irqs; + qemu_irq irqs[1]; } HeathrowState; #define HEATHROW_NUM_IRQS 64 -- cgit v1.2.3-55-g7522 From 20d2514ad88057b8ef400cc4f1484d9160a9781a Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 22:01:59 +0000 Subject: mac_oldworld: move wiring of macio IRQs to macio_oldworld_realize() Since the macio device has a link to the PIC device, we can now wire up the IRQs directly via qdev GPIOs rather than having to use an intermediate array. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/misc/macio/macio.c | 37 ++++++++++++++++++++++--------------- hw/ppc/mac_oldworld.c | 14 -------------- include/hw/misc/macio/macio.h | 1 - 3 files changed, 22 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index a0cefe5719..dac7bcd15e 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -152,10 +152,9 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) { MacIOState *s = MACIO(d); OldWorldMacIOState *os = OLDWORLD_MACIO(d); + DeviceState *pic_dev = DEVICE(os->pic); Error *err = NULL; SysBusDevice *sysbus_dev; - int i; - int cur_irq = 0; macio_common_realize(d, &err); if (err) { @@ -164,11 +163,14 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) } sysbus_dev = SYS_BUS_DEVICE(&s->cuda); - sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); + sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, + OLDWORLD_CUDA_IRQ)); sysbus_dev = SYS_BUS_DEVICE(&s->escc); - sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]); - sysbus_connect_irq(sysbus_dev, 1, os->irqs[cur_irq++]); + sysbus_connect_irq(sysbus_dev, 0, qdev_get_gpio_in(pic_dev, + OLDWORLD_ESCCB_IRQ)); + sysbus_connect_irq(sysbus_dev, 1, qdev_get_gpio_in(pic_dev, + OLDWORLD_ESCCA_IRQ)); object_property_set_bool(OBJECT(&os->nvram), true, "realized", &err); if (err) { @@ -186,15 +188,22 @@ static void macio_oldworld_realize(PCIDevice *d, Error **errp) sysbus_mmio_get_region(sysbus_dev, 0)); /* IDE buses */ - for (i = 0; i < ARRAY_SIZE(os->ide); i++) { - qemu_irq irq0 = os->irqs[cur_irq++]; - qemu_irq irq1 = os->irqs[cur_irq++]; + macio_realize_ide(s, &os->ide[0], + qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ), + qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ), + 0x16, &err); + if (err) { + error_propagate(errp, err); + return; + } - macio_realize_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4), &err); - if (err) { - error_propagate(errp, err); - return; - } + macio_realize_ide(s, &os->ide[1], + qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ), + qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ), + 0x1a, &err); + if (err) { + error_propagate(errp, err); + return; } } @@ -219,8 +228,6 @@ static void macio_oldworld_init(Object *obj) DeviceState *dev; int i; - qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs)); - object_property_add_link(obj, "pic", TYPE_HEATHROW, (Object **) &os->pic, qdev_prop_allow_set_link_before_realize, diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 2bbcefa076..4608bab014 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -281,20 +281,6 @@ static void ppc_heathrow_init(MachineState *machine) /* MacIO */ macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); dev = DEVICE(macio); - qdev_connect_gpio_out(dev, 0, - qdev_get_gpio_in(pic_dev, OLDWORLD_CUDA_IRQ)); - qdev_connect_gpio_out(dev, 1, - qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCB_IRQ)); - qdev_connect_gpio_out(dev, 2, - qdev_get_gpio_in(pic_dev, OLDWORLD_ESCCA_IRQ)); - qdev_connect_gpio_out(dev, 3, - qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_IRQ)); - qdev_connect_gpio_out(dev, 4, - qdev_get_gpio_in(pic_dev, OLDWORLD_IDE0_DMA_IRQ)); - qdev_connect_gpio_out(dev, 5, - qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_IRQ)); - qdev_connect_gpio_out(dev, 6, - qdev_get_gpio_in(pic_dev, OLDWORLD_IDE1_DMA_IRQ)); qdev_prop_set_uint64(dev, "frequency", tbfreq); object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", &error_abort); diff --git a/include/hw/misc/macio/macio.h b/include/hw/misc/macio/macio.h index 4528282b36..64a2584a77 100644 --- a/include/hw/misc/macio/macio.h +++ b/include/hw/misc/macio/macio.h @@ -56,7 +56,6 @@ typedef struct OldWorldMacIOState { /*< public >*/ HeathrowState *pic; - qemu_irq irqs[7]; MacIONVRAMState nvram; MACIOIDEState ide[2]; -- cgit v1.2.3-55-g7522 From 0b065209549fdd503fe109b09d78500bb05c9f7f Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 20:30:52 +0000 Subject: uninorth: introduce temporary pic_irqs device property This is in preparation for moving the PCI bus wiring inside the uninorth host bridge devices. In the future it will be possible to remove this once the PICs have been switched to use qdev GPIOs. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/pci-host/uninorth.c | 25 +++++++++++++++++++++++-- include/hw/pci-host/uninorth.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index 5b8fc3aa16..fc59698f06 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -188,6 +188,7 @@ UNINState *pci_pmac_init(qemu_irq *pic, /* Use values found on a real PowerMac */ /* Uninorth main bus */ dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); + qdev_prop_set_ptr(dev, "pic-irqs", pic); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); h = PCI_HOST_BRIDGE(s); @@ -199,7 +200,7 @@ UNINState *pci_pmac_init(qemu_irq *pic, h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - pic, + d->pic_irqs, &d->pci_mmio, address_space_io, PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); @@ -220,6 +221,7 @@ UNINState *pci_pmac_init(qemu_irq *pic, /* Uninorth AGP bus */ pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); + qdev_prop_set_ptr(dev, "pic-irqs", pic); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, 0xf0800000); @@ -251,6 +253,7 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic, /* Uninorth AGP bus */ dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); + qdev_prop_set_ptr(dev, "pic-irqs", pic); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); h = PCI_HOST_BRIDGE(dev); @@ -263,7 +266,7 @@ UNINState *pci_pmac_u3_init(qemu_irq *pic, h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - pic, + d->pic_irqs, &d->pci_mmio, address_space_io, PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); @@ -436,10 +439,16 @@ static const TypeInfo unin_internal_pci_host_info = { }, }; +static Property pci_unin_main_properties[] = { + DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_unin_main_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->props = pci_unin_main_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -451,10 +460,16 @@ static const TypeInfo pci_unin_main_info = { .class_init = pci_unin_main_class_init, }; +static Property pci_u3_agp_properties[] = { + DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_u3_agp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->props = pci_u3_agp_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -466,10 +481,16 @@ static const TypeInfo pci_u3_agp_info = { .class_init = pci_u3_agp_class_init, }; +static Property pci_unin_agp_class_properties[] = { + DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), + DEFINE_PROP_END_OF_LIST(), +}; + static void pci_unin_agp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->props = pci_unin_agp_class_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h index 0366376a3b..e4fa11c145 100644 --- a/include/hw/pci-host/uninorth.h +++ b/include/hw/pci-host/uninorth.h @@ -44,6 +44,7 @@ typedef struct UNINState { PCIHostState parent_obj; + void *pic_irqs; MemoryRegion pci_mmio; MemoryRegion pci_hole; } UNINState; -- cgit v1.2.3-55-g7522 From e7755cc1142db474bfa47247a92c59996af0502a Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 20:30:58 +0000 Subject: uninorth: use object link to pass OpenPIC object to uninorth Now that the OpenPIC is wired up via the board, we can now remove our temporary PIC qdev pointer property and replace it with an object link instead. Signed-off-by: Mark Cave-Ayland Signed-off-by: David Gibson --- hw/pci-host/uninorth.c | 73 +++++++++++++++++++++++++----------------- hw/ppc/mac_newworld.c | 12 ++++--- include/hw/pci-host/uninorth.h | 5 ++- 3 files changed, 55 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index ec6e529d66..e2278fd0f0 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -38,10 +38,10 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) static void pci_unin_set_irq(void *opaque, int irq_num, int level) { - qemu_irq *pic = opaque; + UNINState *s = opaque; trace_unin_set_irq(unin_irq_line[irq_num], level); - qemu_set_irq(pic[unin_irq_line[irq_num]], level); + qemu_set_irq(s->irqs[irq_num], level); } static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) @@ -109,6 +109,15 @@ static const MemoryRegionOps unin_data_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static void pci_unin_init_irqs(UNINState *s) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { + s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]); + } +} + static void pci_unin_main_realize(DeviceState *dev, Error **errp) { UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); @@ -116,12 +125,13 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp) h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - s->pic_irqs, + s, &s->pci_mmio, get_system_io(), PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); + pci_unin_init_irqs(s); /* DEC 21154 bridge */ #if 0 @@ -150,6 +160,11 @@ static void pci_unin_main_init(Object *obj) "unin-pci-hole", &s->pci_mmio, 0x80000000ULL, 0x10000000ULL); + object_property_add_link(obj, "pic", TYPE_OPENPIC, + (Object **) &s->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); sysbus_init_mmio(sbd, &s->pci_hole); @@ -162,12 +177,13 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp) h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - s->pic_irqs, + s, &s->pci_mmio, get_system_io(), PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); + pci_unin_init_irqs(s); } static void pci_u3_agp_init(Object *obj) @@ -189,6 +205,11 @@ static void pci_u3_agp_init(Object *obj) "unin-pci-hole", &s->pci_mmio, 0x80000000ULL, 0x70000000ULL); + object_property_add_link(obj, "pic", TYPE_OPENPIC, + (Object **) &s->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); sysbus_init_mmio(sbd, &s->pci_hole); @@ -201,16 +222,18 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp) h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - s->pic_irqs, + s, &s->pci_mmio, get_system_io(), PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); + pci_unin_init_irqs(s); } static void pci_unin_agp_init(Object *obj) { + UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -219,6 +242,12 @@ static void pci_unin_agp_init(Object *obj) obj, "unin-agp-conf-idx", 0x1000); memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, obj, "unin-agp-conf-data", 0x1000); + + object_property_add_link(obj, "pic", TYPE_OPENPIC, + (Object **) &s->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); } @@ -230,16 +259,18 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp) h->bus = pci_register_root_bus(dev, NULL, pci_unin_set_irq, pci_unin_map_irq, - s->pic_irqs, + s, &s->pci_mmio, get_system_io(), PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); + pci_unin_init_irqs(s); } static void pci_unin_internal_init(Object *obj) { + UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -248,6 +279,12 @@ static void pci_unin_internal_init(Object *obj) obj, "unin-pci-conf-idx", 0x1000); memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, obj, "unin-pci-conf-data", 0x1000); + + object_property_add_link(obj, "pic", TYPE_OPENPIC, + (Object **) &s->pic, + qdev_prop_allow_set_link_before_realize, + 0, NULL); + sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); } @@ -412,17 +449,11 @@ static const TypeInfo unin_internal_pci_host_info = { }, }; -static Property pci_unin_main_properties[] = { - DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), - DEFINE_PROP_END_OF_LIST(), -}; - static void pci_unin_main_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pci_unin_main_realize; - dc->props = pci_unin_main_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -434,17 +465,11 @@ static const TypeInfo pci_unin_main_info = { .class_init = pci_unin_main_class_init, }; -static Property pci_u3_agp_properties[] = { - DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), - DEFINE_PROP_END_OF_LIST(), -}; - static void pci_u3_agp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pci_u3_agp_realize; - dc->props = pci_u3_agp_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -456,17 +481,11 @@ static const TypeInfo pci_u3_agp_info = { .class_init = pci_u3_agp_class_init, }; -static Property pci_unin_agp_class_properties[] = { - DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), - DEFINE_PROP_END_OF_LIST(), -}; - static void pci_unin_agp_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pci_unin_agp_realize; - dc->props = pci_unin_agp_class_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } @@ -478,17 +497,11 @@ static const TypeInfo pci_unin_agp_info = { .class_init = pci_unin_agp_class_init, }; -static Property pci_unin_internal_class_properties[] = { - DEFINE_PROP_PTR("pic-irqs", UNINState, pic_irqs), - DEFINE_PROP_END_OF_LIST(), -}; - static void pci_unin_internal_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = pci_unin_internal_realize; - dc->props = pci_unin_internal_class_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 2360b24a12..e05aa26c3d 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -347,7 +347,8 @@ static void ppc_core99_init(MachineState *machine) /* 970 gets a U3 bus */ /* Uninorth AGP bus */ dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); - qdev_prop_set_ptr(dev, "pic-irqs", pic); + object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", + &error_abort); qdev_init_nofail(dev); uninorth_pci = U3_AGP_HOST_BRIDGE(dev); s = SYS_BUS_DEVICE(dev); @@ -362,7 +363,8 @@ static void ppc_core99_init(MachineState *machine) /* Use values found on a real PowerMac */ /* Uninorth AGP bus */ dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); - qdev_prop_set_ptr(dev, "pic-irqs", pic); + object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", + &error_abort); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, 0xf0800000); @@ -370,7 +372,8 @@ static void ppc_core99_init(MachineState *machine) /* Uninorth internal bus */ dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); - qdev_prop_set_ptr(dev, "pic-irqs", pic); + object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", + &error_abort); qdev_init_nofail(dev); s = SYS_BUS_DEVICE(dev); sysbus_mmio_map(s, 0, 0xf4800000); @@ -378,7 +381,8 @@ static void ppc_core99_init(MachineState *machine) /* Uninorth main bus */ dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); - qdev_prop_set_ptr(dev, "pic-irqs", pic); + object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", + &error_abort); qdev_init_nofail(dev); uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); s = SYS_BUS_DEVICE(dev); diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h index e4fa11c145..e048fd56e8 100644 --- a/include/hw/pci-host/uninorth.h +++ b/include/hw/pci-host/uninorth.h @@ -27,6 +27,8 @@ #include "hw/hw.h" +#include "hw/ppc/openpic.h" + #define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost" #define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost" #define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost" @@ -44,7 +46,8 @@ typedef struct UNINState { PCIHostState parent_obj; - void *pic_irqs; + OpenPICState *pic; + qemu_irq irqs[4]; MemoryRegion pci_mmio; MemoryRegion pci_hole; } UNINState; -- cgit v1.2.3-55-g7522 From e226efbb262468241c2c8828373a84ffd93992ac Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 20:30:59 +0000 Subject: uninorth: move PCI IO (ISA) memory region into the uninorth device Do this for both the uninorth main and uninorth u3 AGP buses, using the main PCI bus for each machine (this ensures the IO addresses still match those used by OpenBIOS). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/pci-host/uninorth.c | 14 ++++++++++---- hw/ppc/mac_newworld.c | 12 ++++++------ include/hw/pci-host/uninorth.h | 1 + 3 files changed, 17 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index e2278fd0f0..3a29a4410e 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -127,7 +127,7 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp) pci_unin_set_irq, pci_unin_map_irq, s, &s->pci_mmio, - get_system_io(), + &s->pci_io, PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci"); @@ -155,6 +155,8 @@ static void pci_unin_main_init(Object *obj) memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 0x100000000ULL); + memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, + "unin-pci-isa-mmio", 0x00800000); memory_region_init_alias(&s->pci_hole, OBJECT(s), "unin-pci-hole", &s->pci_mmio, @@ -168,6 +170,7 @@ static void pci_unin_main_init(Object *obj) sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); sysbus_init_mmio(sbd, &s->pci_hole); + sysbus_init_mmio(sbd, &s->pci_io); } static void pci_u3_agp_realize(DeviceState *dev, Error **errp) @@ -179,7 +182,7 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp) pci_unin_set_irq, pci_unin_map_irq, s, &s->pci_mmio, - get_system_io(), + &s->pci_io, PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp"); @@ -200,6 +203,8 @@ static void pci_u3_agp_init(Object *obj) memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio", 0x100000000ULL); + memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, + "unin-pci-isa-mmio", 0x00800000); memory_region_init_alias(&s->pci_hole, OBJECT(s), "unin-pci-hole", &s->pci_mmio, @@ -213,6 +218,7 @@ static void pci_u3_agp_init(Object *obj) sysbus_init_mmio(sbd, &h->conf_mem); sysbus_init_mmio(sbd, &h->data_mem); sysbus_init_mmio(sbd, &s->pci_hole); + sysbus_init_mmio(sbd, &s->pci_io); } static void pci_unin_agp_realize(DeviceState *dev, Error **errp) @@ -224,7 +230,7 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp) pci_unin_set_irq, pci_unin_map_irq, s, &s->pci_mmio, - get_system_io(), + &s->pci_io, PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp"); @@ -261,7 +267,7 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp) pci_unin_set_irq, pci_unin_map_irq, s, &s->pci_mmio, - get_system_io(), + &s->pci_io, PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS); pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci"); diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index e05aa26c3d..bd7ffdb0fb 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -145,7 +145,6 @@ static void ppc_core99_init(MachineState *machine) CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; - MemoryRegion *isa = g_new(MemoryRegion, 1); MemoryRegion *unin_memory = g_new(MemoryRegion, 1); int linux_boot, i, j, k; MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); @@ -273,11 +272,6 @@ static void ppc_core99_init(MachineState *machine) } } - /* Register 8 MB of ISA IO space */ - memory_region_init_alias(isa, NULL, "isa_mmio", - get_system_io(), 0, 0x00800000); - memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); - /* UniN init: XXX should be a real device */ memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); @@ -355,6 +349,9 @@ static void ppc_core99_init(MachineState *machine) /* PCI hole */ memory_region_add_subregion(get_system_memory(), 0x80000000ULL, sysbus_mmio_get_region(s, 2)); + /* Register 8 MB of ISA IO space */ + memory_region_add_subregion(get_system_memory(), 0xf2000000, + sysbus_mmio_get_region(s, 3)); sysbus_mmio_map(s, 0, 0xf0800000); sysbus_mmio_map(s, 1, 0xf0c00000); @@ -389,6 +386,9 @@ static void ppc_core99_init(MachineState *machine) /* PCI hole */ memory_region_add_subregion(get_system_memory(), 0x80000000ULL, sysbus_mmio_get_region(s, 2)); + /* Register 8 MB of ISA IO space */ + memory_region_add_subregion(get_system_memory(), 0xf2000000, + sysbus_mmio_get_region(s, 3)); sysbus_mmio_map(s, 0, 0xf2800000); sysbus_mmio_map(s, 1, 0xf2c00000); diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h index e048fd56e8..a953b5e9b1 100644 --- a/include/hw/pci-host/uninorth.h +++ b/include/hw/pci-host/uninorth.h @@ -50,6 +50,7 @@ typedef struct UNINState { qemu_irq irqs[4]; MemoryRegion pci_mmio; MemoryRegion pci_hole; + MemoryRegion pci_io; } UNINState; #endif /* UNINORTH_H */ -- cgit v1.2.3-55-g7522 From c90c393c2dca764bf2a062b3769ac0de32f5fe28 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Tue, 6 Mar 2018 20:31:00 +0000 Subject: uninorth: rename UNINState to UNINHostState The existing UNINState actually represents the PCI/AGP host bridge stage so rename it accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: David Gibson --- hw/pci-host/uninorth.c | 32 ++++++++++++++++---------------- hw/ppc/mac.h | 8 ++++---- hw/ppc/mac_newworld.c | 2 +- include/hw/pci-host/uninorth.h | 12 ++++++------ 4 files changed, 27 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index 3a29a4410e..fada0ffd5f 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -38,7 +38,7 @@ static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) static void pci_unin_set_irq(void *opaque, int irq_num, int level) { - UNINState *s = opaque; + UNINHostState *s = opaque; trace_unin_set_irq(unin_irq_line[irq_num], level); qemu_set_irq(s->irqs[irq_num], level); @@ -81,7 +81,7 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr) static void unin_data_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - UNINState *s = opaque; + UNINHostState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); trace_unin_data_write(addr, len, val); pci_data_write(phb->bus, @@ -92,7 +92,7 @@ static void unin_data_write(void *opaque, hwaddr addr, static uint64_t unin_data_read(void *opaque, hwaddr addr, unsigned len) { - UNINState *s = opaque; + UNINHostState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); uint32_t val; @@ -109,7 +109,7 @@ static const MemoryRegionOps unin_data_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static void pci_unin_init_irqs(UNINState *s) +static void pci_unin_init_irqs(UNINHostState *s) { int i; @@ -120,7 +120,7 @@ static void pci_unin_init_irqs(UNINState *s) static void pci_unin_main_realize(DeviceState *dev, Error **errp) { - UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); + UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev); PCIHostState *h = PCI_HOST_BRIDGE(dev); h->bus = pci_register_root_bus(dev, NULL, @@ -142,7 +142,7 @@ static void pci_unin_main_realize(DeviceState *dev, Error **errp) static void pci_unin_main_init(Object *obj) { - UNINState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); + UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -175,7 +175,7 @@ static void pci_unin_main_init(Object *obj) static void pci_u3_agp_realize(DeviceState *dev, Error **errp) { - UNINState *s = U3_AGP_HOST_BRIDGE(dev); + UNINHostState *s = U3_AGP_HOST_BRIDGE(dev); PCIHostState *h = PCI_HOST_BRIDGE(dev); h->bus = pci_register_root_bus(dev, NULL, @@ -191,7 +191,7 @@ static void pci_u3_agp_realize(DeviceState *dev, Error **errp) static void pci_u3_agp_init(Object *obj) { - UNINState *s = U3_AGP_HOST_BRIDGE(obj); + UNINHostState *s = U3_AGP_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -223,7 +223,7 @@ static void pci_u3_agp_init(Object *obj) static void pci_unin_agp_realize(DeviceState *dev, Error **errp) { - UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); + UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev); PCIHostState *h = PCI_HOST_BRIDGE(dev); h->bus = pci_register_root_bus(dev, NULL, @@ -239,7 +239,7 @@ static void pci_unin_agp_realize(DeviceState *dev, Error **errp) static void pci_unin_agp_init(Object *obj) { - UNINState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); + UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -260,7 +260,7 @@ static void pci_unin_agp_init(Object *obj) static void pci_unin_internal_realize(DeviceState *dev, Error **errp) { - UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); + UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev); PCIHostState *h = PCI_HOST_BRIDGE(dev); h->bus = pci_register_root_bus(dev, NULL, @@ -276,7 +276,7 @@ static void pci_unin_internal_realize(DeviceState *dev, Error **errp) static void pci_unin_internal_init(Object *obj) { - UNINState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); + UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); PCIHostState *h = PCI_HOST_BRIDGE(obj); @@ -466,7 +466,7 @@ static void pci_unin_main_class_init(ObjectClass *klass, void *data) static const TypeInfo pci_unin_main_info = { .name = TYPE_UNI_NORTH_PCI_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(UNINState), + .instance_size = sizeof(UNINHostState), .instance_init = pci_unin_main_init, .class_init = pci_unin_main_class_init, }; @@ -482,7 +482,7 @@ static void pci_u3_agp_class_init(ObjectClass *klass, void *data) static const TypeInfo pci_u3_agp_info = { .name = TYPE_U3_AGP_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(UNINState), + .instance_size = sizeof(UNINHostState), .instance_init = pci_u3_agp_init, .class_init = pci_u3_agp_class_init, }; @@ -498,7 +498,7 @@ static void pci_unin_agp_class_init(ObjectClass *klass, void *data) static const TypeInfo pci_unin_agp_info = { .name = TYPE_UNI_NORTH_AGP_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(UNINState), + .instance_size = sizeof(UNINHostState), .instance_init = pci_unin_agp_init, .class_init = pci_unin_agp_class_init, }; @@ -514,7 +514,7 @@ static void pci_unin_internal_class_init(ObjectClass *klass, void *data) static const TypeInfo pci_unin_internal_info = { .name = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(UNINState), + .instance_size = sizeof(UNINHostState), .instance_init = pci_unin_internal_init, .class_init = pci_unin_internal_class_init, }; diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h index 1ab2a3b354..892dd03789 100644 --- a/hw/ppc/mac.h +++ b/hw/ppc/mac.h @@ -89,10 +89,10 @@ void macio_init(PCIDevice *dev, #define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost" /* UniNorth PCI */ -UNINState *pci_pmac_init(qemu_irq *pic, - MemoryRegion *address_space_mem); -UNINState *pci_pmac_u3_init(qemu_irq *pic, - MemoryRegion *address_space_mem); +UNINHostState *pci_pmac_init(qemu_irq *pic, + MemoryRegion *address_space_mem); +UNINHostState *pci_pmac_u3_init(qemu_irq *pic, + MemoryRegion *address_space_mem); /* Mac NVRAM */ #define TYPE_MACIO_NVRAM "macio-nvram" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index bd7ffdb0fb..29bd3838bf 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -150,7 +150,7 @@ static void ppc_core99_init(MachineState *machine) MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); hwaddr kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; - UNINState *uninorth_pci; + UNINHostState *uninorth_pci; PCIBus *pci_bus; NewWorldMacIOState *macio; MACIOIDEState *macio_ide; diff --git a/include/hw/pci-host/uninorth.h b/include/hw/pci-host/uninorth.h index a953b5e9b1..f0e6836c76 100644 --- a/include/hw/pci-host/uninorth.h +++ b/include/hw/pci-host/uninorth.h @@ -35,15 +35,15 @@ #define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost" #define UNI_NORTH_PCI_HOST_BRIDGE(obj) \ - OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE) + OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE) #define UNI_NORTH_AGP_HOST_BRIDGE(obj) \ - OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE) + OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE) #define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \ - OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE) + OBJECT_CHECK(UNINHostState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE) #define U3_AGP_HOST_BRIDGE(obj) \ - OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE) + OBJECT_CHECK(UNINHostState, (obj), TYPE_U3_AGP_HOST_BRIDGE) -typedef struct UNINState { +typedef struct UNINHostState { PCIHostState parent_obj; OpenPICState *pic; @@ -51,6 +51,6 @@ typedef struct UNINState { MemoryRegion pci_mmio; MemoryRegion pci_hole; MemoryRegion pci_io; -} UNINState; +} UNINHostState; #endif /* UNINORTH_H */ -- cgit v1.2.3-55-g7522 From 8a4fd427fe8236bb4f6993702112f058b5d80507 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 29 Mar 2018 18:34:22 +1100 Subject: spapr: Introduce pseries-2.13 machine type Signed-off-by: David Gibson --- hw/ppc/spapr.c | 23 +++++++++++++++++++++-- include/hw/compat.h | 2 ++ 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 92194a9a53..b92dad2273 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3984,19 +3984,38 @@ static const TypeInfo spapr_machine_info = { } \ type_init(spapr_machine_register_##suffix) +/* + * pseries-2.13 + */ +static void spapr_machine_2_13_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_2_13_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(2_13, "2.13", true); + /* * pseries-2.12 */ +#define SPAPR_COMPAT_2_12 \ + HW_COMPAT_2_12 + static void spapr_machine_2_12_instance_options(MachineState *machine) { + spapr_machine_2_13_instance_options(machine); } static void spapr_machine_2_12_class_options(MachineClass *mc) { - /* Defaults for the latest behaviour inherited from the base class */ + spapr_machine_2_13_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12); } -DEFINE_SPAPR_MACHINE(2_12, "2.12", true); +DEFINE_SPAPR_MACHINE(2_12, "2.12", false); static void spapr_machine_2_12_sxxm_instance_options(MachineState *machine) { diff --git a/include/hw/compat.h b/include/hw/compat.h index 13242b831a..4681c2719a 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -1,6 +1,8 @@ #ifndef HW_COMPAT_H #define HW_COMPAT_H +#define HW_COMPAT_2_12 + #define HW_COMPAT_2_11 \ {\ .driver = "hpet",\ -- cgit v1.2.3-55-g7522 From 2b10808539d7ace3d9b1226a71a68e2431ef2176 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Tue, 3 Apr 2018 15:05:45 +1000 Subject: Add host_memory_backend_pagesize() helper There are a couple places (one generic, one target specific) where we need to get the host page size associated with a particular memory backend. I have some upcoming code which will add another place which wants this. So, for convenience, add a helper function to calculate this. host_memory_backend_pagesize() returns the host pagesize for a given HostMemoryBackend object. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Acked-by: Paolo Bonzini --- backends/hostmem.c | 18 ++++++++++++++++++ exec.c | 5 ++--- include/sysemu/hostmem.h | 2 ++ target/ppc/kvm.c | 6 +----- 4 files changed, 23 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/backends/hostmem.c b/backends/hostmem.c index f61093654e..6a0c474222 100644 --- a/backends/hostmem.c +++ b/backends/hostmem.c @@ -18,6 +18,7 @@ #include "qapi/visitor.h" #include "qemu/config-file.h" #include "qom/object_interfaces.h" +#include "qemu/mmap-alloc.h" #ifdef CONFIG_NUMA #include @@ -262,6 +263,23 @@ bool host_memory_backend_is_mapped(HostMemoryBackend *backend) return backend->is_mapped; } +#ifdef __linux__ +size_t host_memory_backend_pagesize(HostMemoryBackend *memdev) +{ + Object *obj = OBJECT(memdev); + char *path = object_property_get_str(obj, "mem-path", NULL); + size_t pagesize = qemu_mempath_getpagesize(path); + + g_free(path); + return pagesize; +} +#else +size_t host_memory_backend_pagesize(HostMemoryBackend *memdev) +{ + return getpagesize(); +} +#endif + static void host_memory_backend_memory_complete(UserCreatable *uc, Error **errp) { diff --git a/exec.c b/exec.c index b38b004563..c7fcefa851 100644 --- a/exec.c +++ b/exec.c @@ -1491,9 +1491,8 @@ static int find_max_supported_pagesize(Object *obj, void *opaque) long *hpsize_min = opaque; if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { - char *mem_path = object_property_get_str(obj, "mem-path", NULL); - long hpsize = qemu_mempath_getpagesize(mem_path); - g_free(mem_path); + long hpsize = host_memory_backend_pagesize(MEMORY_BACKEND(obj)); + if (hpsize < *hpsize_min) { *hpsize_min = hpsize; } diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h index 47bc9846ac..bc36899bb8 100644 --- a/include/sysemu/hostmem.h +++ b/include/sysemu/hostmem.h @@ -68,4 +68,6 @@ MemoryRegion *host_memory_backend_get_memory(HostMemoryBackend *backend, void host_memory_backend_set_mapped(HostMemoryBackend *backend, bool mapped); bool host_memory_backend_is_mapped(HostMemoryBackend *backend); +size_t host_memory_backend_pagesize(HostMemoryBackend *memdev); + #endif diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index e24fa50dc9..f62f7ac288 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -496,11 +496,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) bool kvmppc_is_mem_backend_page_size_ok(const char *obj_path) { Object *mem_obj = object_resolve_path(obj_path, NULL); - char *mempath = object_property_get_str(mem_obj, "mem-path", NULL); - long pagesize; - - pagesize = qemu_mempath_getpagesize(mempath); - g_free(mempath); + long pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(mem_obj)); return pagesize >= max_cpu_page_size; } -- cgit v1.2.3-55-g7522 From 644a2c99a90b95957fd56fc3b9f8908ac9e90702 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Thu, 22 Mar 2018 16:18:40 +1100 Subject: target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() As a rule we prefer to pass PowerPCCPU instead of CPUPPCState, and this change will make some things simpler later on. Signed-off-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: Cédric Le Goater --- hw/ppc/fdt.c | 5 +++-- hw/ppc/pnv.c | 4 ++-- hw/ppc/spapr.c | 4 ++-- include/hw/ppc/fdt.h | 2 +- 4 files changed, 8 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/hw/ppc/fdt.c b/hw/ppc/fdt.c index 2ffc5866e4..2721603ffa 100644 --- a/hw/ppc/fdt.c +++ b/hw/ppc/fdt.c @@ -13,9 +13,10 @@ #include "hw/ppc/fdt.h" #if defined(TARGET_PPC64) -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, - size_t maxsize) +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop, + size_t maxsize) { + CPUPPCState *env = &cpu->env; size_t maxcells = maxsize / sizeof(uint32_t); int i, j, count; uint32_t *p = prop; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 549cfccdcb..3220ef8f79 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -209,8 +209,8 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); } - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, - sizeof(page_sizes_prop)); + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, + sizeof(page_sizes_prop)); if (page_sizes_prop_size) { _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", page_sizes_prop, page_sizes_prop_size))); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index d35a88ca80..a4b3722656 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -581,8 +581,8 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); } - page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, - sizeof(page_sizes_prop)); + page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, + sizeof(page_sizes_prop)); if (page_sizes_prop_size) { _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", page_sizes_prop, page_sizes_prop_size))); diff --git a/include/hw/ppc/fdt.h b/include/hw/ppc/fdt.h index bd5b0a8c3d..a8cd85069f 100644 --- a/include/hw/ppc/fdt.h +++ b/include/hw/ppc/fdt.h @@ -23,7 +23,7 @@ } \ } while (0) -size_t ppc_create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, +size_t ppc_create_page_sizes_prop(PowerPCCPU *cpu, uint32_t *prop, size_t maxsize); #endif /* PPC_FDT_H */ -- cgit v1.2.3-55-g7522 From a324d6f166970f8f6a82c61ffd2356fbda81c8f4 Mon Sep 17 00:00:00 2001 From: Bharata B Rao Date: Thu, 19 Apr 2018 12:17:35 +0530 Subject: spapr: Support ibm,dynamic-memory-v2 property The new property ibm,dynamic-memory-v2 allows memory to be represented in a more compact manner in device tree. Signed-off-by: Bharata B Rao Signed-off-by: David Gibson --- docs/specs/ppc-spapr-hotplug.txt | 19 ++++ hw/ppc/spapr.c | 230 +++++++++++++++++++++++++++++++-------- include/hw/ppc/spapr_ovec.h | 1 + 3 files changed, 202 insertions(+), 48 deletions(-) (limited to 'include') diff --git a/docs/specs/ppc-spapr-hotplug.txt b/docs/specs/ppc-spapr-hotplug.txt index f57e2a09c6..cc7833108e 100644 --- a/docs/specs/ppc-spapr-hotplug.txt +++ b/docs/specs/ppc-spapr-hotplug.txt @@ -387,4 +387,23 @@ Each LMB list entry consists of the following elements: - A 32bit flags word. The bit at bit position 0x00000008 defines whether the LMB is assigned to the the partition as of boot time. +ibm,dynamic-memory-v2 + +This property describes the dynamically reconfigurable memory. This is +an alternate and newer way to describe dyanamically reconfigurable memory. +It is a property encoded array that has an integer N (the number of +LMB set entries) followed by N LMB set entries. There is an LMB set entry +for each sequential group of LMBs that share common attributes. + +Each LMB set entry consists of the following elements: + +- Number of sequential LMBs in the entry represented by a 32bit integer. +- Logical address of the first LMB in the set encoded as a 64bit integer. +- DRC index of the first LMB in the set. +- Associativity list index that is used as an index into + ibm,associativity-lookup-arrays property described earlier. This + is used to retrieve the right associativity list to be used for all + the LMBs in this set. +- A 32bit flags word that applies to all the LMBs in the set. + [1] http://thread.gmane.org/gmane.linux.ports.ppc.embedded/75350/focus=106867 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2203b6f46d..b35aff5d81 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -668,63 +668,137 @@ static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) return -1; } -/* - * Adds ibm,dynamic-reconfiguration-memory node. - * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation - * of this device tree node. - */ -static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) +struct sPAPRDrconfCellV2 { + uint32_t seq_lmbs; + uint64_t base_addr; + uint32_t drc_index; + uint32_t aa_index; + uint32_t flags; +} QEMU_PACKED; + +typedef struct DrconfCellQueue { + struct sPAPRDrconfCellV2 cell; + QSIMPLEQ_ENTRY(DrconfCellQueue) entry; +} DrconfCellQueue; + +static DrconfCellQueue * +spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, + uint32_t drc_index, uint32_t aa_index, + uint32_t flags) { - MachineState *machine = MACHINE(spapr); - int ret, i, offset; - uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; - uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; - uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; - uint32_t nr_lmbs = (spapr->hotplug_memory.base + - memory_region_size(&spapr->hotplug_memory.mr)) / - lmb_size; - uint32_t *int_buf, *cur_index, buf_len; - int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; - MemoryDeviceInfoList *dimms = NULL; + DrconfCellQueue *elem; - /* - * Don't create the node if there is no hotpluggable memory - */ - if (machine->ram_size == machine->maxram_size) { - return 0; - } + elem = g_malloc0(sizeof(*elem)); + elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); + elem->cell.base_addr = cpu_to_be64(base_addr); + elem->cell.drc_index = cpu_to_be32(drc_index); + elem->cell.aa_index = cpu_to_be32(aa_index); + elem->cell.flags = cpu_to_be32(flags); - /* - * Allocate enough buffer size to fit in ibm,dynamic-memory - * or ibm,associativity-lookup-arrays - */ - buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) - * sizeof(uint32_t); - cur_index = int_buf = g_malloc0(buf_len); + return elem; +} - offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); +/* ibm,dynamic-memory-v2 */ +static int spapr_populate_drmem_v2(sPAPRMachineState *spapr, void *fdt, + int offset, MemoryDeviceInfoList *dimms) +{ + uint8_t *int_buf, *cur_index, buf_len; + int ret; + uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; + uint64_t addr, cur_addr, size; + uint32_t nr_boot_lmbs = (spapr->hotplug_memory.base / lmb_size); + uint64_t mem_end = spapr->hotplug_memory.base + + memory_region_size(&spapr->hotplug_memory.mr); + uint32_t node, nr_entries = 0; + sPAPRDRConnector *drc; + DrconfCellQueue *elem, *next; + MemoryDeviceInfoList *info; + QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue + = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); + + /* Entry to cover RAM and the gap area */ + elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, + SPAPR_LMB_FLAGS_RESERVED | + SPAPR_LMB_FLAGS_DRC_INVALID); + QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); + nr_entries++; + + cur_addr = spapr->hotplug_memory.base; + for (info = dimms; info; info = info->next) { + PCDIMMDeviceInfo *di = info->value->u.dimm.data; + + addr = di->addr; + size = di->size; + node = di->node; + + /* Entry for hot-pluggable area */ + if (cur_addr < addr) { + drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); + g_assert(drc); + elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, + cur_addr, spapr_drc_index(drc), -1, 0); + QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); + nr_entries++; + } - ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, - sizeof(prop_lmb_size)); - if (ret < 0) { - goto out; + /* Entry for DIMM */ + drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); + g_assert(drc); + elem = spapr_get_drconf_cell(size / lmb_size, addr, + spapr_drc_index(drc), node, + SPAPR_LMB_FLAGS_ASSIGNED); + QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); + nr_entries++; + cur_addr = addr + size; } - ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); - if (ret < 0) { - goto out; + /* Entry for remaining hotpluggable area */ + if (cur_addr < mem_end) { + drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); + g_assert(drc); + elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, + cur_addr, spapr_drc_index(drc), -1, 0); + QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); + nr_entries++; } - ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); - if (ret < 0) { - goto out; + buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); + int_buf = cur_index = g_malloc0(buf_len); + *(uint32_t *)int_buf = cpu_to_be32(nr_entries); + cur_index += sizeof(nr_entries); + + QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { + memcpy(cur_index, &elem->cell, sizeof(elem->cell)); + cur_index += sizeof(elem->cell); + QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); + g_free(elem); } - if (hotplug_lmb_start) { - dimms = qmp_pc_dimm_device_list(); + ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); + g_free(int_buf); + if (ret < 0) { + return -1; } + return 0; +} + +/* ibm,dynamic-memory */ +static int spapr_populate_drmem_v1(sPAPRMachineState *spapr, void *fdt, + int offset, MemoryDeviceInfoList *dimms) +{ + int i, ret; + uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; + uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; + uint32_t nr_lmbs = (spapr->hotplug_memory.base + + memory_region_size(&spapr->hotplug_memory.mr)) / + lmb_size; + uint32_t *int_buf, *cur_index, buf_len; - /* ibm,dynamic-memory */ + /* + * Allocate enough buffer size to fit in ibm,dynamic-memory + */ + buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); + cur_index = int_buf = g_malloc0(buf_len); int_buf[0] = cpu_to_be32(nr_lmbs); cur_index++; for (i = 0; i < nr_lmbs; i++) { @@ -764,13 +838,71 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; } - qapi_free_MemoryDeviceInfoList(dimms); ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); + g_free(int_buf); if (ret < 0) { - goto out; + return -1; + } + return 0; +} + +/* + * Adds ibm,dynamic-reconfiguration-memory node. + * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation + * of this device tree node. + */ +static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) +{ + MachineState *machine = MACHINE(spapr); + int ret, i, offset; + uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; + uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; + uint32_t *int_buf, *cur_index, buf_len; + int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; + MemoryDeviceInfoList *dimms = NULL; + + /* + * Don't create the node if there is no hotpluggable memory + */ + if (machine->ram_size == machine->maxram_size) { + return 0; + } + + offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); + + ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, + sizeof(prop_lmb_size)); + if (ret < 0) { + return ret; + } + + ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); + if (ret < 0) { + return ret; + } + + ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); + if (ret < 0) { + return ret; + } + + /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ + dimms = qmp_pc_dimm_device_list(); + if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { + ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms); + } else { + ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms); + } + qapi_free_MemoryDeviceInfoList(dimms); + + if (ret < 0) { + return ret; } /* ibm,associativity-lookup-arrays */ + buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t); + cur_index = int_buf = g_malloc0(buf_len); + cur_index = int_buf; int_buf[0] = cpu_to_be32(nr_nodes); int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ @@ -787,8 +919,8 @@ static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) } ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, (cur_index - int_buf) * sizeof(uint32_t)); -out: g_free(int_buf); + return ret; } @@ -2491,6 +2623,9 @@ static void spapr_machine_init(MachineState *machine) spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); } + /* advertise support for ibm,dyamic-memory-v2 */ + spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); + /* init CPUs */ spapr_init_cpus(spapr); @@ -2918,7 +3053,6 @@ static void spapr_instance_init(Object *obj) " place of standard EPOW events when possible" " (required for memory hot-unplug support)", NULL); - ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, "Maximum permitted CPU compatibility mode", &error_fatal); diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index bf25e5d954..0f2d8d715d 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -51,6 +51,7 @@ typedef struct sPAPROptionVector sPAPROptionVector; #define OV5_FORM1_AFFINITY OV_BIT(5, 0) #define OV5_HP_EVT OV_BIT(6, 5) #define OV5_HPT_RESIZE OV_BIT(6, 7) +#define OV5_DRMEM_V2 OV_BIT(22, 0) #define OV5_XIVE_BOTH OV_BIT(23, 0) #define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */ -- cgit v1.2.3-55-g7522