From 11411489da890ae40c182be7fa745c647e8ce399 Mon Sep 17 00:00:00 2001 From: Sai Pavan Boddu Date: Mon, 24 Feb 2020 15:09:22 +0530 Subject: arm_gic: Mask the un-supported priority bits The GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by: Sai Pavan Boddu Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell [PMM: improved commit message] Signed-off-by: Peter Maydell --- include/hw/intc/arm_gic.h | 2 ++ include/hw/intc/arm_gic_common.h | 1 + 2 files changed, 3 insertions(+) (limited to 'include') diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index ed703a1720..303b9748cb 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -68,6 +68,8 @@ /* Number of SGI target-list bits */ #define GIC_TARGETLIST_BITS 8 +#define GIC_MAX_PRIORITY_BITS 8 +#define GIC_MIN_PRIORITY_BITS 4 #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index b5585fec45..6e0d6b8a88 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -96,6 +96,7 @@ typedef struct GICState { uint16_t priority_mask[GIC_NCPU_VCPU]; uint16_t running_priority[GIC_NCPU_VCPU]; uint16_t current_pending[GIC_NCPU_VCPU]; + uint32_t n_prio_bits; /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary point -- cgit v1.2.3-55-g7522