From f286f04c21aba0f751ede4f5c99228a09e40c90b Mon Sep 17 00:00:00 2001
From: Cédric Le Goater
Date: Tue, 19 Nov 2019 15:12:06 +0100
Subject: aspeed/smc: Add AST2600 timings registers

Each CS has its own Read Timing Compensation Register on newer SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-13-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/ssi/aspeed_smc.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 684d16e336..6fbbb238f1 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -40,6 +40,7 @@ typedef struct AspeedSMCController {
     uint8_t r_ce_ctrl;
     uint8_t r_ctrl0;
     uint8_t r_timings;
+    uint8_t nregs_timings;
     uint8_t conf_enable_w0;
     uint8_t max_slaves;
     const AspeedSegments *segments;
-- 
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