From 29a0af618ddd21f55df5753c3e16b0625f534b3c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 16:07:18 -0700 Subject: cpu: Replace ENV_GET_CPU with env_cpu Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell Acked-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/arm/cpu_loop.c | 2 +- linux-user/cpu_loop-common.h | 2 +- linux-user/cris/cpu_loop.c | 2 +- linux-user/elfload.c | 6 +++--- linux-user/m68k/cpu_loop.c | 2 +- linux-user/main.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- linux-user/nios2/cpu_loop.c | 2 +- linux-user/riscv/cpu_loop.c | 2 +- linux-user/signal.c | 8 ++++---- linux-user/syscall.c | 18 +++++++++--------- linux-user/uname.c | 2 +- 12 files changed, 25 insertions(+), 25 deletions(-) (limited to 'linux-user') diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index ee68aa60bf..b7e7a6323c 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -423,7 +423,7 @@ void cpu_loop(CPUARMState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; int i; diff --git a/linux-user/cpu_loop-common.h b/linux-user/cpu_loop-common.h index c1d554a249..8828af28a4 100644 --- a/linux-user/cpu_loop-common.h +++ b/linux-user/cpu_loop-common.h @@ -24,7 +24,7 @@ #define EXCP_DUMP(env, fmt, ...) \ do { \ - CPUState *cs = ENV_GET_CPU(env); \ + CPUState *cs = env_cpu(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ cpu_dump_state(cs, stderr, 0); \ if (qemu_log_separate()) { \ diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index af8c128bf8..7ec36cb0b5 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -83,7 +83,7 @@ void cpu_loop(CPUCRISState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5451d262ec..9fd65708c4 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -3377,7 +3377,7 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu = env_cpu((CPUArchState *)env); TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; @@ -3407,7 +3407,7 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + CPUState *cpu = env_cpu((CPUArchState *)env); TaskState *ts = (TaskState *)cpu->opaque; int i; @@ -3531,7 +3531,7 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const CPUState *cpu = env_cpu((CPUArchState *)env); const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index bfb41bbcc5..42d8d841ea 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -130,7 +130,7 @@ void cpu_loop(CPUM68KState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/main.c b/linux-user/main.c index 689bcf436d..97ca22bb04 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -180,7 +180,7 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); CPUState *new_cpu = cpu_create(cpu_type); CPUArchState *new_env = new_cpu->env_ptr; CPUBreakpoint *bp; diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 61dc90d51c..828137cd84 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -654,7 +654,7 @@ error: void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; int i; diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 5aa1eca740..9869083fa1 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUNios2State *env) { - CPUState *cs = ENV_GET_CPU(env); + CPUState *cs = env_cpu(env); Nios2CPU *cpu = NIOS2_CPU(cs); target_siginfo_t info; int trapnr, ret; diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index a9bac4ca79..31700f75d0 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -116,7 +116,7 @@ void cpu_loop(CPURISCVState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; struct image_info *info = ts->info; diff --git a/linux-user/signal.c b/linux-user/signal.c index 44b2d3b35a..7c5588adff 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -626,7 +626,7 @@ static void QEMU_NORETURN dump_core_and_abort(int target_sig) int queue_signal(CPUArchState *env, int sig, int si_type, target_siginfo_t *info) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; trace_user_queue_signal(env, sig); @@ -651,7 +651,7 @@ static void host_signal_handler(int host_signum, siginfo_t *info, void *puc) { CPUArchState *env = thread_cpu->env_ptr; - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); TaskState *ts = cpu->opaque; int sig; @@ -842,7 +842,7 @@ int do_sigaction(int sig, const struct target_sigaction *act, static void handle_pending_signal(CPUArchState *cpu_env, int sig, struct emulated_sigtable *k) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_ulong handler; sigset_t set; target_sigset_t target_old_set; @@ -927,7 +927,7 @@ static void handle_pending_signal(CPUArchState *cpu_env, int sig, void process_pending_signals(CPUArchState *cpu_env) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); int sig; TaskState *ts = cpu->opaque; sigset_t set; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5e29e675e9..d1a2c7831f 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -5484,7 +5484,7 @@ static void *clone_func(void *arg) rcu_register_thread(); tcg_register_thread(); env = info->env; - cpu = ENV_GET_CPU(env); + cpu = env_cpu(env); thread_cpu = cpu; ts = (TaskState *)cpu->opaque; info->tid = sys_gettid(); @@ -5514,7 +5514,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = env_cpu(env); int ret; TaskState *ts; CPUState *new_cpu; @@ -5547,7 +5547,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_cpu = ENV_GET_CPU(new_env); + new_cpu = env_cpu(new_env); new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; @@ -6654,7 +6654,7 @@ int host_to_target_waitstatus(int status) static int open_self_cmdline(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); struct linux_binprm *bprm = ((TaskState *)cpu->opaque)->bprm; int i; @@ -6671,7 +6671,7 @@ static int open_self_cmdline(void *cpu_env, int fd) static int open_self_maps(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; FILE *fp; char *line = NULL; @@ -6720,7 +6720,7 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -6757,7 +6757,7 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + CPUState *cpu = env_cpu((CPUArchState *)cpu_env); TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; @@ -7042,7 +7042,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; #if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \ || defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \ @@ -11706,7 +11706,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, abi_long arg5, abi_long arg6, abi_long arg7, abi_long arg8) { - CPUState *cpu = ENV_GET_CPU(cpu_env); + CPUState *cpu = env_cpu(cpu_env); abi_long ret; #ifdef DEBUG_ERESTARTSYS diff --git a/linux-user/uname.c b/linux-user/uname.c index 1c05f95387..a09ffe1ea7 100644 --- a/linux-user/uname.c +++ b/linux-user/uname.c @@ -54,7 +54,7 @@ const char *cpu_to_uname_machine(void *cpu_env) return "armv5te" utsname_suffix; #elif defined(TARGET_I386) && !defined(TARGET_X86_64) /* see arch/x86/kernel/cpu/bugs.c: check_bugs(), 386, 486, 586, 686 */ - CPUState *cpu = ENV_GET_CPU((CPUX86State *)cpu_env); + CPUState *cpu = env_cpu((CPUX86State *)cpu_env); int family = object_property_get_int(OBJECT(cpu), "family", NULL); if (family == 4) { return "i486"; -- cgit v1.2.3-55-g7522 From 1c7ad260009769eff0c2bbb030d5b50d0e794b6a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:26:58 -0700 Subject: target/alpha: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace alpha_env_get_cpu with env_archcpu. The combination CPU(alpha_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/alpha/cpu_loop.c | 2 +- target/alpha/cpu.h | 5 ----- target/alpha/helper.c | 8 +++----- target/alpha/sys_helper.c | 8 ++++---- 4 files changed, 8 insertions(+), 15 deletions(-) (limited to 'linux-user') diff --git a/linux-user/alpha/cpu_loop.c b/linux-user/alpha/cpu_loop.c index 61992571e1..7a94eee84c 100644 --- a/linux-user/alpha/cpu_loop.c +++ b/linux-user/alpha/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUAlphaState *env) { - CPUState *cs = CPU(alpha_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; target_siginfo_t info; abi_long sysret; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e391195be0..86d3e953b9 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -278,11 +278,6 @@ struct AlphaCPU { QEMUTimer *alarm_timer; }; -static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env) -{ - return container_of(env, AlphaCPU, env); -} - #define ENV_OFFSET offsetof(AlphaCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2134ee1e9d..93b8e788b1 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -136,7 +136,7 @@ static int get_physical_address(CPUAlphaState *env, target_ulong addr, int prot_need, int mmu_idx, target_ulong *pphys, int *pprot) { - CPUState *cs = CPU(alpha_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_long saddr = addr; target_ulong phys = 0; target_ulong L1pte, L2pte, L3pte; @@ -486,8 +486,7 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags) We expect that ENV->PC has already been updated. */ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) { - AlphaCPU *cpu = alpha_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); cs->exception_index = excp; env->error_code = error; @@ -498,8 +497,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error) void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr, int excp, int error) { - AlphaCPU *cpu = alpha_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); cs->exception_index = excp; env->error_code = error; diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index ac22323191..f9c34b1144 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -44,17 +44,17 @@ uint64_t helper_load_pcc(CPUAlphaState *env) #ifndef CONFIG_USER_ONLY void helper_tbia(CPUAlphaState *env) { - tlb_flush(CPU(alpha_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } void helper_tbis(CPUAlphaState *env, uint64_t p) { - tlb_flush_page(CPU(alpha_env_get_cpu(env)), p); + tlb_flush_page(env_cpu(env), p); } void helper_tb_flush(CPUAlphaState *env) { - tb_flush(CPU(alpha_env_get_cpu(env))); + tb_flush(env_cpu(env)); } void helper_halt(uint64_t restart) @@ -78,7 +78,7 @@ uint64_t helper_get_walltime(void) void helper_set_alarm(CPUAlphaState *env, uint64_t expire) { - AlphaCPU *cpu = alpha_env_get_cpu(env); + AlphaCPU *cpu = env_archcpu(env); if (expire) { env->alarm_expire = expire; -- cgit v1.2.3-55-g7522 From 2fc0cc0e1e034582f4718b1a2d57691474ccb6aa Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:41:14 -0700 Subject: target/arm: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace arm_env_get_cpu with env_archcpu. The combination CPU(arm_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 6 +-- linux-user/aarch64/signal.c | 4 +- linux-user/arm/cpu_loop.c | 2 +- linux-user/syscall.c | 8 +-- target/arm/arm-semi.c | 4 +- target/arm/cpu.h | 5 -- target/arm/cpu64.c | 2 +- target/arm/helper-a64.c | 4 +- target/arm/helper.c | 120 +++++++++++++++++++++--------------------- target/arm/op_helper.c | 21 ++++---- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- target/arm/vfp_helper.c | 2 +- 13 files changed, 88 insertions(+), 94 deletions(-) (limited to 'linux-user') diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2f2f63e3e8..18db6f80f0 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -73,7 +73,7 @@ /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; @@ -150,8 +150,8 @@ void cpu_loop(CPUARMState *env) void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); + ARMCPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; struct image_info *info = ts->info; int i; diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..cd521ee42d 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -314,7 +314,7 @@ static int target_restore_sigframe(CPUARMState *env, break; case TARGET_SVE_MAGIC: - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq = (env->vfp.zcr_el[1] & 0xf) + 1; sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); if (!sve && size == sve_size) { @@ -433,7 +433,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, &layout); /* SVE state needs saving only if it exists. */ - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(env))) { + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { vq = (env->vfp.zcr_el[1] & 0xf) + 1; sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(vq), 16); sve_ofs = alloc_sigframe_space(sve_size, &layout); diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index b7e7a6323c..ece4cf335e 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -206,7 +206,7 @@ do_kernel_trap(CPUARMState *env) void cpu_loop(CPUARMState *env) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; unsigned int n, insn; target_siginfo_t info; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index d1a2c7831f..ac3b5dc393 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9781,10 +9781,10 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, * even though the current architectural maximum is VQ=16. */ ret = -TARGET_EINVAL; - if (cpu_isar_feature(aa64_sve, arm_env_get_cpu(cpu_env)) + if (cpu_isar_feature(aa64_sve, env_archcpu(cpu_env)) && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { CPUARMState *env = cpu_env; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t vq, old_vq; old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; @@ -9801,7 +9801,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, case TARGET_PR_SVE_GET_VL: ret = -TARGET_EINVAL; { - ARMCPU *cpu = arm_env_get_cpu(cpu_env); + ARMCPU *cpu = env_archcpu(cpu_env); if (cpu_isar_feature(aa64_sve, cpu)) { ret = ((cpu->env.vfp.zcr_el[1] & 0xf) + 1) * 16; } @@ -9810,7 +9810,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, case TARGET_PR_PAC_RESET_KEYS: { CPUARMState *env = cpu_env; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (arg3 || arg4 || arg5) { return -TARGET_EINVAL; diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c index 53e807ab72..07af8d35da 100644 --- a/target/arm/arm-semi.c +++ b/target/arm/arm-semi.c @@ -257,8 +257,8 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb cb, */ target_ulong do_arm_semihosting(CPUARMState *env) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); + ARMCPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1afd1da491..c7df3816b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -913,11 +913,6 @@ struct ARMCPU { uint32_t sve_max_vq; }; -static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) -{ - return container_of(env, ARMCPU, env); -} - void arm_cpu_post_init(Object *obj); uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0ec8cd41f1..b8bd1e88a5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -43,7 +43,7 @@ static inline void unset_feature(CPUARMState *env, int feature) #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); /* Number of cores is in [25:24]; otherwise we RAZ */ return (cpu->core_count - 1) << 24; diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 796ef34b55..44e45a8037 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1005,7 +1005,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); if (!return_to_aa64) { @@ -1047,7 +1047,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); return; diff --git a/target/arm/helper.c b/target/arm/helper.c index f23989febf..188fb1950e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -227,7 +227,7 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, static int arm_gdb_get_sysreg(CPUARMState *env, uint8_t *buf, int reg) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); const ARMCPRegInfo *ri; uint32_t key; @@ -548,7 +548,7 @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); raw_write(env, ri, value); tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ @@ -556,7 +556,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (raw_read(env, ri) != value) { /* Unlike real hardware the qemu TLB uses virtual addresses, @@ -570,7 +570,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { @@ -631,7 +631,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate all (TLBIALL) */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (tlb_force_broadcast(env)) { tlbiall_is_write(env, NULL, value); @@ -645,7 +645,7 @@ static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (tlb_force_broadcast(env)) { tlbimva_is_write(env, NULL, value); @@ -659,7 +659,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate by ASID (TLBIASID) */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (tlb_force_broadcast(env)) { tlbiasid_is_write(env, NULL, value); @@ -673,7 +673,7 @@ static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (tlb_force_broadcast(env)) { tlbimvaa_is_write(env, NULL, value); @@ -1353,7 +1353,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) static void pmu_update_irq(CPUARMState *env) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } @@ -1408,7 +1408,7 @@ static void pmccntr_op_finish(CPUARMState *env) if (overflow_in > 0) { int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1457,7 +1457,7 @@ static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) if (overflow_in > 0) { int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + overflow_in; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); } #endif @@ -1865,7 +1865,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask = 0x3fff; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (arm_el_is_aa64(env, 3)) { value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1902,7 +1902,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); /* Acquire the CSSELR index from the bank corresponding to the CCSIDR * bank @@ -2452,7 +2452,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); timer_del(cpu->gt_timer[timeridx]); } @@ -2473,7 +2473,7 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, { trace_arm_gt_cval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval = value; - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2494,14 +2494,14 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, trace_arm_gt_tval_write(timeridx, value); env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + sextract64(value, 0, 32); - gt_recalc_timer(arm_env_get_cpu(env), timeridx); + gt_recalc_timer(env_archcpu(env), timeridx); } static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, int timeridx, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t oldval = env->cp15.c14_timer[timeridx].ctl; trace_arm_gt_ctl_write(timeridx, value); @@ -2579,7 +2579,7 @@ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); trace_arm_gt_cntvoff_write(value); raw_write(env, ri, value); @@ -3212,7 +3212,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri); if (!u32p) { @@ -3227,7 +3227,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t nrgs = cpu->pmsav7_dregion; if (value >= nrgs) { @@ -3355,7 +3355,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); TCR *tcr = raw_ptr(env, ri); if (arm_feature(env, ARM_FEATURE_LPAE)) { @@ -3384,7 +3384,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); TCR *tcr = raw_ptr(env, ri); /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */ @@ -3398,7 +3398,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ if (cpreg_field_is_64bit(ri) && extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); tlb_flush(CPU(cpu)); } raw_write(env, ri, value); @@ -3407,7 +3407,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); /* Accesses to VTTBR may change the VMID so we must flush the TLB. */ @@ -3497,7 +3497,7 @@ static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT); + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); } static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3650,7 +3650,7 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); unsigned int cur_el = arm_current_el(env); bool secure = arm_is_secure(env); @@ -3662,7 +3662,7 @@ static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t mpidr_read_val(CPUARMState *env) { - ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env)); + ARMCPU *cpu = env_archcpu(env); uint64_t mpidr = cpu->mp_affinity; if (arm_feature(env, ARM_FEATURE_V7MP)) { @@ -3815,7 +3815,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, * stage 2 translations, whereas most other scopes only invalidate * stage 1 translations. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); if (arm_is_secure_below_el3(env)) { @@ -3839,7 +3839,7 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2); @@ -3848,7 +3848,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3); @@ -3904,7 +3904,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); @@ -3918,7 +3918,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); @@ -3928,7 +3928,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); bool sec = arm_is_secure_below_el3(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); @@ -3952,7 +3952,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); uint64_t pageaddr = sextract64(value << 12, 0, 56); @@ -4001,7 +4001,7 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, * translation information. * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); uint64_t pageaddr; @@ -4044,7 +4044,7 @@ static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int dzp_bit = 1 << 4; /* DZP indicates whether DC ZVA access is allowed */ @@ -4079,7 +4079,7 @@ static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (raw_read(env, ri) == value) { /* Skip the TLB flush if nothing actually changed; Linux likes @@ -4571,7 +4571,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint64_t valid_mask = HCR_MASK; if (arm_feature(env, ARM_FEATURE_EL3)) { @@ -5238,7 +5238,7 @@ int sve_exception_el(CPUARMState *env, int el) */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t zcr_len = cpu->sve_max_vq - 1; if (el <= 1) { @@ -5406,7 +5406,7 @@ void hw_watchpoint_update_all(ARMCPU *cpu) static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int i = ri->crm; /* Bits [63:49] are hardwired to the value of bit [48]; that is, the @@ -5422,7 +5422,7 @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int i = ri->crm; raw_write(env, ri, value); @@ -5524,7 +5524,7 @@ void hw_breakpoint_update_all(ARMCPU *cpu) static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int i = ri->crm; raw_write(env, ri, value); @@ -5534,7 +5534,7 @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int i = ri->crm; /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only @@ -5630,7 +5630,7 @@ static void define_debug_regs(ARMCPU *cpu) */ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint64_t pfr1 = cpu->id_pfr1; if (env->gicv3state) { @@ -5641,7 +5641,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint64_t pfr0 = cpu->isar.id_aa64pfr0; if (env->gicv3state) { @@ -7421,14 +7421,14 @@ uint32_t HELPER(rbit)(uint32_t x) /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; @@ -7488,7 +7488,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) static void switch_mode(CPUARMState *env, int mode) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (mode != ARM_CPU_MODE_USR) { cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); @@ -7831,7 +7831,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) * PreserveFPState() pseudocode. * We may throw an exception if the stacking fails. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); @@ -10938,7 +10938,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int level = 1; uint32_t table; uint32_t desc; @@ -11059,7 +11059,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, ARMMMUFaultInfo *fi) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int level = 1; uint32_t table; uint32_t desc; @@ -11444,7 +11444,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); CPUState *cs = CPU(cpu); /* Read an LPAE long-descriptor translation table. */ ARMFaultType fault_type = ARMFault_Translation; @@ -11802,7 +11802,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int n; bool is_user = regime_is_user(env, mmu_idx); @@ -12006,7 +12006,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, * pseudocode SecurityCheck() function. * We assume the caller has zero-initialized *sattrs. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int r; bool idau_exempt = false, idau_ns = true, idau_nsc = true; int idau_region = IREGION_NOTVALID; @@ -12119,7 +12119,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, * We set is_subpage to true if the region hit doesn't cover the * entire TARGET_PAGE the address is within. */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); bool is_user = regime_is_user(env, mmu_idx); uint32_t secure = regime_is_secure(env, mmu_idx); int n; @@ -12899,7 +12899,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) limit = is_psp ? env->v7m.psplim[false] : env->v7m.msplim[false]; if (val < limit) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cpu_restore_state(cs, GETPC(), true); raise_exception(env, EXCP_STKOF, 0, 1); @@ -13180,7 +13180,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) * alignment faults or any memory attribute handling). */ - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint64_t blocklen = 4 << cpu->dcz_blocksize; uint64_t vaddr = vaddr_in & ~(blocklen - 1); @@ -13680,7 +13680,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, uint32_t flags = 0; if (is_a64(env)) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint64_t sctlr; *pc = env->pc; @@ -13853,7 +13853,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) uint64_t pmask; assert(vq >= 1 && vq <= ARM_MAX_VQ); - assert(vq <= arm_env_get_cpu(env)->sve_max_vq); + assert(vq <= env_archcpu(env)->sve_max_vq); /* Zap the high bits of the zregs. */ for (i = 0; i < 32; i++) { @@ -13879,7 +13879,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int old_len, new_len; bool old_a64, new_a64; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8ee15a4bd4..4db254876d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -31,7 +31,7 @@ static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t target_el) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -224,7 +224,7 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) * raising an exception if the limit is breached. */ if (newvalue < v7m_sp_limit(env)) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* * Stack limit exceptions are a rare case, so rather than syncing @@ -427,7 +427,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int target_el = check_wfx_trap(env, false); if (cpu_has_work(cs)) { @@ -462,8 +462,7 @@ void HELPER(wfe)(CPUARMState *env) void HELPER(yield)(CPUARMState *env) { - ARMCPU *cpu = arm_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the @@ -481,7 +480,7 @@ void HELPER(yield)(CPUARMState *env) */ void HELPER(exception_internal)(CPUARMState *env, uint32_t excp) { - CPUState *cs = CPU(arm_env_get_cpu(env)); + CPUState *cs = env_cpu(env); assert(excp_is_internal(excp)); cs->exception_index = excp; @@ -524,7 +523,7 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { qemu_mutex_lock_iothread(); - arm_call_pre_el_change_hook(arm_env_get_cpu(env)); + arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); @@ -537,7 +536,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) env->regs[15] &= (env->thumb ? ~1 : ~3); qemu_mutex_lock_iothread(); - arm_call_el_change_hook(arm_env_get_cpu(env)); + arm_call_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); } @@ -842,7 +841,7 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) void HELPER(pre_hvc)(CPUARMState *env) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int cur_el = arm_current_el(env); /* FIXME: Use actual secure state. */ bool secure = false; @@ -882,7 +881,7 @@ void HELPER(pre_hvc)(CPUARMState *env) void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); int cur_el = arm_current_el(env); bool secure = arm_is_secure(env); bool smd_flag = env->cp15.scr_el3 & SCR_SMD; @@ -1156,7 +1155,7 @@ static bool check_breakpoints(ARMCPU *cpu) void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); if (check_breakpoints(cpu)) { HELPER(exception_internal(env, EXCP_DEBUG)); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f5440e57dd..8a3bf204d3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14289,7 +14289,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; - ARMCPU *arm_cpu = arm_env_get_cpu(env); + ARMCPU *arm_cpu = env_archcpu(env); uint32_t tb_flags = dc->base.tb->flags; int bound, core_mmu_idx; diff --git a/target/arm/translate.c b/target/arm/translate.c index d240c1b714..d25e19ef11 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13408,7 +13408,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; - ARMCPU *cpu = arm_env_get_cpu(env); + ARMCPU *cpu = env_archcpu(env); uint32_t tb_flags = dc->base.tb->flags; uint32_t condexec, core_mmu_idx; diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 7a46d99148..d3e83b627b 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -101,7 +101,7 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { + if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { val &= ~FPCR_FZ16; } -- cgit v1.2.3-55-g7522 From dbefca236a464f942efae6319f68aa7663b20718 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:46:40 -0700 Subject: target/cris: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace cris_env_get_cpu with env_archcpu. The combination CPU(cris_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/cris/cpu_loop.c | 2 +- target/cris/cpu.h | 5 ----- target/cris/mmu.c | 3 +-- target/cris/op_helper.c | 10 +++------- target/cris/translate.c | 2 +- 5 files changed, 6 insertions(+), 16 deletions(-) (limited to 'linux-user') diff --git a/linux-user/cris/cpu_loop.c b/linux-user/cris/cpu_loop.c index 7ec36cb0b5..86e711108d 100644 --- a/linux-user/cris/cpu_loop.c +++ b/linux-user/cris/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUCRISState *env) { - CPUState *cs = CPU(cris_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, ret; target_siginfo_t info; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 0746d19f38..e9e4e39a40 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -183,11 +183,6 @@ struct CRISCPU { CPUCRISState env; }; -static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) -{ - return container_of(env, CRISCPU, env); -} - #define ENV_OFFSET offsetof(CRISCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/cris/mmu.c b/target/cris/mmu.c index 9cb73bbfec..2acbcfd1c7 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -288,7 +288,6 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) { - CRISCPU *cpu = cris_env_get_cpu(env); target_ulong vaddr; unsigned int idx; uint32_t lo, hi; @@ -312,7 +311,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) if (tlb_v && !tlb_g && (tlb_pid == pid)) { vaddr = tlb_vpn << TARGET_PAGE_BITS; D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr); - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index e4c6942922..6b1e7ae4a8 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -39,7 +39,7 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index) { - CPUState *cs = CPU(cris_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = index; cpu_loop_exit(cs); @@ -58,8 +58,7 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid) void helper_spc_write(CPUCRISState *env, uint32_t new_spc) { #if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu = cris_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); tlb_flush_page(cs, env->pregs[PR_SPC]); tlb_flush_page(cs, new_spc); @@ -72,9 +71,6 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc) void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) { -#if !defined(CONFIG_USER_ONLY) - CRISCPU *cpu = cris_env_get_cpu(env); -#endif uint32_t srs; srs = env->pregs[PR_SRS]; srs &= 3; @@ -112,7 +108,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg) D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", vaddr, tlb_v, env->pc); if (tlb_v) { - tlb_flush_page(CPU(cpu), vaddr); + tlb_flush_page(env_cpu(env), vaddr); } } } diff --git a/target/cris/translate.c b/target/cris/translate.c index 31b40a57f9..3429a3b768 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3097,7 +3097,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) * delayslot, like in real hw. */ pc_start = tb->pc & ~1; - dc->cpu = cris_env_get_cpu(env); + dc->cpu = env_archcpu(env); dc->tb = tb; dc->is_jmp = DISAS_NEXT; -- cgit v1.2.3-55-g7522 From 25f327081b4f63290cce0607512e4627cbfd408e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 17:51:33 -0700 Subject: target/hppa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace hppa_env_get_cpu with env_archcpu. The combination CPU(hppa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/hppa/cpu_loop.c | 2 +- target/hppa/cpu.h | 5 ----- target/hppa/helper.c | 3 +-- target/hppa/int_helper.c | 4 ++-- target/hppa/mem_helper.c | 10 ++++------ target/hppa/op_helper.c | 8 +++----- 6 files changed, 11 insertions(+), 21 deletions(-) (limited to 'linux-user') diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 880955fdef..9915456a1d 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -105,7 +105,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) void cpu_loop(CPUHPPAState *env) { - CPUState *cs = CPU(hppa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 0cb1fc8800..75e6a91a5e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -222,11 +222,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; -static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env) -{ - return container_of(env, HPPACPU, env); -} - #define ENV_OFFSET offsetof(HPPACPU, env) typedef CPUHPPAState CPUArchState; diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 11c61b3ca2..0dcd105b88 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -71,8 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) /* If PSW_P changes, it affects how we translate addresses. */ if ((psw ^ old_psw) & PSW_P) { #ifndef CONFIG_USER_ONLY - CPUState *src = CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); #endif } } diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 8d5edd3a20..89241c31e7 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -77,7 +77,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIRR] &= ~val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } @@ -85,7 +85,7 @@ void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) { env->cr[CR_EIEM] = val; qemu_mutex_lock_iothread(); - eval_interrupt(hppa_env_get_cpu(env)); + eval_interrupt(env_archcpu(env)); qemu_mutex_unlock_iothread(); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 0fd3ac6645..b12c5b5054 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -56,7 +56,7 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) { - CPUState *cs = CPU(hppa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned i, n = 1 << (2 * ent->page_size); uint64_t addr = ent->va_b; @@ -329,7 +329,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) { - CPUState *src = CPU(hppa_env_get_cpu(env)); + CPUState *src = env_cpu(env); CPUState *cpu; trace_hppa_tlb_ptlb(env); run_on_cpu_data data = RUN_ON_CPU_TARGET_PTR(addr); @@ -346,17 +346,15 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { - CPUState *src = CPU(hppa_env_get_cpu(env)); trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } void cpu_hppa_change_prot_id(CPUHPPAState *env) { if (env->psw & PSW_P) { - CPUState *src = CPU(hppa_env_get_cpu(env)); - tlb_flush_by_mmuidx(src, 0xf); + tlb_flush_by_mmuidx(env_cpu(env), 0xf); } } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 952e97a7d7..04d23c1b22 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -29,8 +29,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) { - HPPACPU *cpu = hppa_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); cs->exception_index = excp; cpu_loop_exit(cs); @@ -38,8 +37,7 @@ void QEMU_NORETURN HELPER(excp)(CPUHPPAState *env, int excp) void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra) { - HPPACPU *cpu = hppa_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); cs->exception_index = excp; cpu_loop_exit_restore(cs, ra); @@ -630,7 +628,7 @@ target_ureg HELPER(read_interval_timer)(void) #ifndef CONFIG_USER_ONLY void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) { - HPPACPU *cpu = hppa_env_get_cpu(env); + HPPACPU *cpu = env_archcpu(env); uint64_t current = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t timeout; -- cgit v1.2.3-55-g7522 From 6aa9e42f27331be34e06d4d66f92f2272868f96a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 18:08:48 -0700 Subject: target/i386: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace x86_env_get_cpu with env_archcpu. The combination CPU(x86_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- bsd-user/main.c | 3 +-- hw/i386/kvmvapic.c | 4 ++-- hw/i386/pc.c | 2 +- linux-user/i386/cpu_loop.c | 2 +- linux-user/i386/signal.c | 2 +- linux-user/vm86.c | 18 +++++++++--------- target/i386/bpt_helper.c | 4 ++-- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 5 ----- target/i386/excp_helper.c | 2 +- target/i386/fpu_helper.c | 2 +- target/i386/helper.c | 16 ++++++---------- target/i386/misc_helper.c | 24 +++++++++++------------- target/i386/seg_helper.c | 14 +++++++------- target/i386/smm_helper.c | 4 ++-- target/i386/svm_helper.c | 22 +++++++++++----------- 16 files changed, 58 insertions(+), 70 deletions(-) (limited to 'linux-user') diff --git a/bsd-user/main.c b/bsd-user/main.c index 6192e9d91e..53e1f42408 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -140,8 +140,7 @@ static void set_idt(int n, unsigned int dpl) void cpu_loop(CPUX86State *env) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); int trapnr; abi_ulong pc; //target_siginfo_t info; diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 70f6f26a94..fe5b12ef6e 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -152,7 +152,7 @@ static void update_guest_rom_state(VAPICROMState *s) static int find_real_tpr_addr(VAPICROMState *s, CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); hwaddr paddr; target_ulong addr; @@ -279,7 +279,7 @@ instruction_ok: static int update_rom_mapping(VAPICROMState *s, CPUX86State *env, target_ulong ip) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); hwaddr paddr; uint32_t rom_state_vaddr; uint32_t pos, patch, offset; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index edc240bcbf..1b08b56362 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -406,7 +406,7 @@ uint64_t cpu_get_tsc(CPUX86State *env) /* IRQ handling */ int cpu_get_pic_interrupt(CPUX86State *env) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); int intno; if (!kvm_irqchip_in_kernel()) { diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index 51cfa006c9..71da24384f 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -82,7 +82,7 @@ static void set_idt(int n, unsigned int dpl) void cpu_loop(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; abi_ulong pc; abi_ulong ret; diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c index fecb4c99c3..97a39204cc 100644 --- a/linux-user/i386/signal.c +++ b/linux-user/i386/signal.c @@ -198,7 +198,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); #ifndef TARGET_X86_64 uint16_t magic; diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 9c393df424..2fa7a89edc 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,7 @@ static inline unsigned int vm_getl(CPUX86State *env, void save_v86_state(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; @@ -132,7 +132,7 @@ static inline void return_to_32bit(CPUX86State *env, int retval) static inline int set_IF(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->v86flags |= VIF_MASK; @@ -145,7 +145,7 @@ static inline int set_IF(CPUX86State *env) static inline void clear_IF(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->v86flags &= ~VIF_MASK; @@ -163,7 +163,7 @@ static inline void clear_AC(CPUX86State *env) static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; set_flags(ts->v86flags, eflags, ts->v86mask); @@ -177,7 +177,7 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); @@ -191,7 +191,7 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env) static inline unsigned int get_vflags(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; unsigned int flags; @@ -208,7 +208,7 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -267,7 +267,7 @@ void handle_vm86_trap(CPUX86State *env, int trapno) void handle_vm86_fault(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; @@ -392,7 +392,7 @@ void handle_vm86_fault(CPUX86State *env) int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target/i386/bpt_helper.c b/target/i386/bpt_helper.c index b3efdc77ec..c3a8ea73c9 100644 --- a/target/i386/bpt_helper.c +++ b/target/i386/bpt_helper.c @@ -53,7 +53,7 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index) static int hw_breakpoint_insert(CPUX86State *env, int index) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong dr7 = env->dr[7]; target_ulong drN = env->dr[index]; int err = 0; @@ -97,7 +97,7 @@ static int hw_breakpoint_insert(CPUX86State *env, int index) static void hw_breakpoint_remove(CPUX86State *env, int index) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c1ab86d63e..a461d8d92c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4222,8 +4222,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + X86CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); uint32_t pkg_offset; uint32_t limit; uint32_t signature[3]; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 103fd709b0..709d88cfcf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1480,11 +1480,6 @@ struct X86CPU { int32_t hv_max_vps; }; -static inline X86CPU *x86_env_get_cpu(CPUX86State *env) -{ - return container_of(env, X86CPU, env); -} - #define ENV_OFFSET offsetof(X86CPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/i386/excp_helper.c b/target/i386/excp_helper.c index fa1ead6404..a9bca7c28b 100644 --- a/target/i386/excp_helper.c +++ b/target/i386/excp_helper.c @@ -90,7 +90,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno, int next_eip_addend, uintptr_t retaddr) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (!is_int) { cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno, diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index ea5a0c4861..005f1f68f8 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -1477,7 +1477,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm) env->pkru = 0; } if (env->pkru != old_pkru) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); tlb_flush(cs); } } diff --git a/target/i386/helper.c b/target/i386/helper.c index 96336055f3..ff3a60c7cf 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -622,7 +622,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); int pe_state; qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0); @@ -664,19 +664,16 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) the PDPT */ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) { - X86CPU *cpu = x86_env_get_cpu(env); - env->cr[3] = new_cr3; if (env->cr[0] & CR0_PG_MASK) { qemu_log_mask(CPU_LOG_MMU, "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) { - X86CPU *cpu = x86_env_get_cpu(env); uint32_t hflags; #if defined(DEBUG_MMU) @@ -685,7 +682,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } /* Clear bits we're going to recompute. */ @@ -977,8 +974,8 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, void cpu_report_tpr_access(CPUX86State *env, TPRAccess access) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + X86CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); if (kvm_enabled() || whpx_enabled()) { env->tpr_access_type = access; @@ -996,8 +993,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, target_ulong *base, unsigned int *limit, unsigned int *flags) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); SegmentCache *dt; target_ulong ptr; uint32_t e1, e2; diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 78f2020ef2..3eff6885f8 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -133,7 +133,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state); + val = cpu_get_apic_tpr(env_archcpu(env)->apic_state); } else { val = env->v_tpr; } @@ -158,7 +158,7 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { qemu_mutex_lock_iothread(); - cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0); + cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0); qemu_mutex_unlock_iothread(); } env->v_tpr = t0 & 0x0f; @@ -180,7 +180,7 @@ void helper_lmsw(CPUX86State *env, target_ulong t0) void helper_invlpg(CPUX86State *env, target_ulong addr) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC()); tlb_flush_page(CPU(cpu), addr); @@ -247,7 +247,7 @@ void helper_wrmsr(CPUX86State *env) env->sysenter_eip = val; break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val); + cpu_set_apic_base(env_archcpu(env)->apic_state, val); break; case MSR_EFER: { @@ -404,7 +404,7 @@ void helper_rdmsr(CPUX86State *env) val = env->sysenter_eip; break; case MSR_IA32_APICBASE: - val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state); + val = cpu_get_apic_base(env_archcpu(env)->apic_state); break; case MSR_EFER: val = env->efer; @@ -561,7 +561,7 @@ static void do_hlt(X86CPU *cpu) void helper_hlt(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC()); env->eip += next_eip_addend; @@ -580,8 +580,8 @@ void helper_monitor(CPUX86State *env, target_ulong ptr) void helper_mwait(CPUX86State *env, int next_eip_addend) { - CPUState *cs; - X86CPU *cpu; + CPUState *cs = env_cpu(env); + X86CPU *cpu = env_archcpu(env); if ((uint32_t)env->regs[R_ECX] != 0) { raise_exception_ra(env, EXCP0D_GPF, GETPC()); @@ -589,8 +589,6 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC()); env->eip += next_eip_addend; - cpu = x86_env_get_cpu(env); - cs = CPU(cpu); /* XXX: not complete but not completely erroneous */ if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) { do_pause(cpu); @@ -601,7 +599,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) void helper_pause(CPUX86State *env, int next_eip_addend) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC()); env->eip += next_eip_addend; @@ -611,7 +609,7 @@ void helper_pause(CPUX86State *env, int next_eip_addend) void helper_debug(CPUX86State *env) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_DEBUG; cpu_loop_exit(cs); @@ -631,7 +629,7 @@ uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx) void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if ((env->cr[4] & CR4_PKE_MASK) == 0) { raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC()); diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index 63e265cb38..87a627f9dc 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -137,7 +137,7 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl, uintptr_t retaddr) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); int type, index, shift; #if 0 @@ -830,7 +830,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); int index; #if 0 @@ -972,7 +972,7 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int, #if defined(CONFIG_USER_ONLY) void helper_syscall(CPUX86State *env, int next_eip_addend) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_SYSCALL; env->exception_next_eip = env->eip + next_eip_addend; @@ -1172,7 +1172,7 @@ static void do_interrupt_user(CPUX86State *env, int intno, int is_int, static void handle_even_inj(CPUX86State *env, int intno, int is_int, int error_code, int is_hw, int rm) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t event_inj = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.event_inj)); @@ -1312,7 +1312,7 @@ void x86_cpu_do_interrupt(CPUState *cs) void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) { - do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); + do_interrupt_all(env_archcpu(env), intno, 0, 0, 0, is_hw); } bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) @@ -1763,7 +1763,7 @@ void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, target_ulong ssp, old_ssp, offset, sp; LOG_PCALL("lcall %04x:" TARGET_FMT_lx " s=%d\n", new_cs, new_eip, shift); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) == 0) { raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC()); } @@ -2167,7 +2167,7 @@ static inline void helper_ret_protected(CPUX86State *env, int shift, } LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", new_cs, new_eip, shift, addend); - LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); + LOG_PCALL_STATE(env_cpu(env)); if ((new_cs & 0xfffc) == 0) { raise_exception_err_ra(env, EXCP0D_GPF, new_cs & 0xfffc, retaddr); } diff --git a/target/i386/smm_helper.c b/target/i386/smm_helper.c index c1c34a75db..eb5aa6eb3d 100644 --- a/target/i386/smm_helper.c +++ b/target/i386/smm_helper.c @@ -204,8 +204,8 @@ void do_smm_enter(X86CPU *cpu) void helper_rsm(CPUX86State *env) { - X86CPU *cpu = x86_env_get_cpu(env); - CPUState *cs = CPU(cpu); + X86CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 9fd22a883b..7b8105a1c3 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -84,7 +84,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, static inline void svm_save_seg(CPUX86State *env, hwaddr addr, const SegmentCache *sc) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector), sc->selector); @@ -99,7 +99,7 @@ static inline void svm_save_seg(CPUX86State *env, hwaddr addr, static inline void svm_load_seg(CPUX86State *env, hwaddr addr, SegmentCache *sc) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned int flags; sc->selector = x86_lduw_phys(cs, @@ -122,7 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong addr; uint64_t nested_ctl; uint32_t event_inj; @@ -314,7 +314,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->hflags2 |= HF2_GIF_MASK; if (int_ctl & V_IRQ_MASK) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->interrupt_request |= CPU_INTERRUPT_VIRQ; } @@ -379,7 +379,7 @@ void helper_vmmcall(CPUX86State *env) void helper_vmload(CPUX86State *env, int aflag) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC()); @@ -419,7 +419,7 @@ void helper_vmload(CPUX86State *env, int aflag) void helper_vmsave(CPUX86State *env, int aflag) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC()); @@ -482,7 +482,7 @@ void helper_skinit(CPUX86State *env) void helper_invlpga(CPUX86State *env, int aflag) { - X86CPU *cpu = x86_env_get_cpu(env); + X86CPU *cpu = env_archcpu(env); target_ulong addr; cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0, GETPC()); @@ -501,7 +501,7 @@ void helper_invlpga(CPUX86State *env, int aflag) void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint64_t param, uintptr_t retaddr) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (likely(!(env->hflags & HF_GUEST_MASK))) { return; @@ -583,7 +583,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, uint32_t next_eip_addend) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (env->intercept & (1ULL << (SVM_EXIT_IOIO - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ @@ -604,7 +604,7 @@ void helper_svm_check_io(CPUX86State *env, uint32_t port, uint32_t param, void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, uintptr_t retaddr) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cpu_restore_state(cs, retaddr, true); @@ -625,7 +625,7 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1) { - CPUState *cs = CPU(x86_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t int_ctl; if (env->hflags & HF_INHIBIT_IRQ_MASK) { -- cgit v1.2.3-55-g7522 From a8d92fd869c601f723b82d9736a2d78ae640b8a2 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 18:23:25 -0700 Subject: target/m68k: Use env_cpu Cleanup in the boilerplate that each target must define. The combination CPU(m68k_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Acked-by: Laurent Vivier Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/m68k-sim.c | 3 +-- linux-user/m68k/cpu_loop.c | 2 +- linux-user/m68k/target_cpu.h | 2 +- target/m68k/cpu.h | 5 ----- target/m68k/helper.c | 33 ++++++++++++--------------------- target/m68k/m68k-semi.c | 4 ++-- target/m68k/op_helper.c | 12 ++++++------ target/m68k/translate.c | 4 +--- 8 files changed, 24 insertions(+), 41 deletions(-) (limited to 'linux-user') diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index 34d332d8b1..9bc6ff3d3a 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -91,7 +91,6 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { - M68kCPU *cpu = m68k_env_get_cpu(env); uint32_t *args; args = (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -159,6 +158,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 42d8d841ea..f2c33057b3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUM68KState *env) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; unsigned int n; target_siginfo_t info; diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index 7a26f3c3fc..bc7446fbaf 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,7 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp) static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; ts->tp_value = newtls; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 2e53cde076..7f3fa8d141 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -163,11 +163,6 @@ struct M68kCPU { CPUM68KState env; }; -static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) -{ - return container_of(env, M68kCPU, env); -} - #define ENV_OFFSET offsetof(M68kCPU, env) void m68k_cpu_do_interrupt(CPUState *cpu); diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 6db93bdd81..31aacb51c6 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -168,8 +168,6 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu = m68k_env_get_cpu(env); - switch (reg) { case M68K_CR_CACR: env->cacr = val; @@ -186,7 +184,7 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(CPU(cpu), + cpu_abort(env_cpu(env), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); } @@ -194,8 +192,6 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { - M68kCPU *cpu = m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -248,14 +244,13 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) env->mmu.ttr[M68K_DTTR1] = val; return; } - cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", + cpu_abort(env_cpu(env), + "Unimplemented control register write 0x%x = 0x%x\n", reg, val); } uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) { - M68kCPU *cpu = m68k_env_get_cpu(env); - switch (reg) { /* MC680[1234]0 */ case M68K_CR_SFC: @@ -292,7 +287,7 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) case M68K_CR_DTT1: return env->mmu.ttr[M68K_DTTR1]; } - cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", + cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", reg); } @@ -388,8 +383,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer) uint32_t last_logical, last_physical; int32_t size; int last_attr = -1, attr = -1; - M68kCPU *cpu = m68k_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); MemTxResult txres; if (env->mmu.tcr & M68K_TCR_PAGE_8K) { @@ -630,8 +624,7 @@ static int get_physical_address(CPUM68KState *env, hwaddr *physical, int *prot, target_ulong address, int access_type, target_ulong *page_size) { - M68kCPU *cpu = m68k_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); uint32_t entry; uint32_t next; target_ulong page_mask; @@ -1175,7 +1168,7 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc) z = n; \ break; \ default: \ - cpu_abort(CPU(m68k_env_get_cpu(env)), "Bad CC_OP %d", op); \ + cpu_abort(env_cpu(env), "Bad CC_OP %d", op); \ } \ } while (0) @@ -1358,8 +1351,6 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc) #if defined(CONFIG_SOFTMMU) void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) { - M68kCPU *cpu = m68k_env_get_cpu(env); - CPUState *cs = CPU(cpu); hwaddr physical; int access_type; int prot; @@ -1384,7 +1375,7 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) if (ret == 0) { addr &= TARGET_PAGE_MASK; physical += addr & (page_size - 1); - tlb_set_page(cs, addr, physical, + tlb_set_page(env_cpu(env), addr, physical, prot, access_type & ACCESS_SUPER ? MMU_KERNEL_IDX : MMU_USER_IDX, page_size); } @@ -1392,18 +1383,18 @@ void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read) void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode) { - M68kCPU *cpu = m68k_env_get_cpu(env); + CPUState *cs = env_cpu(env); switch (opmode) { case 0: /* Flush page entry if not global */ case 1: /* Flush page entry */ - tlb_flush_page(CPU(cpu), addr); + tlb_flush_page(cs, addr); break; case 2: /* Flush all except global entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 3: /* Flush all entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; } } diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 1402145c8f..6716b93b5a 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -421,7 +421,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); TaskState *ts = cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { @@ -454,7 +454,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr); + cpu_abort(env_cpu(env), "Unsupported semihosting syscall %d\n", nr); result = 0; } failed: diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 3d1aa23a02..ebcfe3dfdd 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -196,7 +196,7 @@ static const char *m68k_exception_name(int index) static void cf_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t sp; uint32_t sr; uint32_t fmt; @@ -274,7 +274,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp, { if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) { /* all except 68000 */ - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); switch (format) { case 4: *sp -= 4; @@ -299,7 +299,7 @@ static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp, static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t sp; uint32_t retaddr; uint32_t vector; @@ -507,7 +507,7 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = tt; cpu_loop_exit_restore(cs, raddr); @@ -1037,7 +1037,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub) env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0; if (val < 0 || val > ub) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); @@ -1068,7 +1068,7 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub) env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb; if (env->cc_c) { - CPUState *cs = CPU(m68k_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* Recover PC and CC_OP for the beginning of the insn. */ cpu_restore_state(cs, GETPC(), true); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index f0534a4ba0..2ae537461f 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4777,14 +4777,12 @@ DISAS_INSN(wddata) DISAS_INSN(wdebug) { - M68kCPU *cpu = m68k_env_get_cpu(env); - if (IS_USER(s)) { gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - cpu_abort(CPU(cpu), "WDEBUG not implemented"); + cpu_abort(env_cpu(env), "WDEBUG not implemented"); } #endif -- cgit v1.2.3-55-g7522 From f5c7e93ad9880accbc6ecba3a77d7ac849c57eba Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 18:27:36 -0700 Subject: target/microblaze: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace mb_env_get_cpu with env_archcpu. The combination CPU(mb_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_mmu_index below the include of "exec/cpu-all.h", so that the definition of env_archcpu is available. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/microblaze/cpu_loop.c | 2 +- target/microblaze/cpu.h | 35 +++++++++++++++-------------------- target/microblaze/mmu.c | 5 ++--- target/microblaze/op_helper.c | 2 +- target/microblaze/translate.c | 2 +- 5 files changed, 20 insertions(+), 26 deletions(-) (limited to 'linux-user') diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 076bdb9a61..a6ea71401d 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUMBState *env) { - CPUState *cs = CPU(mb_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, ret; target_siginfo_t info; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 6e68e00e1f..8402cc81f6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -310,11 +310,6 @@ struct MicroBlazeCPU { CPUMBState env; }; -static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) -{ - return container_of(env, MicroBlazeCPU, env); -} - #define ENV_OFFSET offsetof(MicroBlazeCPU, env) void mb_cpu_do_interrupt(CPUState *cs); @@ -344,21 +339,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu = mb_env_get_cpu(env); - - /* Are we in nommu mode?. */ - if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->sregs[SR_MSR] & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -384,4 +364,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif +static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu = env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->sregs[SR_MSR] & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + #endif diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index fcf86b12d5..6763421ba2 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -34,7 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f) static void mmu_flush_idx(CPUMBState *env, unsigned int idx) { - CPUState *cs = CPU(mb_env_get_cpu(env)); + CPUState *cs = env_cpu(env); struct microblaze_mmu *mmu = &env->mmu; unsigned int tlb_size; uint32_t tlb_tag, end, t; @@ -228,7 +228,6 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { - MicroBlazeCPU *cpu = mb_env_get_cpu(env); uint64_t tmp64; unsigned int i; qemu_log_mask(CPU_LOG_MMU, @@ -269,7 +268,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) /* Changes to the zone protection reg flush the QEMU TLB. Fortunately, these are very uncommon. */ if (v != env->mmu.regs[rn]) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } env->mmu.regs[rn] = v; break; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index b5dbb90d05..18677ddfca 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -65,7 +65,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl) void helper_raise_exception(CPUMBState *env, uint32_t index) { - CPUState *cs = CPU(mb_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = index; cpu_loop_exit(cs); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 885fc44b51..9ce65f3bcf 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1604,7 +1604,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) { CPUMBState *env = cs->env_ptr; - MicroBlazeCPU *cpu = mb_env_get_cpu(env); + MicroBlazeCPU *cpu = env_archcpu(env); uint32_t pc_start; struct DisasContext ctx; struct DisasContext *dc = &ctx; -- cgit v1.2.3-55-g7522 From 5a7330b35cabc9e2fd3a8577b7004b63af8c57f3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 18:38:42 -0700 Subject: target/mips: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- hw/intc/mips_gic.c | 2 +- hw/mips/mips_int.c | 2 +- linux-user/mips/cpu_loop.c | 2 +- target/mips/cpu.h | 5 ----- target/mips/helper.c | 15 +++++---------- target/mips/op_helper.c | 25 +++++++++++-------------- target/mips/translate.c | 3 +-- target/mips/translate_init.inc.c | 4 +--- 8 files changed, 21 insertions(+), 37 deletions(-) (limited to 'linux-user') diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 15e6e40f9f..8f509493ea 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -44,7 +44,7 @@ static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin) GIC_VP_MASK_CMP_SHF; } if (kvm_enabled()) { - kvm_mips_set_ipi_interrupt(mips_env_get_cpu(gic->vps[vp].env), + kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env), pin + GIC_CPU_PIN_OFFSET, ored_level); } else { diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 5ddeb15848..f899f6ceb3 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -76,7 +76,7 @@ void cpu_mips_irq_init_cpu(MIPSCPU *cpu) qemu_irq *qi; int i; - qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8); + qi = qemu_allocate_irqs(cpu_mips_irq_request, env_archcpu(env), 8); for (i = 0; i < 8; i++) { env->irq[i] = qi[i]; } diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 828137cd84..ac6c6d1504 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -425,7 +425,7 @@ static int do_break(CPUMIPSState *env, target_siginfo_t *info, void cpu_loop(CPUMIPSState *env) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_siginfo_t info; int trapnr; abi_long ret; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e684572dda..cb09425476 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1071,11 +1071,6 @@ struct MIPSCPU { CPUMIPSState env; }; -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - #define ENV_OFFSET offsetof(MIPSCPU, env) void mips_cpu_list(void); diff --git a/target/mips/helper.c b/target/mips/helper.c index 68e44df4da..6e6a44292f 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -339,10 +339,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical, void cpu_mips_tlb_flush(CPUMIPSState *env) { - MIPSCPU *cpu = mips_env_get_cpu(env); - /* Flush qemu's TLB and discard all shadowed entries. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); env->tlb->tlb_in_use = env->tlb->nb_tlb; } @@ -404,7 +402,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled */ - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { @@ -449,7 +447,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, int rw, int tlb_error) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int exception = 0, error_code = 0; if (rw == MMU_INST_FETCH) { @@ -1394,8 +1392,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { - MIPSCPU *cpu = mips_env_get_cpu(env); - CPUState *cs; + CPUState *cs = env_cpu(env); r4k_tlb_t *tlb; target_ulong addr; target_ulong end; @@ -1421,7 +1418,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) /* 1k pages are not supported. */ mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); if (tlb->V0) { - cs = CPU(cpu); addr = tlb->VPN & ~mask; #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1435,7 +1431,6 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) } } if (tlb->V1) { - cs = CPU(cpu); addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); #if defined(TARGET_MIPS64) if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { @@ -1456,7 +1451,7 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, int error_code, uintptr_t pc) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", __func__, exception, error_code); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 39180275b5..9e2e02f858 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -350,7 +350,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env, int rw, uintptr_t retaddr) { hwaddr paddr; - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); paddr = cpu_mips_translate_address(env, address, rw); @@ -699,7 +699,7 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) return env; } - cs = CPU(mips_env_get_cpu(env)); + cs = env_cpu(env); vpe_idx = tc_idx / cs->nr_threads; *tc = tc_idx % cs->nr_threads; other_cs = qemu_get_cpu(vpe_idx); @@ -1298,7 +1298,7 @@ void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu = mips_env_get_cpu(env); + MIPSCPU *cpu = env_archcpu(env); env->active_tc.CP0_TCHalt = arg1 & 0x1; @@ -1314,7 +1314,7 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - MIPSCPU *other_cpu = mips_env_get_cpu(other); + MIPSCPU *other_cpu = env_archcpu(other); // TODO: Halt TC / Restart (if allocated+active) TC. @@ -1427,7 +1427,7 @@ void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->CP0_SegCtl0 = arg1 & CP0SC0_MASK; tlb_flush(cs); @@ -1435,7 +1435,7 @@ void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->CP0_SegCtl1 = arg1 & CP0SC1_MASK; tlb_flush(cs); @@ -1443,7 +1443,7 @@ void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->CP0_SegCtl2 = arg1 & CP0SC2_MASK; tlb_flush(cs); @@ -1666,7 +1666,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) /* If the ASID changes, flush qemu's TLB. */ if ((old & env->CP0_EntryHi_ASID_mask) != (val & env->CP0_EntryHi_ASID_mask)) { - tlb_flush(CPU(mips_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } @@ -1686,7 +1686,6 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { - MIPSCPU *cpu = mips_env_get_cpu(env); uint32_t val, old; old = env->CP0_Status; @@ -1706,7 +1705,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2485,8 +2484,6 @@ static void debug_pre_eret(CPUMIPSState *env) static void debug_post_eret(CPUMIPSState *env) { - MIPSCPU *cpu = mips_env_get_cpu(env); - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -2502,7 +2499,7 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; default: - cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); break; } } @@ -2633,7 +2630,7 @@ void helper_pmon(CPUMIPSState *env, int function) void helper_wait(CPUMIPSState *env) { - CPUState *cs = CPU(mips_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->halted = 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); diff --git a/target/mips/translate.c b/target/mips/translate.c index e37722dfff..a3cf976ab6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -30119,8 +30119,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address) void cpu_state_reset(CPUMIPSState *env) { - MIPSCPU *cpu = mips_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index 1c2d017d36..6d145a905a 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -871,8 +871,6 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { - MIPSCPU *cpu = mips_env_get_cpu(env); - env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { @@ -889,7 +887,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(CPU(cpu), "MMU type not supported\n"); + cpu_abort(env_cpu(env), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ -- cgit v1.2.3-55-g7522 From 5ee2b02e926ba12946c2ce3fc6ed9913e7c94859 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 18:48:56 -0700 Subject: target/openrisc: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace openrisc_env_get_cpu with env_archcpu. The combination CPU(openrisc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/openrisc/cpu_loop.c | 2 +- target/openrisc/cpu.h | 5 ----- target/openrisc/exception_helper.c | 5 ++--- target/openrisc/sys_helper.c | 8 ++++---- 4 files changed, 7 insertions(+), 13 deletions(-) (limited to 'linux-user') diff --git a/linux-user/openrisc/cpu_loop.c b/linux-user/openrisc/cpu_loop.c index f496e4b48a..4b8165b261 100644 --- a/linux-user/openrisc/cpu_loop.c +++ b/linux-user/openrisc/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUOpenRISCState *env) { - CPUState *cs = CPU(openrisc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 50f79d540b..9e46ac5266 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -317,11 +317,6 @@ typedef struct OpenRISCCPU { } OpenRISCCPU; -static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env) -{ - return container_of(env, OpenRISCCPU, env); -} - #define ENV_OFFSET offsetof(OpenRISCCPU, env) void cpu_openrisc_list(void); diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c index 0797cc9d38..d02a1cf0aa 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -25,15 +25,14 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); + OpenRISCCPU *cpu = env_archcpu(env); raise_exception(cpu, excp); } static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc) { - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_RANGE; cpu_loop_exit_restore(cs, pc); diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 05f66c455b..8f11cb8202 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -30,8 +30,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + OpenRISCCPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); target_ulong mr; int idx; @@ -194,8 +194,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, target_ulong spr) { #ifndef CONFIG_USER_ONLY - OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + OpenRISCCPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); int idx; switch (spr) { -- cgit v1.2.3-55-g7522 From db70b31144d28a40838f8916a7c02adcdf5d8dcd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:07:57 -0700 Subject: target/ppc: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace ppc_env_get_cpu with env_archcpu. The combination CPU(ppc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- hw/ppc/ppc.c | 18 +++---- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc_booke.c | 4 +- linux-user/ppc/cpu_loop.c | 2 +- target/ppc/cpu.h | 7 +-- target/ppc/excp_helper.c | 14 ++--- target/ppc/fpu_helper.c | 14 ++--- target/ppc/helper_regs.h | 4 +- target/ppc/kvm.c | 5 +- target/ppc/misc_helper.c | 22 +++----- target/ppc/mmu-hash64.c | 14 ++--- target/ppc/mmu_helper.c | 115 ++++++++++++++++------------------------ target/ppc/translate_init.inc.c | 85 +++++++++++++++-------------- 13 files changed, 134 insertions(+), 172 deletions(-) (limited to 'linux-user') diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index ad20584f26..debcdab993 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -385,7 +385,7 @@ void ppc40x_system_reset(PowerPCCPU *cpu) void store_40x_dbcr0(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); switch ((val >> 28) & 0x3) { case 0x0: @@ -785,7 +785,7 @@ target_ulong cpu_ppc_load_decr(CPUPPCState *env) target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); ppc_tb_t *tb_env = env->tb_env; uint64_t hdecr; @@ -923,7 +923,7 @@ static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); int nr_bits = 32; @@ -955,7 +955,7 @@ static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, @@ -980,7 +980,7 @@ static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) { CPUPPCState *env = opaque; - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_tb_t *tb_env = env->tb_env; tb_env->tb_freq = freq; @@ -1095,7 +1095,7 @@ const VMStateDescription vmstate_ppc_timebase = { /* Set up (once) timebase frequency (in Hz) */ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_tb_t *tb_env; tb_env = g_malloc0(sizeof(ppc_tb_t)); @@ -1165,7 +1165,7 @@ static void cpu_4xx_fit_cb (void *opaque) uint64_t now, next; env = opaque; - cpu = ppc_env_get_cpu(env); + cpu = env_archcpu(env); tb_env = env->tb_env; ppc40x_timer = tb_env->opaque; now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -1235,7 +1235,7 @@ static void cpu_4xx_pit_cb (void *opaque) ppc40x_timer_t *ppc40x_timer; env = opaque; - cpu = ppc_env_get_cpu(env); + cpu = env_archcpu(env); tb_env = env->tb_env; ppc40x_timer = tb_env->opaque; env->spr[SPR_40x_TSR] |= 1 << 27; @@ -1261,7 +1261,7 @@ static void cpu_4xx_wdt_cb (void *opaque) uint64_t now, next; env = opaque; - cpu = ppc_env_get_cpu(env); + cpu = env_archcpu(env); tb_env = env->tb_env; ppc40x_timer = tb_env->opaque; now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3ae7f6d4df..018dcca888 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -49,7 +49,7 @@ ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, uint32_t flags) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); ram_addr_t bdloc; int i, n; diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 4f11e00a17..323413e074 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -249,7 +249,7 @@ static void booke_wdt_cb(void *opaque) void store_booke_tsr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_tb_t *tb_env = env->tb_env; booke_timer_t *booke_timer = tb_env->opaque; @@ -277,7 +277,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val) void store_booke_tcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_tb_t *tb_env = env->tb_env; booke_timer_t *booke_timer = tb_env->opaque; diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index 801f5ace29..24dfdba854 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -67,7 +67,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) void cpu_loop(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_siginfo_t info; int trapnr; target_ulong ret; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ec92a8e7af..73ef868a7b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1203,11 +1203,6 @@ struct PowerPCCPU { int32_t mig_slb_nr; }; -static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) -{ - return container_of(env, PowerPCCPU, env); -} - #define ENV_OFFSET offsetof(PowerPCCPU, env) PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); @@ -2450,7 +2445,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) } } - cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); + cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id); return 0; } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index ec2c177091..50b004d00d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -49,7 +49,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) static void ppc_hw_interrupt(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = POWERPC_EXCP_NONE; env->error_code = 0; @@ -792,7 +792,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) static void ppc_hw_interrupt(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); bool async_deliver; /* External reset */ @@ -931,7 +931,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) * It generally means a discrepancy between the wakup conditions in the * processor has_work implementation and the logic in this function. */ - cpu_abort(CPU(ppc_env_get_cpu(env)), + cpu_abort(env_cpu(env), "Wakeup from PM state but interrupt Undelivered"); } } @@ -974,7 +974,7 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr) void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, uint32_t error_code, uintptr_t raddr) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = exception; env->error_code = error_code; @@ -1015,7 +1015,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val) uint32_t excp = hreg_store_msr(env, val, 0); if (excp != 0) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cpu_interrupt_exittb(cs); raise_exception(env, excp); } @@ -1026,7 +1026,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) { CPUState *cs; - cs = CPU(ppc_env_get_cpu(env)); + cs = env_cpu(env); cs->halted = 1; /* @@ -1043,7 +1043,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* MSR:POW cannot be set by any form of rfi */ msr &= ~(1ULL << MSR_POW); diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 0b7308f539..ffbd19afa1 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -271,7 +271,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc, env->fpscr |= FP_FX; /* We must update the target FPR before raising the exception */ if (fpscr_ve != 0) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = POWERPC_EXCP_PROGRAM; env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC; @@ -315,7 +315,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr) static inline void float_overflow_excp(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->fpscr |= 1 << FPSCR_OX; /* Update the floating-point exception summary */ @@ -335,7 +335,7 @@ static inline void float_overflow_excp(CPUPPCState *env) static inline void float_underflow_excp(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->fpscr |= 1 << FPSCR_UX; /* Update the floating-point exception summary */ @@ -352,7 +352,7 @@ static inline void float_underflow_excp(CPUPPCState *env) static inline void float_inexact_excp(CPUPPCState *env) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->fpscr |= 1 << FPSCR_FI; env->fpscr |= 1 << FPSCR_XX; @@ -442,7 +442,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit) void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int prev; prev = (env->fpscr >> bit) & 1; @@ -574,7 +574,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit) void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong prev, new; int i; @@ -612,7 +612,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask) static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int status = get_float_exception_flags(&env->fp_status); bool inexact_happened = false; diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index 922da76c6c..85dfe7687f 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -116,7 +116,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, { int excp; #if !defined(CONFIG_USER_ONLY) - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); #endif excp = 0; @@ -175,7 +175,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, #if !defined(CONFIG_USER_ONLY) static inline void check_tlb_flush(CPUPPCState *env, bool global) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* Handle global flushes first */ if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 3bf0a46c33..d4107dd70d 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1991,9 +1991,8 @@ static int kvmppc_get_dec_bits(void) } static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) - { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - CPUState *cs = CPU(cpu); +{ + CPUState *cs = env_cpu(env); if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 0a81e98ee9..49a8a02363 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -81,28 +81,24 @@ void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, void helper_store_sdr1(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - if (env->spr[SPR_SDR1] != val) { ppc_store_sdr1(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } #if defined(TARGET_PPC64) void helper_store_ptcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - if (env->spr[SPR_PTCR] != val) { ppc_store_ptcr(env, val); - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } void helper_store_pcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); env->spr[SPR_PCR] = value & pcc->pcr_mask; @@ -111,16 +107,12 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value) void helper_store_pidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - env->spr[SPR_BOOKS_PID] = val; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void helper_store_lpidr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - env->spr[SPR_LPIDR] = val; /* @@ -129,7 +121,7 @@ void helper_store_lpidr(CPUPPCState *env, target_ulong val) * potentially access and cache entries for the current LPID as * well. */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void helper_store_hid0_601(CPUPPCState *env, target_ulong val) @@ -151,12 +143,10 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val) void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - if (likely(env->pb[num] != value)) { env->pb[num] = value; /* Should be optimized */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 7899eb2918..da8966ccf5 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -96,7 +96,7 @@ void dump_slb(PowerPCCPU *cpu) void helper_slbia(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); int n; /* XXX: Warning: slbia never invalidates the first segment */ @@ -118,7 +118,7 @@ void helper_slbia(CPUPPCState *env) static void __helper_slbie(CPUPPCState *env, target_ulong addr, target_ulong global) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_slb_t *slb; slb = slb_lookup(cpu, addr); @@ -251,7 +251,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, @@ -261,7 +261,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); target_ulong rt = 0; if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { @@ -273,7 +273,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); target_ulong rt = 0; if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { @@ -285,7 +285,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); target_ulong rt = 0; if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { @@ -1163,7 +1163,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) void helper_store_lpcr(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc_store_lpcr(cpu, val); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index e3149e4d3f..261a8fe707 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -239,7 +239,6 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); ppc6xx_tlb_t *tlb; int nr, max; @@ -253,7 +252,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlb6[nr]; pte_invalidate(&tlb->pte0); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, @@ -261,7 +260,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env, int is_code, int match_epn) { #if !defined(FLUSH_ALL_TLBS) - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); ppc6xx_tlb_t *tlb; int way, nr; @@ -474,7 +473,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int type) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); hwaddr hash; target_ulong vsid; int ds, pr, target_page_bits; @@ -670,7 +669,6 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, /* Helpers specific to PowerPC 40x implementations */ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; int i; @@ -678,7 +676,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) tlb = &env->tlb.tlbe[i]; tlb->prot &= ~PAGE_VALID; } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, @@ -749,11 +747,10 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, void store_40x_sler(CPUPPCState *env, uint32_t val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - /* XXX: TO BE FIXED */ if (val != 0x00000000) { - cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n"); + cpu_abort(env_cpu(env), + "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] = val; } @@ -863,7 +860,6 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, static void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); int tlb_size; int i, j; ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -880,7 +876,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags, tlb += booke206_tlb_size(env, i); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, @@ -1275,7 +1271,7 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type) static void mmu6xx_dump_mmu(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; @@ -1347,13 +1343,13 @@ void dump_mmu(CPUPPCState *env) case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: case POWERPC_MMU_2_07: - dump_slb(ppc_env_get_cpu(env)); + dump_slb(env_archcpu(env)); break; case POWERPC_MMU_3_00: - if (ppc64_v3_radix(ppc_env_get_cpu(env))) { + if (ppc64_v3_radix(env_archcpu(env))) { /* TODO - Unsupported */ } else { - dump_slb(ppc_env_get_cpu(env)); + dump_slb(env_archcpu(env)); break; } #endif @@ -1419,7 +1415,6 @@ static int get_physical_address_wtlb( target_ulong eaddr, int rw, int access_type, int mmu_idx) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); int ret = -1; bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -1460,18 +1455,18 @@ static int get_physical_address_wtlb( break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret = check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(CPU(cpu), + cpu_abort(env_cpu(env), "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); + cpu_abort(env_cpu(env), "Unknown or invalid MMU model\n"); return -1; } @@ -1583,7 +1578,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address, static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, int mmu_idx) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); PowerPCCPU *cpu = POWERPC_CPU(cs); mmu_ctx_t ctx; int access_type; @@ -1815,7 +1810,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, target_ulong mask) { - CPUState *cs = CPU(ppc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong base, end, page; base = BATu & ~0x0001FFFF; @@ -1847,7 +1842,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); #endif dump_store_bat(env, 'I', 0, nr, value); @@ -1868,7 +1863,7 @@ void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->IBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1883,7 +1878,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); #endif dump_store_bat(env, 'D', 0, nr, value); @@ -1904,7 +1899,7 @@ void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong value) #if !defined(FLUSH_ALL_TLBS) do_invalidate_BAT(env, env->DBAT[0][nr], mask); #else - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); #endif } } @@ -1919,7 +1914,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value) { target_ulong mask; #if defined(FLUSH_ALL_TLBS) - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); int do_inval; #endif @@ -1953,7 +1948,7 @@ void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong value) } #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -1964,7 +1959,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) #if !defined(FLUSH_ALL_TLBS) target_ulong mask; #else - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); int do_inval; #endif @@ -1993,7 +1988,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) env->DBAT[1][nr] = value; #if defined(FLUSH_ALL_TLBS) if (do_inval) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } #endif } @@ -2003,12 +1998,10 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { env->tlb_need_flush = 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } else #endif /* defined(TARGET_PPC64) */ switch (env->mmu_model) { @@ -2021,14 +2014,14 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(env_cpu(env), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; case POWERPC_MMU_BOOKE206: booke206_flush_tlb(env, -1, 0); @@ -2036,11 +2029,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_32B: case POWERPC_MMU_601: env->tlb_need_flush = 0; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); break; default: /* XXX: TODO */ - cpu_abort(CPU(cpu), "Unknown MMU model %x\n", env->mmu_model); + cpu_abort(env_cpu(env), "Unknown MMU model %x\n", env->mmu_model); break; } } @@ -2091,7 +2084,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) /* Special registers manipulation */ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value); assert(!cpu->vhyp); #if defined(TARGET_PPC64) @@ -2118,7 +2111,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value) #if defined(TARGET_PPC64) void ppc_store_ptcr(CPUPPCState *env, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS; target_ulong patbsize = value & PTCR_PATS; @@ -2163,7 +2156,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) (int)srnum, value, env->sr[srnum]); #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); + PowerPCCPU *cpu = env_archcpu(env); uint64_t esid, vsid; /* ESID = srnum */ @@ -2190,7 +2183,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value) page = (16 << 20) * srnum; end = page + (16 << 20); for (; page != end; page += TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), page); + tlb_flush_page(env_cpu(env), page); } } #else @@ -2212,12 +2205,10 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr) void helper_tlbiva(CPUPPCState *env, target_ulong addr) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - /* tlbiva instruction only exists on BookE */ assert(env->mmu_model == POWERPC_MMU_BOOKE); /* XXX: TODO */ - cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); + cpu_abort(env_cpu(env), "BookE MMU model is not implemented\n"); } /* Software driven TLBs management */ @@ -2433,8 +2424,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2529,7 +2519,6 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, target_ulong value) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; int do_flush_tlbs; @@ -2565,13 +2554,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, } tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF; if (do_flush_tlbs) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } break; case 1: RPN = value & 0xFFFFFC0F; if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } tlb->RPN = RPN; break; @@ -2665,7 +2654,6 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address) static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg = 0; int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT; int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2675,7 +2663,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb]; if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(CPU(cpu), "we don't support HES yet\n"); + cpu_abort(env_cpu(env), "we don't support HES yet\n"); } return booke206_get_tlbm(env, tlb, ea, esel); @@ -2683,40 +2671,33 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - env->spr[pidn] = pid; /* changing PIDs mean we're in a different address space now */ - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void helper_booke_set_eplc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPLC] = val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_LOAD); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_LOAD); } void helper_booke_set_epsc(CPUPPCState *env, target_ulong val) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); env->spr[SPR_BOOKE_EPSC] = val & EPID_MASK; - tlb_flush_by_mmuidx(CPU(cpu), 1 << PPC_TLB_EPID_STORE); + tlb_flush_by_mmuidx(env_cpu(env), 1 << PPC_TLB_EPID_STORE); } static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); - if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) { - tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK); + tlb_flush_page(env_cpu(env), tlb->mas2 & MAS2_EPN_MASK); } else { - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } void helper_booke206_tlbwe(CPUPPCState *env) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2770,7 +2751,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (msr_gs) { - cpu_abort(CPU(cpu), "missing HV implementation\n"); + cpu_abort(env_cpu(env), "missing HV implementation\n"); } if (tlb->mas1 & MAS1_VALID) { @@ -2968,7 +2949,6 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address) void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); ppcmas_tlb_t *tlb = env->tlb.tlbm; @@ -2985,12 +2965,11 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) } tlb += booke206_tlb_size(env, i); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); int i, j; ppcmas_tlb_t *tlb; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -3026,7 +3005,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb->mas1 &= ~MAS1_VALID; } } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type) diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index ad5e14b16f..d161e95fb2 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -3432,7 +3432,7 @@ static void init_proc_401(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3486,7 +3486,7 @@ static void init_proc_401x2(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3538,7 +3538,7 @@ static void init_proc_401x3(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3597,7 +3597,7 @@ static void init_proc_IOP480(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3648,7 +3648,7 @@ static void init_proc_403(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3714,7 +3714,7 @@ static void init_proc_403GCX(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3780,7 +3780,7 @@ static void init_proc_405(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(8, 12, 16, 20); SET_WDT_PERIOD(16, 20, 24, 28); @@ -3878,7 +3878,7 @@ static void init_proc_440EP(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size = 32; env->icache_line_size = 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4186,7 +4186,7 @@ static void init_proc_440x5(CPUPPCState *env) init_excp_BookE(env); env->dcache_line_size = 32; env->icache_line_size = 32; - ppc40x_irq_init(ppc_env_get_cpu(env)); + ppc40x_irq_init(env_archcpu(env)); SET_FIT_PERIOD(12, 16, 20, 24); SET_WDT_PERIOD(20, 24, 28, 32); @@ -4392,7 +4392,7 @@ static void init_proc_G2(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) @@ -4472,7 +4472,7 @@ static void init_proc_G2LE(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) @@ -4727,7 +4727,7 @@ static void init_proc_e300(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) @@ -4805,7 +4805,6 @@ enum fsl_e500_version { static void init_proc_e500(CPUPPCState *env, int version) { - PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask = 0xFFFF0000ULL; @@ -4877,7 +4876,7 @@ static void init_proc_e500(CPUPPCState *env, int version) tlbncfg[1] = 0x40028040; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } #endif @@ -4902,7 +4901,7 @@ static void init_proc_e500(CPUPPCState *env, int version) l1cfg1 |= 0x0B83820; break; default: - cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", + cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); @@ -5018,7 +5017,7 @@ static void init_proc_e500(CPUPPCState *env, int version) init_excp_e200(env, ivpr_mask); /* Allocate hardware IRQ controller */ - ppce500_irq_init(ppc_env_get_cpu(env)); + ppce500_irq_init(env_archcpu(env)); } static void init_proc_e500v1(CPUPPCState *env) @@ -5291,7 +5290,7 @@ static void init_proc_601(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 64; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(601)(ObjectClass *oc, void *data) @@ -5396,7 +5395,7 @@ static void init_proc_602(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(602)(ObjectClass *oc, void *data) @@ -5466,7 +5465,7 @@ static void init_proc_603(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(603)(ObjectClass *oc, void *data) @@ -5533,7 +5532,7 @@ static void init_proc_603E(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) @@ -5594,7 +5593,7 @@ static void init_proc_604(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(604)(ObjectClass *oc, void *data) @@ -5678,7 +5677,7 @@ static void init_proc_604E(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) @@ -5749,7 +5748,7 @@ static void init_proc_740(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(740)(ObjectClass *oc, void *data) @@ -5829,7 +5828,7 @@ static void init_proc_750(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(750)(ObjectClass *oc, void *data) @@ -5993,7 +5992,7 @@ static void init_proc_750cl(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) @@ -6115,7 +6114,7 @@ static void init_proc_750cx(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) @@ -6203,7 +6202,7 @@ static void init_proc_750fx(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) @@ -6291,7 +6290,7 @@ static void init_proc_750gx(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) @@ -6370,7 +6369,7 @@ static void init_proc_745(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(745)(ObjectClass *oc, void *data) @@ -6457,7 +6456,7 @@ static void init_proc_755(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(755)(ObjectClass *oc, void *data) @@ -6527,7 +6526,7 @@ static void init_proc_7400(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) @@ -6612,7 +6611,7 @@ static void init_proc_7410(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) @@ -6723,7 +6722,7 @@ static void init_proc_7440(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) @@ -6857,7 +6856,7 @@ static void init_proc_7450(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) @@ -6994,7 +6993,7 @@ static void init_proc_7445(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) @@ -7133,7 +7132,7 @@ static void init_proc_7455(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) @@ -7296,7 +7295,7 @@ static void init_proc_7457(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) @@ -7434,7 +7433,7 @@ static void init_proc_e600(CPUPPCState *env) env->dcache_line_size = 32; env->icache_line_size = 32; /* Allocate hardware IRQ controller */ - ppc6xx_irq_init(ppc_env_get_cpu(env)); + ppc6xx_irq_init(env_archcpu(env)); } POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) @@ -8298,7 +8297,7 @@ static void init_proc_970(CPUPPCState *env) /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } POWERPC_FAMILY(970)(ObjectClass *oc, void *data) @@ -8372,7 +8371,7 @@ static void init_proc_power5plus(CPUPPCState *env) /* Allocate hardware IRQ controller */ init_excp_970(env); - ppc970_irq_init(ppc_env_get_cpu(env)); + ppc970_irq_init(env_archcpu(env)); } POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) @@ -8487,7 +8486,7 @@ static void init_proc_POWER7(CPUPPCState *env) /* Allocate hardware IRQ controller */ init_excp_POWER7(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8639,7 +8638,7 @@ static void init_proc_POWER8(CPUPPCState *env) /* Allocate hardware IRQ controller */ init_excp_POWER8(env); - ppcPOWER7_irq_init(ppc_env_get_cpu(env)); + ppcPOWER7_irq_init(env_archcpu(env)); } static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) @@ -8838,7 +8837,7 @@ static void init_proc_POWER9(CPUPPCState *env) /* Allocate hardware IRQ controller */ init_excp_POWER9(env); - ppcPOWER9_irq_init(ppc_env_get_cpu(env)); + ppcPOWER9_irq_init(env_archcpu(env)); } static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) -- cgit v1.2.3-55-g7522 From 3109cd98a6c0c618189b38a83a8aa29cb20acbce Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:11:37 -0700 Subject: target/riscv: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- linux-user/riscv/cpu_loop.c | 2 +- target/riscv/cpu.h | 5 ----- target/riscv/cpu_helper.c | 10 ++++------ target/riscv/csr.c | 12 ++++++------ target/riscv/op_helper.c | 7 +++---- 5 files changed, 14 insertions(+), 22 deletions(-) (limited to 'linux-user') diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 31700f75d0..c1134597fd 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -25,7 +25,7 @@ void cpu_loop(CPURISCVState *env) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong ret; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ab038bac3..29a1e08f03 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -221,11 +221,6 @@ typedef struct RISCVCPU { } cfg; } RISCVCPU; -static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) -{ - return container_of(env, RISCVCPU, env); -} - static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { return (env->misa & ext) != 0; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c577a262b8..8b6754b917 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -89,14 +89,12 @@ struct CpuAsyncInfo { static void riscv_cpu_update_mip_irqs_async(CPUState *target_cpu_state, run_on_cpu_data data) { - CPURISCVState *env = &RISCV_CPU(target_cpu_state)->env; - RISCVCPU *cpu = riscv_env_get_cpu(env); struct CpuAsyncInfo *info = (struct CpuAsyncInfo *) data.host_ptr; if (info->new_mip) { - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + cpu_reset_interrupt(target_cpu_state, CPU_INTERRUPT_HARD); } g_free(info); @@ -212,7 +210,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, } } - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int va_bits = PGSHIFT + levels * ptidxbits; target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; @@ -341,7 +339,7 @@ restart: static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int page_fault_exceptions = (env->priv_ver >= PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9e2910643..c67d29e206 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -296,7 +296,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver <= PRIV_VERSION_1_09_1) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -307,7 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) if (env->priv_ver >= PRIV_VERSION_1_10_0) { if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | @@ -382,7 +382,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val) /* flush translation cache */ if (val != env->misa) { - tb_flush(CPU(riscv_env_get_cpu(env))); + tb_flush(env_cpu(env)); } env->misa = val; @@ -549,7 +549,7 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val) static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu = riscv_env_get_cpu(env); + RISCVCPU *cpu = env_archcpu(env); /* Allow software control of delegable interrupts not claimed by hardware */ target_ulong mask = write_mask & delegable_ints & ~env->miclaim; uint32_t old_mip; @@ -712,7 +712,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return 0; } if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); env->sptbr = val & (((target_ulong) 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); } @@ -724,7 +724,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) return -1; } else { if((val ^ env->satp) & SATP_ASID) { - tlb_flush(CPU(riscv_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } env->satp = val; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 644d0fb35f..331cc36232 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -28,7 +28,7 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index = exception; cpu_loop_exit_restore(cs, pc); @@ -128,7 +128,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) void helper_wfi(CPURISCVState *env) { - CPUState *cs = CPU(riscv_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && @@ -143,8 +143,7 @@ void helper_wfi(CPURISCVState *env) void helper_tlb_flush(CPURISCVState *env) { - RISCVCPU *cpu = riscv_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); if (!(env->priv >= PRV_S) || (env->priv == PRV_S && env->priv_ver >= PRIV_VERSION_1_10_0 && -- cgit v1.2.3-55-g7522 From dc79e928698567b14e6638c4c9f1e43dc386f1d8 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:21:48 -0700 Subject: target/s390x: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace s390_env_get_cpu with env_archcpu. The combination CPU(s390_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/s390x/cpu_loop.c | 2 +- target/s390x/cc_helper.c | 5 ++--- target/s390x/cpu.h | 5 ----- target/s390x/diag.c | 2 +- target/s390x/excp_helper.c | 8 ++++---- target/s390x/fpu_helper.c | 4 +--- target/s390x/helper.c | 7 +++---- target/s390x/int_helper.c | 3 +-- target/s390x/interrupt.c | 6 ++---- target/s390x/mem_helper.c | 28 ++++++++++--------------- target/s390x/misc_helper.c | 50 ++++++++++++++++++++++----------------------- target/s390x/mmu_helper.c | 8 ++++---- target/s390x/sigp.c | 4 ++-- 13 files changed, 57 insertions(+), 75 deletions(-) (limited to 'linux-user') diff --git a/linux-user/s390x/cpu_loop.c b/linux-user/s390x/cpu_loop.c index b8bd1c956c..8211022ceb 100644 --- a/linux-user/s390x/cpu_loop.c +++ b/linux-user/s390x/cpu_loop.c @@ -26,7 +26,7 @@ void cpu_loop(CPUS390XState *env) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, n, sig; target_siginfo_t info; target_ulong addr; diff --git a/target/s390x/cc_helper.c b/target/s390x/cc_helper.c index a00294f183..cf68792733 100644 --- a/target/s390x/cc_helper.c +++ b/target/s390x/cc_helper.c @@ -419,7 +419,6 @@ static uint32_t cc_calc_vc(uint64_t low, uint64_t high) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { - S390CPU *cpu = s390_env_get_cpu(env); uint32_t r = 0; switch (cc_op) { @@ -543,7 +542,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, break; default: - cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(env_cpu(env), "Unknown CC operation: %s\n", cc_name(cc_op)); } HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__, @@ -567,7 +566,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src, void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr) { load_psw(env, mask, addr); - cpu_loop_exit(CPU(s390_env_get_cpu(env))); + cpu_loop_exit(env_cpu(env)); } void HELPER(sacf)(CPUS390XState *env, uint64_t a1) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 56767f289d..d18b279d87 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,11 +163,6 @@ struct S390CPU { uint32_t irqstate_saved_size; }; -static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) -{ - return container_of(env, S390CPU, env); -} - #define ENV_OFFSET offsetof(S390CPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/diag.c b/target/s390x/diag.c index aafa740f61..65eabf0461 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -55,7 +55,7 @@ int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3) void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t addr = env->regs[r1]; uint64_t subcode = env->regs[r3]; IplParameterBlock *iplb; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index f21bcf79ae..202456cdc5 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -36,7 +36,7 @@ void QEMU_NORETURN tcg_s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, uintptr_t ra) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cpu_restore_state(cs, ra, true); qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n", @@ -51,7 +51,7 @@ void QEMU_NORETURN tcg_s390_data_exception(CPUS390XState *env, uint32_t dxc, g_assert(dxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Store the DXC into the lowcore */ - stl_phys(CPU(s390_env_get_cpu(env))->as, + stl_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, data_exc_code), dxc); #endif @@ -68,7 +68,7 @@ void QEMU_NORETURN tcg_s390_vector_exception(CPUS390XState *env, uint32_t vxc, g_assert(vxc <= 0xff); #if !defined(CONFIG_USER_ONLY) /* Always store the VXC into the lowcore, without AFP it is undefined */ - stl_phys(CPU(s390_env_get_cpu(env))->as, + stl_phys(env_cpu(env)->as, env->psa + offsetof(LowCore, data_exc_code), vxc); #endif @@ -297,7 +297,7 @@ static void do_svc_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { QEMUS390FLICState *flic = QEMU_S390_FLIC(s390_get_flic()); - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); uint64_t mask, addr; uint16_t cpu_addr; LowCore *lowcore; diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index d2c17ed942..5faf973c6c 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -114,8 +114,6 @@ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr) int float_comp_to_cc(CPUS390XState *env, int float_compare) { - S390CPU *cpu = s390_env_get_cpu(env); - switch (float_compare) { case float_relation_equal: return 0; @@ -126,7 +124,7 @@ int float_comp_to_cc(CPUS390XState *env, int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(CPU(cpu), "unknown return value for float compare\n"); + cpu_abort(env_cpu(env), "unknown return value for float compare\n"); } } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index a69e5abf5f..52a11daeae 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -111,11 +111,11 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) env->cc_op = (mask >> 44) & 3; if ((old_mask ^ mask) & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env))); + s390_cpu_recompute_watchpoints(env_cpu(env)); } if (mask & PSW_MASK_WAIT) { - s390_handle_wait(s390_env_get_cpu(env)); + s390_handle_wait(env_archcpu(env)); } } @@ -137,14 +137,13 @@ uint64_t get_psw_mask(CPUS390XState *env) LowCore *cpu_map_lowcore(CPUS390XState *env) { - S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; hwaddr len = sizeof(LowCore); lowcore = cpu_physical_memory_map(env->psa, &len, 1); if (len < sizeof(LowCore)) { - cpu_abort(CPU(cpu), "Could not map lowcore\n"); + cpu_abort(env_cpu(env), "Could not map lowcore\n"); } return lowcore; diff --git a/target/s390x/int_helper.c b/target/s390x/int_helper.c index abbbc20d9c..d13cc49be6 100644 --- a/target/s390x/int_helper.c +++ b/target/s390x/int_helper.c @@ -109,10 +109,9 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, s390_program_interrupt(env, PGM_FIXPT_DIVIDE, ILEN_AUTO, GETPC()); } #else - S390CPU *cpu = s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just abort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); + cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index a17eff5ebc..a8f9b38795 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -23,7 +23,7 @@ /* Ensure to exit the TB after this call! */ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_PGM; env->int_pgm_code = code; @@ -33,10 +33,8 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen) void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, uintptr_t ra) { - S390CPU *cpu = s390_env_get_cpu(env); - if (kvm_enabled()) { - kvm_s390_program_interrupt(cpu, code); + kvm_s390_program_interrupt(env_archcpu(env), code); } else if (tcg_enabled()) { tcg_s390_program_interrupt(env, code, ilen, ra); } else { diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 4a0161602f..29d9eaa5b7 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1617,7 +1617,6 @@ uint32_t HELPER(csst_parallel)(CPUS390XState *env, uint32_t r3, uint64_t a1, void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { uintptr_t ra = GETPC(); - S390CPU *cpu = s390_env_get_cpu(env); bool PERchanged = false; uint64_t src = a2; uint32_t i; @@ -1642,16 +1641,15 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) { uintptr_t ra = GETPC(); - S390CPU *cpu = s390_env_get_cpu(env); bool PERchanged = false; uint64_t src = a2; uint32_t i; @@ -1675,10 +1673,10 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) } if (PERchanged && env->psw.mask & PSW_MASK_PER) { - s390_cpu_recompute_watchpoints(CPU(cpu)); + s390_cpu_recompute_watchpoints(env_cpu(env)); } - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3) @@ -1737,8 +1735,8 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64_t real_addr) uint32_t HELPER(tprot)(CPUS390XState *env, uint64_t a1, uint64_t a2) { - S390CPU *cpu = s390_env_get_cpu(env); - CPUState *cs = CPU(cpu); + S390CPU *cpu = env_archcpu(env); + CPUState *cs = env_cpu(env); /* * TODO: we currently don't handle all access protection types @@ -1906,7 +1904,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2) void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); const uintptr_t ra = GETPC(); uint64_t table, entry, raddr; uint16_t entries, i, index = 0; @@ -1958,7 +1956,7 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4) void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, uint32_t m4) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); const uintptr_t ra = GETPC(); uint64_t page = vaddr & TARGET_PAGE_MASK; uint64_t pte_addr, pte; @@ -1998,17 +1996,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr, /* flush local tlb */ void HELPER(ptlb)(CPUS390XState *env) { - S390CPU *cpu = s390_env_get_cpu(env); - - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } /* flush global tlb */ void HELPER(purge)(CPUS390XState *env) { - S390CPU *cpu = s390_env_get_cpu(env); - - tlb_flush_all_cpus_synced(CPU(cpu)); + tlb_flush_all_cpus_synced(env_cpu(env)); } /* load using real address */ @@ -2052,7 +2046,7 @@ void HELPER(sturg)(CPUS390XState *env, uint64_t addr, uint64_t v1) /* load real address */ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t cc = 0; uint64_t asc = env->psw.mask & PSW_MASK_ASC; uint64_t ret; diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 10aa617cf9..7530dcb8f3 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -55,7 +55,7 @@ /* Raise an exception statically from a TB. */ void HELPER(exception)(CPUS390XState *env, uint32_t excp) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); HELPER_LOG("%s: exception %d\n", __func__, excp); cs->exception_index = excp; @@ -150,7 +150,7 @@ void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num) /* Set Prefix */ void HELPER(spx)(CPUS390XState *env, uint64_t a1) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t prefix = a1 & 0x7fffe000; env->psa = prefix; @@ -256,7 +256,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, uint64_t r0, uint64_t r1) const uint32_t sel2 = r1 & STSI_R1_SEL2_MASK; const MachineState *ms = MACHINE(qdev_get_machine()); uint16_t total_cpus = 0, conf_cpus = 0, reserved_cpus = 0; - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); SysIB sysib = { }; int i, cc = 0; @@ -411,7 +411,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1, #ifndef CONFIG_USER_ONLY void HELPER(xsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_xsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -419,7 +419,7 @@ void HELPER(xsch)(CPUS390XState *env, uint64_t r1) void HELPER(csch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_csch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -427,7 +427,7 @@ void HELPER(csch)(CPUS390XState *env, uint64_t r1) void HELPER(hsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_hsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -435,7 +435,7 @@ void HELPER(hsch)(CPUS390XState *env, uint64_t r1) void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_msch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -443,7 +443,7 @@ void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst) void HELPER(rchp)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rchp(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -451,7 +451,7 @@ void HELPER(rchp)(CPUS390XState *env, uint64_t r1) void HELPER(rsch)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_rsch(cpu, r1, GETPC()); qemu_mutex_unlock_iothread(); @@ -459,7 +459,7 @@ void HELPER(rsch)(CPUS390XState *env, uint64_t r1) void HELPER(sal)(CPUS390XState *env, uint64_t r1) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_sal(cpu, r1, GETPC()); @@ -468,7 +468,7 @@ void HELPER(sal)(CPUS390XState *env, uint64_t r1) void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_schm(cpu, r1, r2, inst >> 16, GETPC()); @@ -477,7 +477,7 @@ void HELPER(schm)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint64_t inst) void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_ssch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -485,7 +485,7 @@ void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst) void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_stcrw(cpu, inst >> 16, GETPC()); @@ -494,7 +494,7 @@ void HELPER(stcrw)(CPUS390XState *env, uint64_t inst) void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_stsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -503,7 +503,7 @@ void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) { const uintptr_t ra = GETPC(); - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic()); QEMUS390FlicIO *io = NULL; LowCore *lowcore; @@ -555,7 +555,7 @@ uint32_t HELPER(tpi)(CPUS390XState *env, uint64_t addr) void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_tsch(cpu, r1, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -563,7 +563,7 @@ void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst) void HELPER(chsc)(CPUS390XState *env, uint64_t inst) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); ioinst_handle_chsc(cpu, inst >> 16, GETPC()); qemu_mutex_unlock_iothread(); @@ -618,7 +618,7 @@ void HELPER(per_ifetch)(CPUS390XState *env, uint64_t addr) /* If the instruction has to be nullified, trigger the exception immediately. */ if (env->cregs[9] & PER_CR9_EVENT_NULLIFICATION) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); env->per_perc_atmid |= PER_CODE_EVENT_NULLIFICATION; env->int_pgm_code = PGM_PER; @@ -702,7 +702,7 @@ uint32_t HELPER(stfle)(CPUS390XState *env, uint64_t addr) */ void HELPER(clp)(CPUS390XState *env, uint32_t r2) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); clp_service_call(cpu, r2, GETPC()); @@ -711,7 +711,7 @@ void HELPER(clp)(CPUS390XState *env, uint32_t r2) void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); pcilg_service_call(cpu, r1, r2, GETPC()); @@ -720,7 +720,7 @@ void HELPER(pcilg)(CPUS390XState *env, uint32_t r1, uint32_t r2) void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); pcistg_service_call(cpu, r1, r2, GETPC()); @@ -730,7 +730,7 @@ void HELPER(pcistg)(CPUS390XState *env, uint32_t r1, uint32_t r2) void HELPER(stpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); stpcifc_service_call(cpu, r1, fiba, ar, GETPC()); @@ -752,7 +752,7 @@ void HELPER(sic)(CPUS390XState *env, uint64_t r1, uint64_t r3) void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); rpcit_service_call(cpu, r1, r2, GETPC()); @@ -762,7 +762,7 @@ void HELPER(rpcit)(CPUS390XState *env, uint32_t r1, uint32_t r2) void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint64_t gaddr, uint32_t ar) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); pcistb_service_call(cpu, r1, r3, gaddr, ar, GETPC()); @@ -772,7 +772,7 @@ void HELPER(pcistb)(CPUS390XState *env, uint32_t r1, uint32_t r3, void HELPER(mpcifc)(CPUS390XState *env, uint32_t r1, uint64_t fiba, uint32_t ar) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); qemu_mutex_lock_iothread(); mpcifc_service_call(cpu, r1, fiba, ar, GETPC()); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index 145b62a7ef..9669bae393 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -58,12 +58,12 @@ static void trigger_access_exception(CPUS390XState *env, uint32_t type, uint32_t ilen, uint64_t tec) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); if (kvm_enabled()) { kvm_s390_access_exception(cpu, type, tec); } else { - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); if (type != PGM_ADDRESSING) { stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); } @@ -185,7 +185,7 @@ static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t origin, offs, pt_entry; if (st_entry & SEGMENT_ENTRY_RO) { @@ -214,7 +214,7 @@ static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr, target_ulong *raddr, int *flags, int rw, bool exc) { - CPUState *cs = CPU(s390_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t origin, offs, new_entry; const int pchks[4] = { PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index c1f9245797..ea5f69d5d8 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -454,7 +454,7 @@ int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3) { uint64_t *status_reg = &env->regs[r1]; uint64_t param = (r1 % 2) ? env->regs[r1] : env->regs[r1 + 1]; - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); S390CPU *dst_cpu = NULL; int ret; @@ -492,7 +492,7 @@ int s390_cpu_restart(S390CPU *cpu) void do_stop_interrupt(CPUS390XState *env) { - S390CPU *cpu = s390_env_get_cpu(env); + S390CPU *cpu = env_archcpu(env); if (s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu) == 0) { qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); -- cgit v1.2.3-55-g7522 From dad1c8ecc707a0f3fe6963b364477ce0a92670fa Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:26:42 -0700 Subject: target/sh4: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace sh_env_get_cpu with env_archcpu. The combination CPU(sh_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/sh4/cpu_loop.c | 2 +- target/sh4/cpu.h | 5 ----- target/sh4/helper.c | 26 ++++++++++++-------------- target/sh4/op_helper.c | 9 +++------ 4 files changed, 16 insertions(+), 26 deletions(-) (limited to 'linux-user') diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c index 59cbbeda7e..add8817d86 100644 --- a/linux-user/sh4/cpu_loop.c +++ b/linux-user/sh4/cpu_loop.c @@ -23,7 +23,7 @@ void cpu_loop(CPUSH4State *env) { - CPUState *cs = CPU(sh_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, ret; target_siginfo_t info; diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 8b17e6d63e..089eea261c 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,11 +207,6 @@ struct SuperHCPU { CPUSH4State env; }; -static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) -{ - return container_of(env, SuperHCPU, env); -} - #define ENV_OFFSET offsetof(SuperHCPU, env) void superh_cpu_do_interrupt(CPUState *cpu); diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fda195e7cb..2afc1770d8 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -216,8 +216,6 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb) static int itlb_replacement(CPUSH4State * env) { - SuperHCPU *cpu = sh_env_get_cpu(env); - if ((env->mmucr & 0xe0000000) == 0xe0000000) { return 0; } @@ -230,7 +228,7 @@ static int itlb_replacement(CPUSH4State * env) if ((env->mmucr & 0x2c000000) == 0x00000000) { return 3; } - cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); + cpu_abort(env_cpu(env), "Unhandled itlb_replacement"); } /* Find the corresponding entry in the right TLB @@ -286,7 +284,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb) itlb = itlb_replacement(env); ientry = &env->itlb[itlb]; if (ientry->v) { - tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10); + tlb_flush_page(env_cpu(env), ientry->vpn << 10); } *ientry = env->utlb[utlb]; update_itlb_use(env, itlb); @@ -448,14 +446,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_load_tlb(CPUSH4State * env) { - SuperHCPU *cpu = sh_env_get_cpu(env); + CPUState *cs = env_cpu(env); int n = cpu_mmucr_urc(env->mmucr); tlb_t * entry = &env->utlb[n]; if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(CPU(cpu), address); + tlb_flush_page(cs, address); } /* Take values into cpu status from registers. */ @@ -478,7 +476,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size = 1024 * 1024; /* 1M */ break; default: - cpu_abort(CPU(cpu), "Unhandled load_tlb"); + cpu_abort(cs, "Unhandled load_tlb"); break; } entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); @@ -505,7 +503,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->v = 0; } - tlb_flush(CPU(sh_env_get_cpu(s))); + tlb_flush(env_cpu(s)); } uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s, @@ -531,7 +529,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in itlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->asid = asid; entry->vpn = vpn; @@ -573,7 +571,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; @@ -626,7 +624,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, if (entry->vpn == vpn && (!use_asid || entry->asid == asid || entry->sh)) { if (utlb_match_entry) { - CPUState *cs = CPU(sh_env_get_cpu(s)); + CPUState *cs = env_cpu(s); /* Multiple TLB Exception */ cs->exception_index = 0x140; @@ -658,13 +656,13 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr, } if (needs_tlb_flush) { - tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10); + tlb_flush_page(env_cpu(s), vpn << 10); } } else { int index = (addr & 0x00003f00) >> 8; tlb_t * entry = &s->utlb[index]; if (entry->v) { - CPUState *cs = CPU(sh_env_get_cpu(s)); + CPUState *cs = env_cpu(s); /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; @@ -719,7 +717,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, if (entry->v) { /* Overwriting valid entry in utlb. */ target_ulong address = entry->vpn << 10; - tlb_flush_page(CPU(sh_env_get_cpu(s)), address); + tlb_flush_page(env_cpu(s), address); } entry->ppn = (mem_value & 0x1ffffc00) >> 10; entry->v = (mem_value & 0x00000100) >> 8; diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 932aa7a7c7..14c3db0f48 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -46,10 +46,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY - SuperHCPU *cpu = sh_env_get_cpu(env); - - /* XXXXX */ - cpu_abort(CPU(cpu), "Unhandled ldtlb"); + cpu_abort(env_cpu(env), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif @@ -58,7 +55,7 @@ void helper_ldtlb(CPUSH4State *env) static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index, uintptr_t retaddr) { - CPUState *cs = CPU(sh_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = index; cpu_loop_exit_restore(cs, retaddr); @@ -91,7 +88,7 @@ void helper_debug(CPUSH4State *env) void helper_sleep(CPUSH4State *env) { - CPUState *cs = CPU(sh_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->halted = 1; env->in_sleep = 1; -- cgit v1.2.3-55-g7522 From 5a59fbce9141c40db0f0a5a6e17583ad9189b48b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:36:20 -0700 Subject: target/sparc: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace sparc_env_get_cpu with env_archcpu. The combination CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- bsd-user/main.c | 2 +- hw/sparc/leon3.c | 4 ++-- hw/sparc/sun4m.c | 4 ++-- hw/sparc64/sparc64.c | 2 +- linux-user/sparc/cpu_loop.c | 2 +- target/sparc/cpu.h | 5 ----- target/sparc/fop_helper.c | 2 +- target/sparc/helper.c | 8 ++++---- target/sparc/ldst_helper.c | 33 +++++++++++++++------------------ target/sparc/mmu_helper.c | 10 +++++----- 10 files changed, 32 insertions(+), 40 deletions(-) (limited to 'linux-user') diff --git a/bsd-user/main.c b/bsd-user/main.c index 53e1f42408..c473a99153 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -486,7 +486,7 @@ static void flush_windows(CPUSPARCState *env) void cpu_loop(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr, ret, syscall_nr; //target_siginfo_t info; diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index bdead85a93..19cedebd16 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -159,7 +159,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in) env->interrupt_index = TT_EXTINT | i; if (old_interrupt != env->interrupt_index) { - cs = CPU(sparc_env_get_cpu(env)); + cs = env_cpu(env); trace_leon3_set_irq(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -167,7 +167,7 @@ static void leon3_set_pil_in(void *opaque, uint32_t pil_in) } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = CPU(sparc_env_get_cpu(env)); + cs = env_cpu(env); trace_leon3_reset_irq(env->interrupt_index & 15); env->interrupt_index = 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 5151a7202b..7e4f61fc3e 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -166,7 +166,7 @@ void cpu_check_irqs(CPUSPARCState *env) env->interrupt_index = TT_EXTINT | i; if (old_interrupt != env->interrupt_index) { - cs = CPU(sparc_env_get_cpu(env)); + cs = env_cpu(env); trace_sun4m_cpu_interrupt(i); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -174,7 +174,7 @@ void cpu_check_irqs(CPUSPARCState *env) } } } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { - cs = CPU(sparc_env_get_cpu(env)); + cs = env_cpu(env); trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); env->interrupt_index = 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 408388945e..689801f37d 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -46,7 +46,7 @@ void cpu_check_irqs(CPUSPARCState *env) if (env->ivec_status & 0x20) { return; } - cs = CPU(sparc_env_get_cpu(env)); + cs = env_cpu(env); /* check if TM or SM in SOFTINT are set setting these also causes interrupt 14 */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { diff --git a/linux-user/sparc/cpu_loop.c b/linux-user/sparc/cpu_loop.c index 9e357229c0..d85359037c 100644 --- a/linux-user/sparc/cpu_loop.c +++ b/linux-user/sparc/cpu_loop.c @@ -145,7 +145,7 @@ static void flush_windows(CPUSPARCState *env) void cpu_loop (CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; abi_long ret; target_siginfo_t info; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index e29421349b..adcd9e3000 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -532,11 +532,6 @@ struct SPARCCPU { CPUSPARCState env; }; -static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) -{ - return container_of(env, SPARCCPU, env); -} - #define ENV_OFFSET offsetof(SPARCCPU, env) #ifndef CONFIG_USER_ONLY diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index b6642fd1d7..9eb9b75718 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -53,7 +53,7 @@ static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) } if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); /* Unmasked exception, generate a trap. Note that while the helper is marked as NO_WG, we can get away with diff --git a/target/sparc/helper.c b/target/sparc/helper.c index 46232788c8..1a52061fbf 100644 --- a/target/sparc/helper.c +++ b/target/sparc/helper.c @@ -26,7 +26,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = tt; cpu_loop_exit_restore(cs, ra); @@ -34,7 +34,7 @@ void cpu_raise_exception_ra(CPUSPARCState *env, int tt, uintptr_t ra) void helper_raise_exception(CPUSPARCState *env, int tt) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = tt; cpu_loop_exit(cs); @@ -42,7 +42,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt) void helper_debug(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = EXCP_DEBUG; cpu_loop_exit(cs); @@ -243,7 +243,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1, #ifndef TARGET_SPARC64 void helper_power_down(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->halted = 1; cs->exception_index = EXCP_HLT; diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index b4bf6faf41..7f56c100c6 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -122,13 +122,13 @@ static uint64_t ultrasparc_tag_target(uint64_t tag_access_register) static void replace_tlb_entry(SparcTLBEntry *tlb, uint64_t tlb_tag, uint64_t tlb_tte, - CPUSPARCState *env1) + CPUSPARCState *env) { target_ulong mask, size, va, offset; /* flush page range if translation is valid */ if (TTE_IS_VALID(tlb->tte)) { - CPUState *cs = CPU(sparc_env_get_cpu(env1)); + CPUState *cs = env_cpu(env); size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); mask = 1ULL + ~size; @@ -499,7 +499,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { int size = 1 << (memop & MO_SIZE); int sign = memop & MO_SIGN; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t ret = 0; #if defined(DEBUG_MXCC) || defined(DEBUG_ASI) uint32_t last_addr = addr; @@ -725,8 +725,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, uint32_t memop) { int size = 1 << (memop & MO_SIZE); - SPARCCPU *cpu = sparc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); do_check_align(env, addr, size - 1, GETPC()); switch (asi) { @@ -874,13 +873,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, DPRINTF_MMU("mmu flush level %d\n", mmulev); switch (mmulev) { case 0: /* flush page */ - tlb_flush_page(CPU(cpu), addr & 0xfffff000); + tlb_flush_page(cs, addr & 0xfffff000); break; case 1: /* flush segment (256k) */ case 2: /* flush region (16M) */ case 3: /* flush context (4G) */ case 4: /* flush entire */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; default: break; @@ -905,7 +904,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) & (MMU_NF | env->def.mmu_bm)) { - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 1: /* Context Table Pointer Register */ @@ -916,7 +915,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); } break; case 3: /* Synchronous Fault Status Register with Clear */ @@ -1027,8 +1026,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case ASI_USERTXT: /* User code access, XXX */ case ASI_KERNELTXT: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(CPU(sparc_env_get_cpu(env)), - addr, true, false, asi, size); + cpu_unassigned_access(cs, addr, true, false, asi, size); break; case ASI_USERDATA: /* User data access */ @@ -1175,7 +1173,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, { int size = 1 << (memop & MO_SIZE); int sign = memop & MO_SIGN; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint64_t ret = 0; #if defined(DEBUG_ASI) target_ulong last_addr = addr; @@ -1481,8 +1479,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, int asi, uint32_t memop) { int size = 1 << (memop & MO_SIZE); - SPARCCPU *cpu = sparc_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); #ifdef DEBUG_ASI dump_asi("write", addr, asi, size, val); @@ -1686,13 +1683,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.mmu_primary_context = val; /* can be optimized to only flush MMU_USER_IDX and MMU_KERNEL_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 2: /* Secondary context */ env->dmmu.mmu_secondary_context = val; /* can be optimized to only flush MMU_USER_SECONDARY_IDX and MMU_KERNEL_SECONDARY_IDX entries */ - tlb_flush(CPU(cpu)); + tlb_flush(cs); break; case 5: /* TSB access */ DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" @@ -1768,13 +1765,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case 1: env->dmmu.mmu_primary_context = val; env->immu.mmu_primary_context = val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX)); break; case 2: env->dmmu.mmu_secondary_context = val; env->immu.mmu_secondary_context = val; - tlb_flush_by_mmuidx(CPU(cpu), + tlb_flush_by_mmuidx(cs, (1 << MMU_USER_SECONDARY_IDX) | (1 << MMU_KERNEL_SECONDARY_IDX)); break; diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index facc0c60e9..cbd1e91179 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -97,7 +97,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, uint32_t pde; int error_code = 0, is_dirty, is_user; unsigned long page_offset; - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); is_user = mmu_idx == MMU_USER_IDX; @@ -268,7 +268,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); hwaddr pde_ptr; uint32_t pde; @@ -335,7 +335,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) void dump_mmu(CPUSPARCState *env) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_ulong va, va1, va2; unsigned int n, m, o; hwaddr pde_ptr, pa; @@ -494,7 +494,7 @@ static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int mmu_idx) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned int i; uint64_t context; uint64_t sfsr = 0; @@ -612,7 +612,7 @@ static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, int *prot, target_ulong address, int mmu_idx) { - CPUState *cs = CPU(sparc_env_get_cpu(env)); + CPUState *cs = env_cpu(env); unsigned int i; uint64_t context; bool is_user = false; -- cgit v1.2.3-55-g7522 From 06887771bda2a297f2fb669522166a97d67e2ad9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:38:33 -0700 Subject: target/tilegx: Use env_cpu Cleanup in the boilerplate that each target must define. Replace tilegx_env_get_cpu with env_archcpu. The combination CPU(tilegx_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/tilegx/cpu_loop.c | 2 +- target/tilegx/cpu.h | 5 ----- target/tilegx/helper.c | 2 +- 3 files changed, 2 insertions(+), 7 deletions(-) (limited to 'linux-user') diff --git a/linux-user/tilegx/cpu_loop.c b/linux-user/tilegx/cpu_loop.c index 4f39eb9ad3..d4abe29dcd 100644 --- a/linux-user/tilegx/cpu_loop.c +++ b/linux-user/tilegx/cpu_loop.c @@ -206,7 +206,7 @@ static void do_fetch(CPUTLGState *env, int trapnr, bool quad) void cpu_loop(CPUTLGState *env) { - CPUState *cs = CPU(tilegx_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int trapnr; while (1) { diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h index 135df63523..7f8fe7c513 100644 --- a/target/tilegx/cpu.h +++ b/target/tilegx/cpu.h @@ -138,11 +138,6 @@ typedef struct TileGXCPU { CPUTLGState env; } TileGXCPU; -static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env) -{ - return container_of(env, TileGXCPU, env); -} - #define ENV_OFFSET offsetof(TileGXCPU, env) /* TILE-Gx memory attributes */ diff --git a/target/tilegx/helper.c b/target/tilegx/helper.c index 4964bb9111..a57a679825 100644 --- a/target/tilegx/helper.c +++ b/target/tilegx/helper.c @@ -28,7 +28,7 @@ void helper_exception(CPUTLGState *env, uint32_t excp) { - CPUState *cs = CPU(tilegx_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = excp; cpu_loop_exit(cs); -- cgit v1.2.3-55-g7522 From 92fddfbd1792cb6009f869c47e7ea55a741fe2e3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 22 Mar 2019 19:52:17 -0700 Subject: target/xtensa: Use env_cpu, env_archcpu Cleanup in the boilerplate that each target must define. Replace xtensa_env_get_cpu with env_archcpu. The combination CPU(xtensa_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Move cpu_get_tb_cpu_state below the include of "exec/cpu-all.h" so that the definition of env_cpu is available. Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- hw/xtensa/pic_cpu.c | 2 +- linux-user/xtensa/cpu_loop.c | 2 +- target/xtensa/cpu.h | 17 ++++++----------- target/xtensa/dbg_helper.c | 4 ++-- target/xtensa/exc_helper.c | 9 ++++----- target/xtensa/helper.c | 2 +- target/xtensa/mmu_helper.c | 17 ++++++----------- target/xtensa/xtensa-semi.c | 2 +- 8 files changed, 22 insertions(+), 33 deletions(-) (limited to 'linux-user') diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index a8939f5e58..df3acbb541 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -33,7 +33,7 @@ void check_interrupts(CPUXtensaState *env) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int minlevel = xtensa_get_cintlevel(env); uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE]; int level; diff --git a/linux-user/xtensa/cpu_loop.c b/linux-user/xtensa/cpu_loop.c index bee78edb8a..64831c9199 100644 --- a/linux-user/xtensa/cpu_loop.c +++ b/linux-user/xtensa/cpu_loop.c @@ -123,7 +123,7 @@ static void xtensa_underflow12(CPUXtensaState *env) void cpu_loop(CPUXtensaState *env) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); target_siginfo_t info; abi_ulong ret; int trapnr; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3de53cb5d0..97b7bae0fe 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -559,11 +559,6 @@ struct XtensaCPU { CPUXtensaState env; }; -static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) -{ - return container_of(env, XtensaCPU, env); -} - #define ENV_OFFSET offsetof(XtensaCPU, env) @@ -724,10 +719,15 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 +typedef CPUXtensaState CPUArchState; +typedef XtensaCPU ArchCPU; + +#include "exec/cpu-all.h" + static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); *pc = env->pc; *cs_base = 0; @@ -797,9 +797,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, } } -typedef CPUXtensaState CPUArchState; -typedef XtensaCPU ArchCPU; - -#include "exec/cpu-all.h" - #endif diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index cd8fbd653a..be1f81107b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -71,7 +71,7 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask = dbreakc | ~DBREAKC_MASK; @@ -118,7 +118,7 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] = NULL; diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 4a1f7aef5d..601341d13a 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -34,7 +34,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); cs->exception_index = excp; if (excp == EXCP_YIELD) { @@ -100,7 +100,7 @@ void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause) void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) { - CPUState *cpu; + CPUState *cpu = env_cpu(env); env->pc = pc; env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | @@ -111,11 +111,10 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel) qemu_mutex_unlock_iothread(); if (env->pending_irq_level) { - cpu_loop_exit(CPU(xtensa_env_get_cpu(env))); + cpu_loop_exit(cpu); return; } - cpu = CPU(xtensa_env_get_cpu(env)); cpu->halted = 1; HELPER(exception)(env, EXCP_HLT); } @@ -165,7 +164,7 @@ static void handle_interrupt(CPUXtensaState *env) (env->config->level_mask[level] & env->sregs[INTSET] & env->sregs[INTENABLE])) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); if (level > 1) { env->sregs[EPC1 + level - 1] = env->pc; diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f2d07e4a2f..376a61f339 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -324,7 +324,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, void xtensa_runstall(CPUXtensaState *env, bool runstall) { - CPUState *cpu = CPU(xtensa_env_get_cpu(env)); + CPUState *cpu = env_cpu(env); env->runstall = runstall; cpu->halted = runstall; diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index cab39f687a..f15bff306f 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -71,12 +71,10 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) { - XtensaCPU *cpu = xtensa_env_get_cpu(env); - v = (v & 0xffffff00) | 0x1; if (v != env->sregs[RASID]) { env->sregs[RASID] = v; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } @@ -276,8 +274,7 @@ static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) { - XtensaCPU *cpu = xtensa_env_get_cpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { @@ -503,7 +500,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t wi; xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); if (entry->variable && entry->asid) { - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); + tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid = 0; } } @@ -844,7 +841,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t paddr; uint32_t page_size; unsigned access; @@ -924,13 +921,11 @@ static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) { - XtensaCPU *cpu = xtensa_env_get_cpu(env); - v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; if (v != env->sregs[MPUENB]) { env->sregs[MPUENB] = v; - tlb_flush(CPU(cpu)); + tlb_flush(env_cpu(env)); } } @@ -942,7 +937,7 @@ void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) env->mpu_fg[segment].vaddr = v & -env->config->mpu_align; env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK; env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v); - tlb_flush(CPU(xtensa_env_get_cpu(env))); + tlb_flush(env_cpu(env)); } } diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c index 38efa3485a..8862985e56 100644 --- a/target/xtensa/xtensa-semi.c +++ b/target/xtensa/xtensa-semi.c @@ -197,7 +197,7 @@ void xtensa_sim_open_console(Chardev *chr) void HELPER(simcall)(CPUXtensaState *env) { - CPUState *cs = CPU(xtensa_env_get_cpu(env)); + CPUState *cs = env_cpu(env); uint32_t *regs = env->regs; switch (regs[2]) { -- cgit v1.2.3-55-g7522