From 27103424c40ce71053c07d8a54ef431365fa9b7f Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 08:31:06 +0200 Subject: cpu: Move exception_index field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- linux-user/signal.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'linux-user') diff --git a/linux-user/signal.c b/linux-user/signal.c index c8a1da0749..acf10328ee 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -774,8 +774,9 @@ static int setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr) { - int err = 0; - uint16_t magic; + CPUState *cs = CPU(x86_env_get_cpu(env)); + int err = 0; + uint16_t magic; /* already locked in setup_frame() */ err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs); @@ -790,7 +791,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate, err |= __put_user(env->regs[R_EDX], &sc->edx); err |= __put_user(env->regs[R_ECX], &sc->ecx); err |= __put_user(env->regs[R_EAX], &sc->eax); - err |= __put_user(env->exception_index, &sc->trapno); + err |= __put_user(cs->exception_index, &sc->trapno); err |= __put_user(env->error_code, &sc->err); err |= __put_user(env->eip, &sc->eip); err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs); -- cgit v1.2.3-55-g7522 From 0429a9719551a4aa794051aeb8c7b42658902c27 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:14:44 +0200 Subject: cpu: Move opaque field from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- bsd-user/main.c | 2 +- gdbstub.c | 3 +-- include/exec/cpu-defs.h | 3 --- include/qom/cpu.h | 3 +++ linux-user/elfload.c | 10 ++++++---- linux-user/linuxload.c | 3 +-- linux-user/m68k/target_cpu.h | 4 +++- linux-user/main.c | 6 +++--- linux-user/signal.c | 17 +++++++++++------ linux-user/syscall.c | 30 ++++++++++++++++++------------ linux-user/vm86.c | 27 ++++++++++++++++++--------- target-arm/arm-semi.c | 9 +++++---- target-m68k/m68k-semi.c | 3 ++- 13 files changed, 72 insertions(+), 48 deletions(-) (limited to 'linux-user') diff --git a/bsd-user/main.c b/bsd-user/main.c index f9246aa102..f81ba55af8 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -1000,7 +1000,7 @@ int main(int argc, char **argv) memset(ts, 0, sizeof(TaskState)); init_task_state(ts); ts->info = info; - env->opaque = ts; + cpu->opaque = ts; #if defined(TARGET_I386) cpu_x86_set_cpl(env, 3); diff --git a/gdbstub.c b/gdbstub.c index e8ab0b2992..c5ab73fb1d 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1086,8 +1086,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) } #ifdef CONFIG_USER_ONLY else if (strncmp(p, "Offsets", 7) == 0) { - CPUArchState *env = s->c_cpu->env_ptr; - TaskState *ts = env->opaque; + TaskState *ts = s->c_cpu->opaque; snprintf(buf, sizeof(buf), "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bec06e8f99..8af85476fc 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -138,8 +138,5 @@ typedef struct CPUWatchpoint { \ QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ CPUWatchpoint *watchpoint_hit; \ - \ - /* user data */ \ - void *opaque; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index a385b9f71d..4d1ea35ca4 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -184,6 +184,7 @@ struct kvm_run; * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @next_cpu: Next CPU sharing TB cache. + * @opaque: User data. * @mem_io_pc: Host Program Counter at which the memory was accessed. * @mem_io_vaddr: Target virtual address at which the memory was accessed. * @kvm_fd: vCPU file descriptor for KVM. @@ -230,6 +231,8 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + void *opaque; + /* In order to avoid passing too many arguments to the MMIO helpers, * we store some rarely used information in the CPU context. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index c0687e3b38..6bc799957b 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2621,7 +2621,8 @@ static int write_note(struct memelfnote *men, int fd) static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env) { - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; struct elf_thread_status *ets; ets = g_malloc0(sizeof (*ets)); @@ -2650,8 +2651,8 @@ static int fill_note_info(struct elf_note_info *info, long signr, const CPUArchState *env) { #define NUMNOTES 3 - CPUState *cpu = NULL; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + TaskState *ts = (TaskState *)cpu->opaque; int i; info->notes = g_malloc0(NUMNOTES * sizeof (struct memelfnote)); @@ -2775,7 +2776,8 @@ static int write_note_info(struct elf_note_info *info, int fd) */ static int elf_core_dump(int signr, const CPUArchState *env) { - const TaskState *ts = (const TaskState *)env->opaque; + const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env); + const TaskState *ts = (const TaskState *)cpu->opaque; struct vm_area_struct *vma = NULL; char corefile[PATH_MAX]; struct elf_note_info info; diff --git a/linux-user/linuxload.c b/linux-user/linuxload.c index f2997c2f4b..506e837ae1 100644 --- a/linux-user/linuxload.c +++ b/linux-user/linuxload.c @@ -89,8 +89,7 @@ static int prepare_binprm(struct linux_binprm *bprm) abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp, abi_ulong stringp, int push_ptr) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + TaskState *ts = (TaskState *)thread_cpu->opaque; int n = sizeof(abi_ulong); abi_ulong envp; abi_ulong argv; diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h index cad9c90dd0..bb4d3fabe1 100644 --- a/linux-user/m68k/target_cpu.h +++ b/linux-user/m68k/target_cpu.h @@ -31,7 +31,9 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp) static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; + ts->tp_value = newtls; } diff --git a/linux-user/main.c b/linux-user/main.c index dee10841c3..6e62b8babd 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -685,7 +685,7 @@ void cpu_loop(CPUARMState *env) switch(trapnr) { case EXCP_UDEF: { - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; uint32_t opcode; int rc; @@ -2965,7 +2965,7 @@ void cpu_loop(CPUM68KState *env) int trapnr; unsigned int n; target_siginfo_t info; - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; for(;;) { trapnr = cpu_m68k_exec(env); @@ -4001,7 +4001,7 @@ int main(int argc, char **argv, char **envp) /* build Task State */ ts->info = info; ts->bprm = &bprm; - env->opaque = ts; + cpu->opaque = ts; task_settid(ts); execfd = qemu_getauxval(AT_EXECFD); diff --git a/linux-user/signal.c b/linux-user/signal.c index acf10328ee..24c91f37d9 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -370,7 +370,8 @@ void signal_init(void) static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct sigqueue *q = ts->first_free; if (!q) return NULL; @@ -380,7 +381,9 @@ static inline struct sigqueue *alloc_sigqueue(CPUArchState *env) static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; + q->next = ts->first_free; ts->first_free = q; } @@ -388,8 +391,9 @@ static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q) /* abort execution with signal */ static void QEMU_NORETURN force_sig(int target_sig) { - CPUArchState *env = thread_cpu->env_ptr; - TaskState *ts = (TaskState *)env->opaque; + CPUState *cpu = thread_cpu; + CPUArchState *env = cpu->env_ptr; + TaskState *ts = (TaskState *)cpu->opaque; int host_sig, core_dumped = 0; struct sigaction act; host_sig = target_to_host_signal(target_sig); @@ -440,7 +444,8 @@ static void QEMU_NORETURN force_sig(int target_sig) as possible */ int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info) { - TaskState *ts = env->opaque; + CPUState *cpu = ENV_GET_CPU(env); + TaskState *ts = cpu->opaque; struct emulated_sigtable *k; struct sigqueue *q, **pq; abi_ulong handler; @@ -5676,7 +5681,7 @@ void process_pending_signals(CPUArchState *cpu_env) struct emulated_sigtable *k; struct target_sigaction *sa; struct sigqueue *q; - TaskState *ts = cpu_env->opaque; + TaskState *ts = cpu->opaque; if (!ts->signal_pending) return; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index e2c10cc0bd..ffc11de4b7 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4243,7 +4243,7 @@ static void *clone_func(void *arg) env = info->env; cpu = ENV_GET_CPU(env); thread_cpu = cpu; - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; info->tid = gettid(); cpu->host_tid = info->tid; task_settid(ts); @@ -4271,8 +4271,10 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, abi_ulong parent_tidptr, target_ulong newtls, abi_ulong child_tidptr) { + CPUState *cpu = ENV_GET_CPU(env); int ret; TaskState *ts; + CPUState *new_cpu; CPUArchState *new_env; unsigned int nptl_flags; sigset_t sigmask; @@ -4282,7 +4284,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, flags &= ~(CLONE_VFORK | CLONE_VM); if (flags & CLONE_VM) { - TaskState *parent_ts = (TaskState *)env->opaque; + TaskState *parent_ts = (TaskState *)cpu->opaque; new_thread_info info; pthread_attr_t attr; @@ -4292,7 +4294,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, new_env = cpu_copy(env); /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); - new_env->opaque = ts; + new_cpu = ENV_GET_CPU(new_env); + new_cpu->opaque = ts; ts->bprm = parent_ts->bprm; ts->info = parent_ts->info; nptl_flags = flags; @@ -4364,7 +4367,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, put_user_u32(gettid(), child_tidptr); if (flags & CLONE_PARENT_SETTID) put_user_u32(gettid(), parent_tidptr); - ts = (TaskState *)env->opaque; + ts = (TaskState *)cpu->opaque; if (flags & CLONE_SETTLS) cpu_set_tls (env, newtls); if (flags & CLONE_CHILD_CLEARTID) @@ -4974,7 +4977,8 @@ void init_qemu_uname_release(void) static int open_self_maps(void *cpu_env, int fd) { #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32) - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; #endif FILE *fp; char *line = NULL; @@ -5026,7 +5030,8 @@ static int open_self_maps(void *cpu_env, int fd) static int open_self_stat(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong start_stack = ts->info->start_stack; int i; @@ -5062,7 +5067,8 @@ static int open_self_stat(void *cpu_env, int fd) static int open_self_auxv(void *cpu_env, int fd) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env); + TaskState *ts = cpu->opaque; abi_ulong auxv = ts->info->saved_auxv; abi_ulong len = ts->info->auxv_len; char *ptr; @@ -5244,14 +5250,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, /* Remove the CPU from the list. */ QTAILQ_REMOVE(&cpus, cpu, node); cpu_list_unlock(); - ts = ((CPUArchState *)cpu_env)->opaque; + ts = cpu->opaque; if (ts->child_tidptr) { put_user_u32(0, ts->child_tidptr); sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } thread_cpu = NULL; - object_unref(OBJECT(ENV_GET_CPU(cpu_env))); + object_unref(OBJECT(cpu)); g_free(ts); pthread_exit(NULL); } @@ -6555,7 +6561,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; case TARGET_NR_mprotect: { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; /* Special hack to detect libc making the stack executable. */ if ((arg3 & PROT_GROWSDOWN) && arg1 >= ts->info->stack_limit @@ -8647,7 +8653,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ts->tp_value = arg1; ret = 0; break; @@ -8663,7 +8669,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, break; #elif defined(TARGET_M68K) { - TaskState *ts = ((CPUArchState *)cpu_env)->opaque; + TaskState *ts = cpu->opaque; ret = ts->tp_value; break; } diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 2c4ffeb551..45ef559ec6 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -72,7 +72,8 @@ static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16) void save_v86_state(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) @@ -131,7 +132,8 @@ static inline void return_to_32bit(CPUX86State *env, int retval) static inline int set_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags |= VIF_MASK; if (ts->v86flags & VIP_MASK) { @@ -143,7 +145,8 @@ static inline int set_IF(CPUX86State *env) static inline void clear_IF(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; ts->v86flags &= ~VIF_MASK; } @@ -160,7 +163,8 @@ static inline void clear_AC(CPUX86State *env) static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, eflags, ts->v86mask); set_flags(env->eflags, eflags, SAFE_MASK); @@ -173,7 +177,8 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) static inline int set_vflags_short(unsigned short flags, CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); set_flags(env->eflags, flags, SAFE_MASK); @@ -186,7 +191,8 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env) static inline unsigned int get_vflags(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; unsigned int flags; flags = env->eflags & RETURN_MASK; @@ -202,7 +208,8 @@ static inline unsigned int get_vflags(CPUX86State *env) support TSS interrupt revectoring, so this code is always executed) */ static void do_int(CPUX86State *env, int intno) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t int_addr, segoffs, ssp; unsigned int sp; @@ -260,7 +267,8 @@ void handle_vm86_trap(CPUX86State *env, int trapno) void handle_vm86_fault(CPUX86State *env) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; uint32_t csp, ssp; unsigned int ip, sp, newflags, newip, newcs, opcode, intno; int data32, pref_done; @@ -384,7 +392,8 @@ void handle_vm86_fault(CPUX86State *env) int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(x86_env_get_cpu(env)); + TaskState *ts = cs->opaque; struct target_vm86plus_struct * target_v86; int ret; diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c index ee469c49c5..ebb5235521 100644 --- a/target-arm/arm-semi.c +++ b/target-arm/arm-semi.c @@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #endif if (ret == (target_ulong)-1) { @@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0); env->regs[0] = be32_to_cpu(size); #ifdef CONFIG_USER_ONLY - ((TaskState *)env->opaque)->swi_errno = err; + ((TaskState *)cs->opaque)->swi_errno = err; #else syscall_err = err; #endif @@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err) uint32_t do_arm_semihosting(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); + CPUState *cs = CPU(cpu); target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) uint32_t ret; uint32_t len; #ifdef CONFIG_USER_ONLY - TaskState *ts = env->opaque; + TaskState *ts = cs->opaque; #else CPUARMState *ts = env; #endif @@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env) exit(0); default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); - cpu_dump_state(CPU(cpu), stderr, fprintf, 0); + cpu_dump_state(cs, stderr, fprintf, 0); abort(); } } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 94c4983813..2dea3cac90 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -428,7 +428,8 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) case HOSTED_INIT_SIM: #if defined(CONFIG_USER_ONLY) { - TaskState *ts = env->opaque; + CPUState *cs = CPU(m68k_env_get_cpu(env)); + TaskState *ts = cs->opaque; /* Allocate the heap using sbrk. */ if (!ts->heap_limit) { abi_ulong ret; -- cgit v1.2.3-55-g7522 From ff4700b05cfb305a880762c288b88ca01c782352 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 18:23:18 +0200 Subject: cpu: Move watchpoint fields from CPU_COMMON to CPUState Signed-off-by: Andreas Färber --- cpu-exec.c | 5 +++-- exec.c | 33 ++++++++++++++++++++------------- gdbstub.c | 8 ++++---- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 10 ++++++++++ linux-user/main.c | 5 +++-- target-i386/cpu.h | 2 +- target-i386/helper.c | 7 ++++--- target-i386/kvm.c | 8 ++++---- target-lm32/cpu.h | 2 +- target-lm32/helper.c | 7 ++++--- target-xtensa/cpu.h | 2 +- target-xtensa/helper.c | 8 +++++--- 13 files changed, 60 insertions(+), 47 deletions(-) (limited to 'linux-user') diff --git a/cpu-exec.c b/cpu-exec.c index 798dc084d9..d7c21d35e5 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -200,10 +200,11 @@ void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler) static void cpu_handle_debug_exception(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp; - if (!env->watchpoint_hit) { - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + if (!cpu->watchpoint_hit) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { wp->flags &= ~BP_WATCHPOINT_HIT; } } diff --git a/exec.c b/exec.c index 26ed9ccd0c..ee5eff7734 100644 --- a/exec.c +++ b/exec.c @@ -485,7 +485,7 @@ void cpu_exec_init(CPUArchState *env) cpu->cpu_index = cpu_index; cpu->numa_node = 0; QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; cpu->thread_id = qemu_get_thread_id(); @@ -542,6 +542,7 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, int flags, CPUWatchpoint **watchpoint) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; @@ -559,10 +560,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len wp->flags = flags; /* keep all GDB-injected watchpoints in front */ - if (flags & BP_GDB) - QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry); - else - QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry); + if (flags & BP_GDB) { + QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry); + } else { + QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry); + } tlb_flush_page(env, addr); @@ -575,10 +577,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, int flags) { + CPUState *cpu = ENV_GET_CPU(env); target_ulong len_mask = ~(len - 1); CPUWatchpoint *wp; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { cpu_watchpoint_remove_by_ref(env, wp); @@ -591,7 +594,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len /* Remove a specific watchpoint by reference. */ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) { - QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); + + QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); tlb_flush_page(env, watchpoint->vaddr); @@ -601,9 +606,10 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) /* Remove all matching watchpoints. */ void cpu_watchpoint_remove_all(CPUArchState *env, int mask) { + CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp, *next; - QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) { + QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { if (wp->flags & mask) cpu_watchpoint_remove_by_ref(env, wp); } @@ -799,6 +805,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, int prot, target_ulong *address) { + CPUState *cpu = ENV_GET_CPU(env); hwaddr iotlb; CPUWatchpoint *wp; @@ -818,7 +825,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env, /* Make accesses to pages with watchpoints go via the watchpoint trap routines. */ - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) { /* Avoid trapping reads of pages with a write breakpoint. */ if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) { @@ -1579,7 +1586,7 @@ static void check_watchpoint(int offset, int len_mask, int flags) CPUWatchpoint *wp; int cpu_flags; - if (env->watchpoint_hit) { + if (cpu->watchpoint_hit) { /* We re-entered the check after replacing the TB. Now raise * the debug interrupt so that is will trigger after the * current instruction. */ @@ -1587,12 +1594,12 @@ static void check_watchpoint(int offset, int len_mask, int flags) return; } vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset; - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if ((vaddr == (wp->vaddr & len_mask) || (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) { wp->flags |= BP_WATCHPOINT_HIT; - if (!env->watchpoint_hit) { - env->watchpoint_hit = wp; + if (!cpu->watchpoint_hit) { + cpu->watchpoint_hit = wp; tb_check_watchpoint(env); if (wp->flags & BP_STOP_BEFORE_ACCESS) { cpu->exception_index = EXCP_DEBUG; diff --git a/gdbstub.c b/gdbstub.c index c5ab73fb1d..0176b3f80e 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1204,8 +1204,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) } switch (state) { case RUN_STATE_DEBUG: - if (env->watchpoint_hit) { - switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) { + if (cpu->watchpoint_hit) { + switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { case BP_MEM_READ: type = "r"; break; @@ -1219,8 +1219,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state) snprintf(buf, sizeof(buf), "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", GDB_SIGNAL_TRAP, cpu_index(cpu), type, - env->watchpoint_hit->vaddr); - env->watchpoint_hit = NULL; + (target_ulong)cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit = NULL; goto send_packet; } tb_flush(env); diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 8af85476fc..31aac691c5 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -120,13 +120,6 @@ typedef struct CPUBreakpoint { QTAILQ_ENTRY(CPUBreakpoint) entry; } CPUBreakpoint; -typedef struct CPUWatchpoint { - target_ulong vaddr; - target_ulong len_mask; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUWatchpoint) entry; -} CPUWatchpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ @@ -135,8 +128,5 @@ typedef struct CPUWatchpoint { /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ - \ - QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ - CPUWatchpoint *watchpoint_hit; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4d1ea35ca4..c7420e070b 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,13 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUWatchpoint { + vaddr vaddr; + vaddr len_mask; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUWatchpoint) entry; +} CPUWatchpoint; + struct KVMState; struct kvm_run; @@ -231,6 +238,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; + CPUWatchpoint *watchpoint_hit; + void *opaque; /* In order to avoid passing too many arguments to the MMIO helpers, diff --git a/linux-user/main.c b/linux-user/main.c index 6e62b8babd..5a06192ec4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3435,6 +3435,7 @@ void init_task_state(TaskState *ts) CPUArchState *cpu_copy(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; @@ -3450,12 +3451,12 @@ CPUArchState *cpu_copy(CPUArchState *env) Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ QTAILQ_INIT(&env->breakpoints); - QTAILQ_INIT(&env->watchpoints); + QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &env->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } - QTAILQ_FOREACH(wp, &env->watchpoints, entry) { + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62641af77e..906018757d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -876,7 +876,7 @@ typedef struct CPUX86State { target_ulong dr[8]; /* debug registers */ union { CPUBreakpoint *cpu_breakpoint[4]; - CPUWatchpoint *cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; int old_exception; /* exception in flight */ diff --git a/target-i386/helper.c b/target-i386/helper.c index 6d9bd71a3a..bd8da20946 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1088,11 +1088,12 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) void breakpoint_handler(CPUX86State *env) { + CPUState *cs = CPU(x86_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_hw_breakpoints(env, false)) { raise_exception(env, EXCP01_DB); } else { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e555040a97..7a295f6f20 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -2277,13 +2277,13 @@ static int kvm_handle_debug(X86CPU *cpu, break; case 0x1: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - env->watchpoint_hit = &hw_watchpoint; + cs->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -2291,11 +2291,11 @@ static int kvm_handle_debug(X86CPU *cpu, } } } - } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(CPU(cpu)); + cpu_synchronize_state(cs); assert(env->exception_injected == -1); /* pass to guest */ diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index b94d9b007e..d50726bce7 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -167,7 +167,7 @@ struct CPULM32State { uint32_t wp[4]; /* watchpoints */ CPUBreakpoint * cpu_breakpoint[4]; - CPUWatchpoint * cpu_watchpoint[4]; + struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON diff --git a/target-lm32/helper.c b/target-lm32/helper.c index e5536c0ecb..67ba278e27 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -118,11 +118,12 @@ static bool check_watchpoints(CPULM32State *env) void lm32_debug_excp_handler(CPULM32State *env) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { - env->watchpoint_hit = NULL; + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit = NULL; if (check_watchpoints(env)) { raise_exception(env, EXCP_WATCHPOINT); } else { diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 4bae693c6d..e210bacdff 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -359,7 +359,7 @@ typedef struct CPUXtensaState { int exception_taken; /* Watchpoints for DBREAK registers */ - CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; CPU_COMMON } CPUXtensaState; diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 259878837f..8a9cb0a825 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -81,11 +81,13 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env) void xtensa_breakpoint_handler(CPUXtensaState *env) { - if (env->watchpoint_hit) { - if (env->watchpoint_hit->flags & BP_CPU) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { uint32_t cause; - env->watchpoint_hit = NULL; + cs->watchpoint_hit = NULL; cause = check_hw_breakpoints(env); if (cause) { debug_exception_env(env, cause); -- cgit v1.2.3-55-g7522 From f0c3c505a8ec1a948006b3a16a35864a2270a84b Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 26 Aug 2013 21:22:53 +0200 Subject: cpu: Move breakpoints field from CPU_COMMON to CPUState Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber --- exec.c | 21 +++++++++++++-------- include/exec/cpu-defs.h | 10 ---------- include/qom/cpu.h | 9 +++++++++ linux-user/main.c | 4 ++-- target-alpha/translate.c | 4 ++-- target-arm/cpu.c | 2 +- target-arm/translate-a64.c | 4 ++-- target-arm/translate.c | 4 ++-- target-cris/cpu.c | 2 +- target-cris/cpu.h | 4 ++-- target-cris/translate.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/cpu.h | 3 ++- target-i386/helper.c | 3 ++- target-i386/translate.c | 4 ++-- target-lm32/cpu.c | 2 +- target-lm32/cpu.h | 3 ++- target-lm32/helper.c | 2 +- target-lm32/translate.c | 5 +++-- target-m68k/cpu.c | 2 +- target-m68k/cpu.h | 1 + target-m68k/translate.c | 4 ++-- target-microblaze/cpu.c | 2 +- target-microblaze/translate.c | 5 +++-- target-mips/cpu.c | 2 +- target-mips/cpu.h | 1 + target-mips/translate.c | 4 ++-- target-moxie/cpu.c | 2 +- target-moxie/translate.c | 4 ++-- target-openrisc/cpu.c | 6 +++++- target-openrisc/cpu.h | 1 + target-openrisc/translate.c | 5 +++-- target-ppc/translate.c | 4 ++-- target-s390x/cpu.c | 4 ++-- target-s390x/translate.c | 4 ++-- target-sh4/cpu.c | 2 +- target-sh4/cpu.h | 1 + target-sh4/translate.c | 4 ++-- target-sparc/cpu.c | 2 +- target-sparc/cpu.h | 1 + target-sparc/translate.c | 4 ++-- target-unicore32/translate.c | 4 ++-- target-xtensa/translate.c | 5 +++-- 43 files changed, 94 insertions(+), 73 deletions(-) (limited to 'linux-user') diff --git a/exec.c b/exec.c index ee5eff7734..6d9e13a0a6 100644 --- a/exec.c +++ b/exec.c @@ -484,7 +484,7 @@ void cpu_exec_init(CPUArchState *env) } cpu->cpu_index = cpu_index; cpu->numa_node = 0; - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #ifndef CONFIG_USER_ONLY cpu->as = &address_space_memory; @@ -621,6 +621,7 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -630,12 +631,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, /* keep all GDB-injected breakpoints in front */ if (flags & BP_GDB) { - QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry); + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry); } else { - QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry); + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } - breakpoint_invalidate(ENV_GET_CPU(env), pc); + breakpoint_invalidate(cpu, pc); if (breakpoint) { *breakpoint = bp; @@ -650,9 +651,10 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { cpu_breakpoint_remove_by_ref(env, bp); return 0; @@ -668,9 +670,11 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry); + CPUState *cpu = ENV_GET_CPU(env); - breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc); + QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); + + breakpoint_invalidate(cpu, breakpoint->pc); g_free(breakpoint); #endif @@ -680,9 +684,10 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) void cpu_breakpoint_remove_all(CPUArchState *env, int mask) { #if defined(TARGET_HAS_ICE) + CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp, *next; - QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) { + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { if (bp->flags & mask) cpu_breakpoint_remove_by_ref(env, bp); } diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 31aac691c5..2dd6206d4a 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -114,19 +114,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); #endif -typedef struct CPUBreakpoint { - target_ulong pc; - int flags; /* BP_* */ - QTAILQ_ENTRY(CPUBreakpoint) entry; -} CPUBreakpoint; - #define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ /* soft mmu support */ \ CPU_COMMON_TLB \ - \ - /* from this point: preserved by CPU reset */ \ - /* ice debug support */ \ - QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c7420e070b..3bbda08eac 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -151,6 +151,12 @@ typedef struct icount_decr_u16 { } icount_decr_u16; #endif +typedef struct CPUBreakpoint { + vaddr pc; + int flags; /* BP_* */ + QTAILQ_ENTRY(CPUBreakpoint) entry; +} CPUBreakpoint; + typedef struct CPUWatchpoint { vaddr vaddr; vaddr len_mask; @@ -238,6 +244,9 @@ struct CPUState { int gdb_num_g_regs; QTAILQ_ENTRY(CPUState) node; + /* ice debug support */ + QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; + QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; CPUWatchpoint *watchpoint_hit; diff --git a/linux-user/main.c b/linux-user/main.c index 5a06192ec4..dbc04b7d0f 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3450,10 +3450,10 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Clone all break/watchpoints. Note: Once we support ptrace with hw-debug register access, make sure BP_CPU break/watchpoints are handled correctly on clone. */ - QTAILQ_INIT(&env->breakpoints); + QTAILQ_INIT(&cpu->breakpoints); QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4c94bed704..a9ef1a7507 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3463,8 +3463,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { gen_excp(&ctx, EXCP_DEBUG, 0); break; diff --git a/target-arm/cpu.c b/target-arm/cpu.c index be17d72537..ecd0b7ecde 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -82,7 +82,7 @@ static void arm_cpu_reset(CPUState *s) acc->parent_reset(s); - memset(env, 0, offsetof(CPUARMState, breakpoints)); + memset(env, 0, offsetof(CPUARMState, features)); g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 37e05e81f7..2fd9113628 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -9061,8 +9061,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_clear_temp_count(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-arm/translate.c b/target-arm/translate.c index df259debcc..2f02c183a7 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10733,8 +10733,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } #endif - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception_insn(dc, 0, EXCP_DEBUG); /* Advance PC so that clearing the breakpoint will diff --git a/target-cris/cpu.c b/target-cris/cpu.c index ff27e7f773..95b6a8889b 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -49,7 +49,7 @@ static void cris_cpu_reset(CPUState *s) ccc->parent_reset(s); vr = env->pregs[PR_VR]; - memset(env, 0, offsetof(CPUCRISState, breakpoints)); + memset(env, 0, offsetof(CPUCRISState, load_info)); env->pregs[PR_VR] = vr; tlb_flush(env, 1); diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 6cc0616523..b88c147518 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -171,8 +171,8 @@ typedef struct CPUCRISState { CPU_COMMON - /* Members after CPU_COMMON are preserved across resets. */ - void *load_info; + /* Members from load_info on are preserved across resets. */ + void *load_info; } CPUCRISState; #include "cpu-qom.h" diff --git a/target-cris/translate.c b/target-cris/translate.c index f990d591c7..7e70940c9b 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3089,10 +3089,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) static void check_breakpoint(CPUCRISState *env, DisasContext *dc) { + CPUState *cs = CPU(cris_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 63ba2194cb..fab0f55735 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2410,7 +2410,7 @@ static void x86_cpu_reset(CPUState *s) xcc->parent_reset(s); - memset(env, 0, offsetof(CPUX86State, breakpoints)); + memset(env, 0, offsetof(CPUX86State, pat)); tlb_flush(env, 1); diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 906018757d..4d1374c6cc 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -875,7 +875,7 @@ typedef struct CPUX86State { target_ulong exception_next_eip; target_ulong dr[8]; /* debug registers */ union { - CPUBreakpoint *cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; }; /* break/watchpoints for dr[0..3] */ uint32_t smbase; @@ -887,6 +887,7 @@ typedef struct CPUX86State { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint64_t pat; /* processor features (e.g. for CPUID insn) */ diff --git a/target-i386/helper.c b/target-i386/helper.c index bd8da20946..59736d7a4f 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1101,7 +1101,7 @@ void breakpoint_handler(CPUX86State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->eip) { if (bp->flags & BP_CPU) { check_hw_breakpoints(env, true); @@ -1109,6 +1109,7 @@ void breakpoint_handler(CPUX86State *env) } break; } + } } } diff --git a/target-i386/translate.c b/target-i386/translate.c index 707ebd5ca0..02625e31c2 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7965,8 +7965,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu, gen_tb_start(); for(;;) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == pc_ptr && !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) { gen_debug(dc, pc_ptr - dc->cs_base); diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index daec499502..d0c66bc0f5 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -125,7 +125,7 @@ static void lm32_cpu_reset(CPUState *s) lcc->parent_reset(s); /* reset cpu state */ - memset(env, 0, offsetof(CPULM32State, breakpoints)); + memset(env, 0, offsetof(CPULM32State, eba)); lm32_cpu_init_cfg_reg(cpu); tlb_flush(env, 1); diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index d50726bce7..24bde78502 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -166,11 +166,12 @@ struct CPULM32State { uint32_t bp[4]; /* breakpoints */ uint32_t wp[4]; /* watchpoints */ - CPUBreakpoint * cpu_breakpoint[4]; + struct CPUBreakpoint *cpu_breakpoint[4]; struct CPUWatchpoint *cpu_watchpoint[4]; CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t eba; /* exception base address */ uint32_t deba; /* debug exception base address */ diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 67ba278e27..eadc7277a7 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -131,7 +131,7 @@ void lm32_debug_excp_handler(CPULM32State *env) } } } else { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == env->pc) { if (bp->flags & BP_CPU) { raise_exception(env, EXCP_BREAKPOINT); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 80bffc7b27..c8abd1f27e 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1037,10 +1037,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPULM32State *env, DisasContext *dc) { + CPUState *cs = CPU(lm32_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); t_gen_raise_exception(dc, EXCP_DEBUG); diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 46601dcd5d..a88da20b46 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -49,7 +49,7 @@ static void m68k_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUM68KState, breakpoints)); + memset(env, 0, offsetof(CPUM68KState, features)); #if !defined(CONFIG_USER_ONLY) env->sr = 0x2700; #endif diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index dd1794feac..6e4001d523 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -110,6 +110,7 @@ typedef struct CPUM68KState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ uint32_t features; } CPUM68KState; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 4f06443532..a0e2f19e15 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3003,8 +3003,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, do { pc_offset = dc->pc - pc_start; gen_throws_exception = NULL; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_exception(dc, dc->pc, EXCP_DEBUG); dc->is_jmp = DISAS_JUMP; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 86ec25811e..3177fe6d12 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -63,7 +63,7 @@ static void mb_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMBState, breakpoints)); + memset(env, 0, sizeof(CPUMBState)); env->res_addr = RES_ADDR_NONE; tlb_flush(env, 1); diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 270138c6d2..fbd6951d1a 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1660,10 +1660,11 @@ static inline void decode(DisasContext *dc, uint32_t ir) static void check_breakpoint(CPUMBState *env, DisasContext *dc) { + CPUState *cs = CPU(mb_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { t_gen_raise_exception(dc, EXCP_DEBUG); dc->is_jmp = DISAS_UPDATE; diff --git a/target-mips/cpu.c b/target-mips/cpu.c index 8c304ac832..cf4d856d6b 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -83,7 +83,7 @@ static void mips_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMIPSState, breakpoints)); + memset(env, 0, offsetof(CPUMIPSState, mvp)); tlb_flush(env, 1); cpu_state_reset(env); diff --git a/target-mips/cpu.h b/target-mips/cpu.h index a1d85efea1..3ba3229e66 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -482,6 +482,7 @@ struct CPUMIPSState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; diff --git a/target-mips/translate.c b/target-mips/translate.c index d1c25d2b22..71dccaea55 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15613,8 +15613,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); gen_tb_start(); while (ctx.bstate == BS_NONE) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 03d8eb13d7..14d1a24438 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -42,7 +42,7 @@ static void moxie_cpu_reset(CPUState *s) mcc->parent_reset(s); - memset(env, 0, offsetof(CPUMoxieState, breakpoints)); + memset(env, 0, sizeof(CPUMoxieState)); env->pc = 0x1000; tlb_flush(env, 1); diff --git a/target-moxie/translate.c b/target-moxie/translate.c index a93196f47b..63f889fd7f 100644 --- a/target-moxie/translate.c +++ b/target-moxie/translate.c @@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { tcg_gen_movi_i32(cpu_pc, ctx.pc); gen_helper_debug(cpu_env); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index b601de009c..a00369bef5 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -41,7 +41,11 @@ static void openrisc_cpu_reset(CPUState *s) occ->parent_reset(s); - memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints)); +#ifndef CONFIG_USER_ONLY + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb)); +#else + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq)); +#endif tlb_flush(&cpu->env, 1); /*tb_flush(&cpu->env); FIXME: Do we need it? */ diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 660bb4f1e7..4512f459bf 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ #ifndef CONFIG_USER_ONLY CPUOpenRISCTLBContext * tlb; diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index 776cb6eece..852b5e6107 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1619,10 +1619,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc) { + CPUState *cs = CPU(cpu); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) { - QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_tl(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 91c33dcd1d..e3fcb03c26 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -11377,8 +11377,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, /* Set env in case of segfault during code fetch */ while (ctx.exception == POWERPC_EXCP_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == ctx.nip) { gen_debug_exception(ctxp); break; diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 993d924e52..ae78ebc5f7 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -109,7 +109,7 @@ static void s390_cpu_initial_reset(CPUState *s) s390_cpu_reset(s); /* initial reset does not touch regs,fregs and aregs */ - memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) - offsetof(CPUS390XState, fpc)); /* architectured initial values for CR 0 and 14 */ @@ -139,7 +139,7 @@ static void s390_cpu_full_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); + memset(env, 0, offsetof(CPUS390XState, cpu_num)); /* architectured initial values for CR 0 and 14 */ env->cregs[0] = CR0_RESET; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bc99a378a7..81b7e330ab 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -4795,8 +4795,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu, } status = NO_EXIT; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc.pc) { status = EXIT_PC_STALE; do_debug = true; diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 88960c8512..4e0e2179cc 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -53,7 +53,7 @@ static void superh_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSH4State, breakpoints)); + memset(env, 0, offsetof(CPUSH4State, id)); tlb_flush(env, 1); env->pc = 0xA0000000; diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index a85571087d..a2e9e2c031 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -175,6 +175,7 @@ typedef struct CPUSH4State { CPU_COMMON + /* Fields from here on are preserved over CPU reset. */ int id; /* CPU model */ /* The features that we should emulate. See sh_features above. */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 661fc6c887..2360609a0a 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1889,8 +1889,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb, max_insns = CF_COUNT_MASK; gen_tb_start(); while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (ctx.pc == bp->pc) { /* We have hit a breakpoint - make sure PC is up-to-date */ tcg_gen_movi_i32(cpu_pc, ctx.pc); diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 3e6e7a754e..8465a0b18a 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUSPARCState, breakpoints)); + memset(env, 0, offsetof(CPUSPARCState, version)); tlb_flush(env, 1); env->cwp = 0; #ifndef TARGET_SPARC64 diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 893caa0576..f72451d53e 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -423,6 +423,7 @@ struct CPUSPARCState { CPU_COMMON + /* Fields from here on are preserved across CPU reset. */ target_ulong version; uint32_t nwindows; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 46d7859e97..2de1c4a58d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5270,8 +5270,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, max_insns = CF_COUNT_MASK; gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { if (dc->pc != pc_start) save_state(dc); diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 4572890ffa..5032bbe2a0 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1922,8 +1922,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, gen_tb_start(); do { - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { gen_set_pc_im(dc->pc); gen_exception(EXCP_DEBUG); diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 9f5895e021..764cee96f3 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2948,10 +2948,11 @@ invalid_opcode: static void check_breakpoint(CPUXtensaState *env, DisasContext *dc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); CPUBreakpoint *bp; - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) { - QTAILQ_FOREACH(bp, &env->breakpoints, entry) { + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { tcg_gen_movi_i32(cpu_pc, dc->pc); gen_exception(dc, EXCP_DEBUG); -- cgit v1.2.3-55-g7522 From 75a34036d43dc961cbef2a4705682d0666caf384 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 2 Sep 2013 16:57:02 +0200 Subject: exec: Change cpu_watchpoint_{insert,remove{,_by_ref,_all}} argument Use CPUState. This lets us drop a few local env usages. Signed-off-by: Andreas Färber --- exec.c | 34 +++++++++++++++++----------------- gdbstub.c | 17 +++++++++-------- include/exec/cpu-all.h | 6 ------ include/qom/cpu.h | 7 +++++++ linux-user/main.c | 5 +++-- target-i386/cpu.c | 2 +- target-i386/helper.c | 11 ++++++++--- target-i386/machine.c | 3 ++- target-lm32/helper.c | 7 +++++-- target-xtensa/op_helper.c | 9 ++++++--- 10 files changed, 58 insertions(+), 43 deletions(-) (limited to 'linux-user') diff --git a/exec.c b/exec.c index 6f8b2ca7b8..e89653ecca 100644 --- a/exec.c +++ b/exec.c @@ -33,6 +33,7 @@ #include "hw/xen/xen.h" #include "qemu/timer.h" #include "qemu/config-file.h" +#include "qemu/error-report.h" #include "exec/memory.h" #include "sysemu/dma.h" #include "exec/address-spaces.h" @@ -527,30 +528,30 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) #endif /* TARGET_HAS_ICE */ #if defined(CONFIG_USER_ONLY) -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { } -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { return -ENOSYS; } #else /* Add a watchpoint. */ -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint) { - CPUState *cpu = ENV_GET_CPU(env); - target_ulong len_mask = ~(len - 1); + CPUArchState *env = cpu->env_ptr; + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */ if ((len & (len - 1)) || (addr & ~len_mask) || len == 0 || len > TARGET_PAGE_SIZE) { - fprintf(stderr, "qemu: tried to set invalid watchpoint at " - TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len); + error_report("tried to set invalid watchpoint at %" + VADDR_PRIx ", len=%" VADDR_PRIu, addr, len); return -EINVAL; } wp = g_malloc(sizeof(*wp)); @@ -574,17 +575,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint. */ -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len, +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len, int flags) { - CPUState *cpu = ENV_GET_CPU(env); - target_ulong len_mask = ~(len - 1); + vaddr len_mask = ~(len - 1); CPUWatchpoint *wp; QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { if (addr == wp->vaddr && len_mask == wp->len_mask && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) { - cpu_watchpoint_remove_by_ref(env, wp); + cpu_watchpoint_remove_by_ref(cpu, wp); return 0; } } @@ -592,9 +592,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len } /* Remove a specific watchpoint by reference. */ -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint) { - CPUState *cpu = ENV_GET_CPU(env); + CPUArchState *env = cpu->env_ptr; QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry); @@ -604,14 +604,14 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint) } /* Remove all matching watchpoints. */ -void cpu_watchpoint_remove_all(CPUArchState *env, int mask) +void cpu_watchpoint_remove_all(CPUState *cpu, int mask) { - CPUState *cpu = ENV_GET_CPU(env); CPUWatchpoint *wp, *next; QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) { - if (wp->flags & mask) - cpu_watchpoint_remove_by_ref(env, wp); + if (wp->flags & mask) { + cpu_watchpoint_remove_by_ref(cpu, wp); + } } } #endif diff --git a/gdbstub.c b/gdbstub.c index 0176b3f80e..cd10781c13 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -657,8 +657,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type], + err = cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type[type], NULL); if (err) break; @@ -695,8 +694,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_WATCHPOINT_READ: case GDB_WATCHPOINT_ACCESS: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]); + err = cpu_watchpoint_remove(cpu, addr, len, xlat_gdb_type[type]); if (err) break; } @@ -721,7 +719,7 @@ static void gdb_breakpoint_remove_all(void) env = cpu->env_ptr; cpu_breakpoint_remove_all(env, BP_GDB); #ifndef CONFIG_USER_ONLY - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); #endif } } @@ -1593,13 +1591,16 @@ int gdbserver_start(int port) /* Disable gdb stub for child processes. */ void gdbserver_fork(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); GDBState *s = gdbserver_state; - if (gdbserver_fd < 0 || s->fd < 0) - return; + + if (gdbserver_fd < 0 || s->fd < 0) { + return; + } close(s->fd); s->fd = -1; cpu_breakpoint_remove_all(env, BP_GDB); - cpu_watchpoint_remove_all(env, BP_GDB); + cpu_watchpoint_remove_all(cpu, BP_GDB); } #else static int gdb_chr_can_receive(void *opaque) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4cb4b4a53a..ea90aee7fe 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -427,12 +427,6 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); void cpu_breakpoint_remove_all(CPUArchState *env, int mask); -int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len, - int flags, CPUWatchpoint **watchpoint); -int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, - target_ulong len, int flags); -void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint); -void cpu_watchpoint_remove_all(CPUArchState *env, int mask); #if !defined(CONFIG_USER_ONLY) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 3bbda08eac..4127438507 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -595,6 +595,13 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, + int flags, CPUWatchpoint **watchpoint); +int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, + vaddr len, int flags); +void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); +void cpu_watchpoint_remove_all(CPUState *cpu, int mask); + #ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common; #else diff --git a/linux-user/main.c b/linux-user/main.c index dbc04b7d0f..280e295de7 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3437,13 +3437,14 @@ CPUArchState *cpu_copy(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); CPUArchState *new_env = cpu_init(cpu_model); + CPUState *new_cpu = ENV_GET_CPU(new_env); #if defined(TARGET_HAS_ICE) CPUBreakpoint *bp; CPUWatchpoint *wp; #endif /* Reset non arch specific state */ - cpu_reset(ENV_GET_CPU(new_env)); + cpu_reset(new_cpu); memcpy(new_env, env, sizeof(CPUArchState)); @@ -3457,7 +3458,7 @@ CPUArchState *cpu_copy(CPUArchState *env) cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1, + cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1, wp->flags, NULL); } #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index fab0f55735..a35f7bcb22 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2474,7 +2474,7 @@ static void x86_cpu_reset(CPUState *s) env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_watchpoint_remove_all(s, BP_CPU); env->tsc_adjust = 0; env->tsc = 0; diff --git a/target-i386/helper.c b/target-i386/helper.c index cb29aa4b0e..dd6d824010 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -993,6 +993,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void hw_breakpoint_insert(CPUX86State *env, int index) { + CPUState *cs = CPU(x86_env_get_cpu(env)); int type = 0, err = 0; switch (hw_breakpoint_type(env->dr[7], index)) { @@ -1014,7 +1015,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) } if (type != 0) { - err = cpu_watchpoint_insert(env, env->dr[index], + err = cpu_watchpoint_insert(cs, env->dr[index], hw_breakpoint_len(env->dr[7], index), type, &env->cpu_watchpoint[index]); } @@ -1026,8 +1027,12 @@ void hw_breakpoint_insert(CPUX86State *env, int index) void hw_breakpoint_remove(CPUX86State *env, int index) { - if (!env->cpu_breakpoint[index]) + CPUState *cs; + + if (!env->cpu_breakpoint[index]) { return; + } + cs = CPU(x86_env_get_cpu(env)); switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { @@ -1036,7 +1041,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index) break; case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); break; case DR7_TYPE_IO_RW: /* No support for I/O watchpoints yet */ diff --git a/target-i386/machine.c b/target-i386/machine.c index d548c055a9..d49398c2eb 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -290,6 +290,7 @@ static void cpu_pre_save(void *opaque) static int cpu_post_load(void *opaque, int version_id) { X86CPU *cpu = opaque; + CPUState *cs = CPU(cpu); CPUX86State *env = &cpu->env; int i; @@ -320,7 +321,7 @@ static int cpu_post_load(void *opaque, int version_id) } cpu_breakpoint_remove_all(env, BP_CPU); - cpu_watchpoint_remove_all(env, BP_CPU); + cpu_watchpoint_remove_all(cs, BP_CPU); for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); } diff --git a/target-lm32/helper.c b/target-lm32/helper.c index eadc7277a7..863337588f 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -69,6 +69,7 @@ void lm32_breakpoint_remove(CPULM32State *env, int idx) void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, lm32_wp_t wp_type) { + LM32CPU *cpu = lm32_env_get_cpu(env); int flags = 0; switch (wp_type) { @@ -87,18 +88,20 @@ void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address, } if (flags != 0) { - cpu_watchpoint_insert(env, address, 1, flags, + cpu_watchpoint_insert(CPU(cpu), address, 1, flags, &env->cpu_watchpoint[idx]); } } void lm32_watchpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_watchpoint[idx]) { return; } - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]); + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]); env->cpu_watchpoint[idx] = NULL; } diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 8233443eb0..07b00a4335 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -790,11 +790,12 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { + CPUState *cs = CPU(xtensa_env_get_cpu(env)); int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; uint32_t mask = dbreakc | ~DBREAKC_MASK; if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); } if (dbreakc & DBREAKC_SB) { flags |= BP_MEM_WRITE; @@ -808,7 +809,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, /* cut mask after the first zero bit */ mask = 0xffffffff << (32 - clo32(mask)); } - if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1, + if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, flags, &env->cpu_watchpoint[i])) { env->cpu_watchpoint[i] = NULL; qemu_log("Failed to set data breakpoint at 0x%08x/%d\n", @@ -834,7 +835,9 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) set_dbreak(env, i, env->sregs[DBREAKA + i], v); } else { if (env->cpu_watchpoint[i]) { - cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]); + CPUState *cs = CPU(xtensa_env_get_cpu(env)); + + cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]); env->cpu_watchpoint[i] = NULL; } } -- cgit v1.2.3-55-g7522 From b3310ab3380995af2c640a3ffd82f6e7b352c9e6 Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Mon, 2 Sep 2013 17:26:20 +0200 Subject: exec: Change cpu_breakpoint_{insert,remove{,_by_ref,_all}} argument Use CPUState. Allows to clean up CPUArchState in gdbstub. Signed-off-by: Andreas Färber --- exec.c | 20 ++++++++------------ gdbstub.c | 20 ++++++++------------ include/exec/cpu-all.h | 15 --------------- include/qom/cpu.h | 15 +++++++++++++++ linux-user/main.c | 2 +- target-i386/cpu.c | 2 +- target-i386/helper.c | 4 ++-- target-i386/machine.c | 2 +- target-lm32/helper.c | 9 +++++++-- 9 files changed, 43 insertions(+), 46 deletions(-) (limited to 'linux-user') diff --git a/exec.c b/exec.c index e89653ecca..03ae5fe661 100644 --- a/exec.c +++ b/exec.c @@ -617,11 +617,10 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask) #endif /* Add a breakpoint. */ -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; bp = g_malloc(sizeof(*bp)); @@ -648,15 +647,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, } /* Remove a specific breakpoint. */ -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == pc && bp->flags == flags) { - cpu_breakpoint_remove_by_ref(env, bp); + cpu_breakpoint_remove_by_ref(cpu, bp); return 0; } } @@ -667,11 +665,9 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags) } /* Remove a specific breakpoint by reference. */ -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); - QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry); breakpoint_invalidate(cpu, breakpoint->pc); @@ -681,15 +677,15 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint) } /* Remove all matching breakpoints. */ -void cpu_breakpoint_remove_all(CPUArchState *env, int mask) +void cpu_breakpoint_remove_all(CPUState *cpu, int mask) { #if defined(TARGET_HAS_ICE) - CPUState *cpu = ENV_GET_CPU(env); CPUBreakpoint *bp, *next; QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) { - if (bp->flags & mask) - cpu_breakpoint_remove_by_ref(env, bp); + if (bp->flags & mask) { + cpu_breakpoint_remove_by_ref(cpu, bp); + } } #endif } diff --git a/gdbstub.c b/gdbstub.c index cd10781c13..8afe0b701c 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -635,7 +635,6 @@ static const int xlat_gdb_type[] = { static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -646,10 +645,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL); - if (err) + err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -672,7 +671,6 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) { CPUState *cpu; - CPUArchState *env; int err = 0; if (kvm_enabled()) { @@ -683,10 +681,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) case GDB_BREAKPOINT_SW: case GDB_BREAKPOINT_HW: CPU_FOREACH(cpu) { - env = cpu->env_ptr; - err = cpu_breakpoint_remove(env, addr, BP_GDB); - if (err) + err = cpu_breakpoint_remove(cpu, addr, BP_GDB); + if (err) { break; + } } return err; #ifndef CONFIG_USER_ONLY @@ -708,7 +706,6 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) static void gdb_breakpoint_remove_all(void) { CPUState *cpu; - CPUArchState *env; if (kvm_enabled()) { kvm_remove_all_breakpoints(gdbserver_state->c_cpu); @@ -716,8 +713,7 @@ static void gdb_breakpoint_remove_all(void) } CPU_FOREACH(cpu) { - env = cpu->env_ptr; - cpu_breakpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); #ifndef CONFIG_USER_ONLY cpu_watchpoint_remove_all(cpu, BP_GDB); #endif @@ -1599,7 +1595,7 @@ void gdbserver_fork(CPUArchState *env) } close(s->fd); s->fd = -1; - cpu_breakpoint_remove_all(env, BP_GDB); + cpu_breakpoint_remove_all(cpu, BP_GDB); cpu_watchpoint_remove_all(cpu, BP_GDB); } #else diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index ea90aee7fe..6bcadb4e51 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -413,21 +413,6 @@ void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) | CPU_INTERRUPT_TGT_EXT_3 \ | CPU_INTERRUPT_TGT_EXT_4) -/* Breakpoint/watchpoint flags */ -#define BP_MEM_READ 0x01 -#define BP_MEM_WRITE 0x02 -#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) -#define BP_STOP_BEFORE_ACCESS 0x04 -#define BP_WATCHPOINT_HIT 0x08 -#define BP_GDB 0x10 -#define BP_CPU 0x20 - -int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags, - CPUBreakpoint **breakpoint); -int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags); -void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint); -void cpu_breakpoint_remove_all(CPUArchState *env, int mask); - #if !defined(CONFIG_USER_ONLY) /* memory API */ diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 4127438507..86698dd183 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -595,6 +595,21 @@ void qemu_init_vcpu(CPUState *cpu); */ void cpu_single_step(CPUState *cpu, int enabled); +/* Breakpoint/watchpoint flags */ +#define BP_MEM_READ 0x01 +#define BP_MEM_WRITE 0x02 +#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) +#define BP_STOP_BEFORE_ACCESS 0x04 +#define BP_WATCHPOINT_HIT 0x08 +#define BP_GDB 0x10 +#define BP_CPU 0x20 + +int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, + CPUBreakpoint **breakpoint); +int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); +void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); +void cpu_breakpoint_remove_all(CPUState *cpu, int mask); + int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, int flags, CPUWatchpoint **watchpoint); int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, diff --git a/linux-user/main.c b/linux-user/main.c index 280e295de7..dc96b2348b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3455,7 +3455,7 @@ CPUArchState *cpu_copy(CPUArchState *env) QTAILQ_INIT(&cpu->watchpoints); #if defined(TARGET_HAS_ICE) QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL); + cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL); } QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1, diff --git a/target-i386/cpu.c b/target-i386/cpu.c index a35f7bcb22..659ec9a11b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2473,7 +2473,7 @@ static void x86_cpu_reset(CPUState *s) memset(env->dr, 0, sizeof(env->dr)); env->dr[6] = DR6_FIXED_1; env->dr[7] = DR7_FIXED_1; - cpu_breakpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); env->tsc_adjust = 0; diff --git a/target-i386/helper.c b/target-i386/helper.c index dd6d824010..ad61062de3 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -999,7 +999,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index) switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU, + err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU, &env->cpu_breakpoint[index]); } break; @@ -1036,7 +1036,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index) switch (hw_breakpoint_type(env->dr[7], index)) { case DR7_TYPE_BP_INST: if (hw_breakpoint_enabled(env->dr[7], index)) { - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]); + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]); } break; case DR7_TYPE_DATA_WR: diff --git a/target-i386/machine.c b/target-i386/machine.c index d49398c2eb..ed159a8c06 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -320,7 +320,7 @@ static int cpu_post_load(void *opaque, int version_id) env->fptags[i] = (env->fptag_vmstate >> i) & 1; } - cpu_breakpoint_remove_all(env, BP_CPU); + cpu_breakpoint_remove_all(cs, BP_CPU); cpu_watchpoint_remove_all(cs, BP_CPU); for (i = 0; i < DR7_MAX_BP; i++) { hw_breakpoint_insert(env, i); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 863337588f..8be5bed2b4 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -53,16 +53,21 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address) { - cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]); + LM32CPU *cpu = lm32_env_get_cpu(env); + + cpu_breakpoint_insert(CPU(cpu), address, BP_CPU, + &env->cpu_breakpoint[idx]); } void lm32_breakpoint_remove(CPULM32State *env, int idx) { + LM32CPU *cpu = lm32_env_get_cpu(env); + if (!env->cpu_breakpoint[idx]) { return; } - cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]); + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]); env->cpu_breakpoint[idx] = NULL; } -- cgit v1.2.3-55-g7522 From a47dddd7348d3e75ad650ef5e2ca9c3b13a600ac Mon Sep 17 00:00:00 2001 From: Andreas Färber Date: Tue, 3 Sep 2013 17:38:47 +0200 Subject: exec: Change cpu_abort() argument to CPUState Signed-off-by: Andreas Färber --- cputlb.c | 2 +- exec.c | 3 +- include/exec/cpu-all.h | 3 -- include/qom/cpu.h | 3 ++ linux-user/m68k-sim.c | 3 +- linux-user/main.c | 80 ++++++++++++++++++++--------------------- target-alpha/helper.c | 2 +- target-arm/helper.c | 35 ++++++++++++------ target-arm/translate.c | 2 +- target-cris/helper.c | 6 ++-- target-cris/translate.c | 4 +-- target-cris/translate_v10.c | 12 +++---- target-i386/seg_helper.c | 8 +++-- target-lm32/helper.c | 2 +- target-m68k/helper.c | 7 ++-- target-m68k/m68k-semi.c | 2 +- target-m68k/translate.c | 16 ++++++--- target-microblaze/helper.c | 4 +-- target-microblaze/translate.c | 32 ++++++++++------- target-mips/op_helper.c | 11 ++++-- target-mips/translate_init.c | 4 ++- target-openrisc/interrupt.c | 2 +- target-ppc/cpu.h | 2 +- target-ppc/excp_helper.c | 48 ++++++++++++------------- target-ppc/kvm.c | 6 ++-- target-ppc/mmu_helper.c | 54 ++++++++++++++++------------ target-ppc/translate_init.c | 5 +-- target-s390x/cc_helper.c | 3 +- target-s390x/fpu_helper.c | 4 ++- target-s390x/helper.c | 23 +++++++----- target-s390x/int_helper.c | 3 +- target-s390x/mem_helper.c | 11 +++--- target-sh4/helper.c | 21 +++++++---- target-sh4/op_helper.c | 4 ++- target-sparc/int32_helper.c | 2 +- target-sparc/int64_helper.c | 2 +- target-unicore32/helper.c | 14 +++----- target-unicore32/softmmu.c | 15 ++++---- target-unicore32/translate.c | 28 +++++++++++++-- target-unicore32/ucf64_helper.c | 3 +- translate-all.c | 16 ++++----- 41 files changed, 301 insertions(+), 206 deletions(-) (limited to 'linux-user') diff --git a/cputlb.c b/cputlb.c index 8a00330db3..22810536f5 100644 --- a/cputlb.c +++ b/cputlb.c @@ -322,7 +322,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) if (cc->do_unassigned_access) { cc->do_unassigned_access(cpu, addr, false, true, 0, 4); } else { - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" + cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); } } diff --git a/exec.c b/exec.c index 82580c5e0d..5224b31e9f 100644 --- a/exec.c +++ b/exec.c @@ -709,9 +709,8 @@ void cpu_single_step(CPUState *cpu, int enabled) #endif } -void cpu_abort(CPUArchState *env, const char *fmt, ...) +void cpu_abort(CPUState *cpu, const char *fmt, ...) { - CPUState *cpu = ENV_GET_CPU(env); va_list ap; va_list ap2; diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6bcadb4e51..fb649a4029 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -360,9 +360,6 @@ int page_check_range(target_ulong start, target_ulong len, int flags); CPUArchState *cpu_copy(CPUArchState *env); -void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) - GCC_FMT_ATTR(2, 3); - /* Flags for use in ENV->INTERRUPT_PENDING. The numbers assigned here are non-sequential in order to preserve diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 86698dd183..06ee2636c3 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -617,6 +617,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); void cpu_watchpoint_remove_all(CPUState *cpu, int mask); +void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + #ifdef CONFIG_SOFTMMU extern const struct VMStateDescription vmstate_cpu_common; #else diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c index d5926eec4b..1994e40000 100644 --- a/linux-user/m68k-sim.c +++ b/linux-user/m68k-sim.c @@ -98,6 +98,7 @@ static int translate_openflags(int flags) #define ARG(x) tswap32(args[x]) void do_m68k_simcall(CPUM68KState *env, int nr) { + M68kCPU *cpu = m68k_env_get_cpu(env); uint32_t *args; args = (uint32_t *)(unsigned long)(env->aregs[7] + 4); @@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr) check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2))); break; default: - cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr); + cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr); } } diff --git a/linux-user/main.c b/linux-user/main.c index dc96b2348b..af924dcc9d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1577,11 +1577,11 @@ void cpu_loop(CPUPPCState *env) /* Just go on */ break; case POWERPC_EXCP_CRITICAL: /* Critical input */ - cpu_abort(env, "Critical interrupt while in user mode. " + cpu_abort(cs, "Critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_MCHECK: /* Machine check exception */ - cpu_abort(env, "Machine check exception while in user mode. " + cpu_abort(cs, "Machine check exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSI: /* Data storage exception */ @@ -1645,7 +1645,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EXTERNAL: /* External input */ - cpu_abort(env, "External interrupt while in user mode. " + cpu_abort(cs, "External interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ALIGN: /* Alignment exception */ @@ -1739,11 +1739,11 @@ void cpu_loop(CPUPPCState *env) } break; case POWERPC_EXCP_TRAP: - cpu_abort(env, "Tried to call a TRAP\n"); + cpu_abort(cs, "Tried to call a TRAP\n"); break; default: /* Should not happen ! */ - cpu_abort(env, "Unknown program exception (%02x)\n", + cpu_abort(cs, "Unknown program exception (%02x)\n", env->error_code); break; } @@ -1759,7 +1759,7 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_SYSCALL: /* System call exception */ - cpu_abort(env, "Syscall exception while in user mode. " + cpu_abort(cs, "Syscall exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ @@ -1771,23 +1771,23 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_DECR: /* Decrementer exception */ - cpu_abort(env, "Decrementer interrupt while in user mode. " + cpu_abort(cs, "Decrementer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ - cpu_abort(env, "Fix interval timer interrupt while in user mode. " + cpu_abort(cs, "Fix interval timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ - cpu_abort(env, "Watchdog timer interrupt while in user mode. " + cpu_abort(cs, "Watchdog timer interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DTLB: /* Data TLB error */ - cpu_abort(env, "Data TLB exception while in user mode. " + cpu_abort(cs, "Data TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ITLB: /* Instruction TLB error */ - cpu_abort(env, "Instruction TLB exception while in user mode. " + cpu_abort(cs, "Instruction TLB exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */ @@ -1799,37 +1799,37 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */ - cpu_abort(env, "Embedded floating-point data IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n"); break; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */ - cpu_abort(env, "Embedded floating-point round IRQ not handled\n"); + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n"); break; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ - cpu_abort(env, "Doorbell interrupt while in user mode. " + cpu_abort(cs, "Doorbell interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ - cpu_abort(env, "Doorbell critical interrupt while in user mode. " + cpu_abort(cs, "Doorbell critical interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RESET: /* System reset exception */ - cpu_abort(env, "Reset interrupt while in user mode. " + cpu_abort(cs, "Reset interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_DSEG: /* Data segment exception */ - cpu_abort(env, "Data segment exception while in user mode. " + cpu_abort(cs, "Data segment exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_ISEG: /* Instruction segment exception */ - cpu_abort(env, "Instruction segment exception " + cpu_abort(cs, "Instruction segment exception " "while in user mode. Aborting\n"); break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ - cpu_abort(env, "Hypervisor decrementer interrupt " + cpu_abort(cs, "Hypervisor decrementer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_TRACE: /* Trace exception */ @@ -1839,19 +1839,19 @@ void cpu_loop(CPUPPCState *env) break; /* PowerPC 64 with hypervisor mode support */ case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ - cpu_abort(env, "Hypervisor data storage exception " + cpu_abort(cs, "Hypervisor data storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */ - cpu_abort(env, "Hypervisor instruction storage exception " + cpu_abort(cs, "Hypervisor instruction storage exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ - cpu_abort(env, "Hypervisor data segment exception " + cpu_abort(cs, "Hypervisor data segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */ - cpu_abort(env, "Hypervisor instruction segment exception " + cpu_abort(cs, "Hypervisor instruction segment exception " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_VPU: /* Vector unavailable exception */ @@ -1863,58 +1863,58 @@ void cpu_loop(CPUPPCState *env) queue_signal(env, info.si_signo, &info); break; case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */ - cpu_abort(env, "Programmable interval timer interrupt " + cpu_abort(cs, "Programmable interval timer interrupt " "while in user mode. Aborting\n"); break; case POWERPC_EXCP_IO: /* IO error exception */ - cpu_abort(env, "IO error exception while in user mode. " + cpu_abort(cs, "IO error exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_RUNM: /* Run mode exception */ - cpu_abort(env, "Run mode exception while in user mode. " + cpu_abort(cs, "Run mode exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ - cpu_abort(env, "Emulation trap exception not handled\n"); + cpu_abort(cs, "Emulation trap exception not handled\n"); break; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ - cpu_abort(env, "Instruction fetch TLB exception " + cpu_abort(cs, "Instruction fetch TLB exception " "while in user-mode. Aborting"); break; case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ - cpu_abort(env, "Data load TLB exception while in user-mode. " + cpu_abort(cs, "Data load TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ - cpu_abort(env, "Data store TLB exception while in user-mode. " + cpu_abort(cs, "Data store TLB exception while in user-mode. " "Aborting"); break; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ - cpu_abort(env, "Floating-point assist exception not handled\n"); + cpu_abort(cs, "Floating-point assist exception not handled\n"); break; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ - cpu_abort(env, "Instruction address breakpoint exception " + cpu_abort(cs, "Instruction address breakpoint exception " "not handled\n"); break; case POWERPC_EXCP_SMI: /* System management interrupt */ - cpu_abort(env, "System management interrupt while in user mode. " + cpu_abort(cs, "System management interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_THERM: /* Thermal interrupt */ - cpu_abort(env, "Thermal interrupt interrupt while in user mode. " + cpu_abort(cs, "Thermal interrupt interrupt while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */ - cpu_abort(env, "Performance monitor exception not handled\n"); + cpu_abort(cs, "Performance monitor exception not handled\n"); break; case POWERPC_EXCP_VPUA: /* Vector assist exception */ - cpu_abort(env, "Vector assist exception not handled\n"); + cpu_abort(cs, "Vector assist exception not handled\n"); break; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ - cpu_abort(env, "Soft patch exception not handled\n"); + cpu_abort(cs, "Soft patch exception not handled\n"); break; case POWERPC_EXCP_MAINT: /* Maintenance exception */ - cpu_abort(env, "Maintenance exception while in user mode. " + cpu_abort(cs, "Maintenance exception while in user mode. " "Aborting\n"); break; case POWERPC_EXCP_STOP: /* stop translation */ @@ -1970,7 +1970,7 @@ void cpu_loop(CPUPPCState *env) /* just indicate that signals should be handled asap */ break; default: - cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr); + cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr); break; } process_pending_signals(env); diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 305dd67b84..fdb033564c 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -452,7 +452,7 @@ void alpha_cpu_do_interrupt(CPUState *cs) } break; default: - cpu_abort(env, "Unhandled CPU exception"); + cpu_abort(cs, "Unhandled CPU exception"); } /* Remember where the exception happened. Emulate real hardware in diff --git a/target-arm/helper.c b/target-arm/helper.c index 0d173ebfcf..0a9c6fc5e2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2671,29 +2671,40 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_msr %d\n", reg); } uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { - cpu_abort(env, "v7m_mrs %d\n", reg); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg); return 0; } void switch_mode(CPUARMState *env, int mode) { - if (mode != ARM_CPU_MODE_USR) - cpu_abort(env, "Tried to switch out of user mode\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + if (mode != ARM_CPU_MODE_USR) { + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + } } void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) { - cpu_abort(env, "banked r13 write\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 write\n"); } uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) { - cpu_abort(env, "banked r13 read\n"); + ARMCPU *cpu = arm_env_get_cpu(env); + + cpu_abort(CPU(cpu), "banked r13 read\n"); return 0; } @@ -2892,7 +2903,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) do_v7m_exception_exit(env); return; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } @@ -3017,7 +3028,7 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } /* High vectors. */ @@ -3695,6 +3706,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ return xpsr_read(env) & 0xf8000000; @@ -3725,13 +3738,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) return env->v7m.control; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register read (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg); return 0; } } void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { + ARMCPU *cpu = arm_env_get_cpu(env); + switch (reg) { case 0: /* APSR */ xpsr_write(env, val, 0xf8000000); @@ -3794,7 +3809,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) break; default: /* ??? For debugging only. */ - cpu_abort(env, "Unimplemented system register write (%d)\n", reg); + cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg); return; } } diff --git a/target-arm/translate.c b/target-arm/translate.c index 2f02c183a7..fbe513b40d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10803,7 +10803,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } diff --git a/target-cris/helper.c b/target-cris/helper.c index d7fdc33647..ec84b57c0b 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -89,7 +89,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, rw, mmu_idx, 0); if (miss) { if (cs->exception_index == EXCP_BUSFAULT) { - cpu_abort(env, + cpu_abort(cs, "CRIS: Illegal recursive bus fault." "addr=%" VADDR_PRIx " rw=%d\n", address, rw); @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) if (env->dslot) { /* CRISv10 never takes interrupts while in a delay-slot. */ - cpu_abort(env, "CRIS: Interrupt on delay-slot\n"); + cpu_abort(cs, "CRIS: Interrupt on delay-slot\n"); } assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); @@ -150,7 +150,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) break; case EXCP_BUSFAULT: - cpu_abort(env, "Unhandled busfault"); + cpu_abort(cs, "Unhandled busfault"); break; default: diff --git a/target-cris/translate.c b/target-cris/translate.c index 7e70940c9b..3e26b9b3c3 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line) { printf("BUG: pc=%x %s %d\n", dc->pc, file, line); qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line); - cpu_abort(dc->env, "%s:%d\n", file, line); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line); } static const char *regnames[] = @@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, break; } default: - cpu_abort(dc->env, "Invalid fetch size %d\n", size); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n", size); break; } return r; diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index d6ef084483..3f27456d19 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) default: LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n", dc->pc, dc->mode, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled quickimm\n"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled quickimm\n"); break; } return 2; @@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc) case 2: tmp = 1; break; case 1: tmp = 0; break; default: - cpu_abort(dc->env, "Unhandled BIAP"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled BIAP"); break; } @@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } } else { @@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc) default: LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } } @@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) default: LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } return insn_len; @@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) break; default: LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode); - cpu_abort(dc->env, "Unhandled opcode"); + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode"); break; } diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 4e134e4338..8c3f92c22b 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector) static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, uint32_t *esp_ptr, int dpl) { + X86CPU *cpu = x86_env_get_cpu(env); int type, index, shift; #if 0 @@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf; if ((type & 7) != 1) { - cpu_abort(env, "invalid tss type"); + cpu_abort(CPU(cpu), "invalid tss type"); } shift = type >> 3; index = (dpl * 4 + 2) << shift; @@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) { + X86CPU *cpu = x86_env_get_cpu(env); int index; #if 0 @@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) #endif if (!(env->tr.flags & DESC_P_MASK)) { - cpu_abort(env, "invalid tss"); + cpu_abort(CPU(cpu), "invalid tss"); } index = 8 * level + 4; if ((index + 7) > env->tr.limit) { diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 7de783b91d..3adfea9ef0 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -185,7 +185,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: - cpu_abort(env, "unhandled exception type=%d\n", + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); break; } diff --git a/target-m68k/helper.c b/target-m68k/helper.c index fb43b81505..276fb4bcc9 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) { + M68kCPU *cpu = m68k_env_get_cpu(env); int flags; uint32_t src; uint32_t dest; @@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) flags |= CCF_C; break; default: - cpu_abort(env, "Bad CC_OP %d", cc_op); + cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op); } env->cc_op = CC_OP_FLAGS; env->cc_dest = flags; @@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op) void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) { + M68kCPU *cpu = m68k_env_get_cpu(env); + switch (reg) { case 0x02: /* CACR */ env->cacr = val; @@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val) break; /* TODO: Implement control registers. */ default: - cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n", + cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); } } diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 2dea3cac90..9dffe8de60 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -461,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) #endif return; default: - cpu_abort(env, "Unsupported semihosting syscall %d\n", nr); + cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr); result = 0; } failed: diff --git a/target-m68k/translate.c b/target-m68k/translate.c index a0e2f19e15..cd662891c8 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -881,8 +881,10 @@ DISAS_INSN(undef_fpu) DISAS_INSN(undef) { + M68kCPU *cpu = m68k_env_get_cpu(env); + gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); - cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2); + cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); } DISAS_INSN(mulw) @@ -2082,12 +2084,14 @@ DISAS_INSN(wddata) DISAS_INSN(wdebug) { + M68kCPU *cpu = m68k_env_get_cpu(env); + if (IS_USER(s)) { gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); return; } /* TODO: Implement wdebug. */ - cpu_abort(env, "WDEBUG not implemented"); + cpu_abort(CPU(cpu), "WDEBUG not implemented"); } DISAS_INSN(trap) @@ -2461,14 +2465,18 @@ DISAS_INSN(fbcc) DISAS_INSN(frestore) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement frestore. */ - cpu_abort(env, "FRESTORE not implemented"); + cpu_abort(CPU(cpu), "FRESTORE not implemented"); } DISAS_INSN(fsave) { + M68kCPU *cpu = m68k_env_get_cpu(env); + /* TODO: Implement fsave. */ - cpu_abort(env, "FSAVE not implemented"); + cpu_abort(CPU(cpu), "FSAVE not implemented"); } static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 48254154d3..11d8aa266d 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -98,7 +98,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, } if (cs->exception_index == EXCP_MMU) { - cpu_abort(env, "recursive faults\n"); + cpu_abort(cs, "recursive faults\n"); } /* TLB miss. */ @@ -259,7 +259,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC] = env->btarget; break; default: - cpu_abort(env, "unhandled exception type=%d\n", + cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); break; } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index fbd6951d1a..4322f171c7 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -370,7 +370,7 @@ static void dec_pattern(DisasContext *dc) } break; default: - cpu_abort(dc->env, + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unsupported pattern insn opcode=%x\n", dc->opcode); break; } @@ -441,6 +441,8 @@ static inline void msr_write(DisasContext *dc, TCGv v) static void dec_msr(DisasContext *dc) { + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env); + CPUState *cs = CPU(cpu); TCGv t0, t1; unsigned int sr, to, rn; int mem_index = cpu_mmu_index(dc->env); @@ -537,7 +539,7 @@ static void dec_msr(DisasContext *dc) tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); break; default: - cpu_abort(dc->env, "unknown mts reg %x\n", sr); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg %x\n", sr); break; } } else { @@ -586,7 +588,7 @@ static void dec_msr(DisasContext *dc) cpu_env, offsetof(CPUMBState, pvr.regs[rn])); break; default: - cpu_abort(dc->env, "unknown mfs reg %x\n", sr); + cpu_abort(cs, "unknown mfs reg %x\n", sr); break; } } @@ -684,7 +686,7 @@ static void dec_mul(DisasContext *dc) t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); break; default: - cpu_abort(dc->env, "unknown MUL insn %x\n", subcode); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n", subcode); break; } done: @@ -752,6 +754,8 @@ static void dec_barrel(DisasContext *dc) static void dec_bit(DisasContext *dc) { + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env); + CPUState *cs = CPU(cpu); TCGv t0; unsigned int op; int mem_index = cpu_mmu_index(dc->env); @@ -839,8 +843,8 @@ static void dec_bit(DisasContext *dc) tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); break; default: - cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", - dc->pc, op, dc->rd, dc->ra, dc->rb); + cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", + dc->pc, op, dc->rd, dc->ra, dc->rb); break; } } @@ -991,7 +995,7 @@ static void dec_load(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n"); break; } } @@ -1142,7 +1146,7 @@ static void dec_store(DisasContext *dc) } break; default: - cpu_abort(dc->env, "Invalid reverse size\n"); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n"); break; } } @@ -1193,7 +1197,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc, tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); break; default: - cpu_abort(dc->env, "Unknown condition code %x.\n", cc); + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code %x.\n", cc); break; } } @@ -1637,8 +1641,9 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("nr_nops=%d\t", dc->nr_nops); dc->nr_nops++; - if (dc->nr_nops > 4) - cpu_abort(dc->env, "fetching nop sequence\n"); + if (dc->nr_nops > 4) { + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop sequence\n"); + } } /* bit 2 seems to indicate insn type. */ dc->type_b = ir & (1 << 29); @@ -1709,8 +1714,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb, dc->abort_at_next_insn = 0; dc->nr_nops = 0; - if (pc_start & 3) - cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start); + if (pc_start & 3) { + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); + } if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index de5a22329a..1a785c23d9 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) { + MIPSCPU *cpu = mips_env_get_cpu(env); uint32_t val, old; uint32_t mask = env->CP0_Status_rw_bitmask; @@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } @@ -1985,6 +1988,8 @@ static void debug_pre_eret(CPUMIPSState *env) static void debug_post_eret(CPUMIPSState *env) { + MIPSCPU *cpu = mips_env_get_cpu(env); + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, env->active_tc.PC, env->CP0_EPC); @@ -1996,7 +2001,9 @@ static void debug_post_eret(CPUMIPSState *env) case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; - default: cpu_abort(env, "Invalid MMU mode!\n"); break; + default: + cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); + break; } } } diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 29d39e2a39..a64fd2b530 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -629,6 +629,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) static void mmu_init (CPUMIPSState *env, const mips_def_t *def) { + MIPSCPU *cpu = mips_env_get_cpu(env); + env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); switch (def->mmu_type) { @@ -645,7 +647,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def) case MMU_TYPE_R6000: case MMU_TYPE_R8000: default: - cpu_abort(env, "MMU type not supported\n"); + cpu_abort(CPU(cpu), "MMU type not supported\n"); } } #endif /* CONFIG_USER_ONLY */ diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 087e2f1351..e312300853 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -57,7 +57,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs) if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { env->pc = (cs->exception_index << 8); } else { - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } #endif diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index acf6909de7..91b7ae5534 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2100,7 +2100,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) } } - cpu_abort(env, "Unknown TLBe: %d\n", id); + cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); return 0; } diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 4a587303a8..a2226d1923 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -242,7 +242,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; default: /* Should never occur */ - cpu_abort(env, "Invalid program exception %d. Aborting\n", + cpu_abort(cs, "Invalid program exception %d. Aborting\n", env->error_code); break; } @@ -302,26 +302,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) break; } /* XXX: TODO */ - cpu_abort(env, "Debug exception is not implemented yet !\n"); + cpu_abort(cs, "Debug exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_current; case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point data exception " + cpu_abort(cs, "Embedded floating point data exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ /* XXX: TODO */ - cpu_abort(env, "Embedded floating point round exception " + cpu_abort(cs, "Embedded floating point round exception " "is not implemented yet !\n"); env->spr[SPR_BOOKE_ESR] = ESR_SPV; goto store_next; case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ @@ -403,15 +403,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) goto store_next; case POWERPC_EXCP_IO: /* IO error exception */ /* XXX: TODO */ - cpu_abort(env, "601 IO error exception is not implemented yet !\n"); + cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_RUNM: /* Run mode exception */ /* XXX: TODO */ - cpu_abort(env, "601 run mode exception is not implemented yet !\n"); + cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_EMUL: /* Emulation trap exception */ /* XXX: TODO */ - cpu_abort(env, "602 emulation trap exception " + cpu_abort(cs, "602 emulation trap exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ @@ -429,7 +429,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid instruction TLB miss exception\n"); + cpu_abort(cs, "Invalid instruction TLB miss exception\n"); break; } break; @@ -448,7 +448,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) case POWERPC_EXCP_74xx: goto tlb_miss_74xx; default: - cpu_abort(env, "Invalid data load TLB miss exception\n"); + cpu_abort(cs, "Invalid data load TLB miss exception\n"); break; } break; @@ -534,30 +534,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) msr |= env->error_code; /* key bit */ break; default: - cpu_abort(env, "Invalid data store TLB miss exception\n"); + cpu_abort(cs, "Invalid data store TLB miss exception\n"); break; } goto store_next; case POWERPC_EXCP_FPA: /* Floating-point assist exception */ /* XXX: TODO */ - cpu_abort(env, "Floating point assist exception " + cpu_abort(cs, "Floating point assist exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_DABR: /* Data address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "DABR exception is not implemented yet !\n"); + cpu_abort(cs, "DABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ /* XXX: TODO */ - cpu_abort(env, "IABR exception is not implemented yet !\n"); + cpu_abort(cs, "IABR exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SMI: /* System management interrupt */ /* XXX: TODO */ - cpu_abort(env, "SMI exception is not implemented yet !\n"); + cpu_abort(cs, "SMI exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_THERM: /* Thermal interrupt */ /* XXX: TODO */ - cpu_abort(env, "Thermal management exception " + cpu_abort(cs, "Thermal management exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ @@ -565,36 +565,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) new_msr |= (target_ulong)MSR_HVB; } /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "Performance counter exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_VPUA: /* Vector assist exception */ /* XXX: TODO */ - cpu_abort(env, "VPU assist exception is not implemented yet !\n"); + cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_SOFTP: /* Soft patch exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 soft-patch exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MAINT: /* Maintenance exception */ /* XXX: TODO */ - cpu_abort(env, + cpu_abort(cs, "970 maintenance exception is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Maskable external exception " + cpu_abort(cs, "Maskable external exception " "is not implemented yet !\n"); goto store_next; case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ /* XXX: TODO */ - cpu_abort(env, "Non maskable external exception " + cpu_abort(cs, "Non maskable external exception " "is not implemented yet !\n"); goto store_next; default: excp_invalid: - cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); break; store_current: /* save current instruction location */ @@ -636,7 +636,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) /* Jump to handler */ vector = env->excp_vectors[excp]; if (vector == (target_ulong)-1ULL) { - cpu_abort(env, "Raised an exception without defined vector %d\n", + cpu_abort(cs, "Raised an exception without defined vector %d\n", excp); } vector |= env->excp_prefix; diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 81ec959b23..9974b10ccb 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -1504,7 +1504,6 @@ int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) void kvmppc_set_papr(PowerPCCPU *cpu) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1513,7 +1512,7 @@ void kvmppc_set_papr(PowerPCCPU *cpu) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret) { - cpu_abort(env, "This KVM version does not support PAPR\n"); + cpu_abort(cs, "This KVM version does not support PAPR\n"); } /* Update the capability flag so we sync the right information @@ -1523,7 +1522,6 @@ void kvmppc_set_papr(PowerPCCPU *cpu) void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) { - CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); struct kvm_enable_cap cap = {}; int ret; @@ -1533,7 +1531,7 @@ void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) ret = kvm_vcpu_ioctl(cs, KVM_ENABLE_CAP, &cap); if (ret && mpic_proxy) { - cpu_abort(env, "This KVM version does not support EPR\n"); + cpu_abort(cs, "This KVM version does not support EPR\n"); } } diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index c75b4f2a71..845a7252b3 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -746,9 +746,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, void store_40x_sler(CPUPPCState *env, uint32_t val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + /* XXX: TO BE FIXED */ if (val != 0x00000000) { - cpu_abort(env, "Little-endian regions are not supported by now\n"); + cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n"); } env->spr[SPR_405_SLER] = val; } @@ -1344,6 +1346,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, int rw, int access_type) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int ret = -1; bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0) || (access_type != ACCESS_CODE && msr_dr == 0); @@ -1388,17 +1391,17 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: if (real_mode) { ret = check_physical(env, ctx, eaddr, rw); } else { - cpu_abort(env, "PowerPC in real mode do not do any translation\n"); + cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n"); } return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n"); return -1; } #if 0 @@ -1543,14 +1546,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, return -1; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; @@ -1623,7 +1626,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(cs, "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: booke206_update_mas_tlb_miss(env, address, rw); @@ -1635,11 +1638,11 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address, env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0; return -1; case POWERPC_MMU_REAL: - cpu_abort(env, "PowerPC in real mode should never raise " + cpu_abort(cs, "PowerPC in real mode should never raise " "any MMU exceptions\n"); return -1; default: - cpu_abort(env, "Unknown or invalid MMU model\n"); + cpu_abort(cs, "Unknown or invalid MMU model\n"); return -1; } break; @@ -1893,6 +1896,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value) /* TLB management */ void ppc_tlb_invalidate_all(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: case POWERPC_MMU_SOFT_74xx: @@ -1903,11 +1908,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) ppc4xx_tlb_invalidate_all(env); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: tlb_flush(env, 1); @@ -1927,7 +1932,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) break; default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } } @@ -1935,6 +1940,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) { #if !defined(FLUSH_ALL_TLBS) + PowerPCCPU *cpu = ppc_env_get_cpu(env); + addr &= TARGET_PAGE_MASK; switch (env->mmu_model) { case POWERPC_MMU_SOFT_6xx: @@ -1949,19 +1956,19 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); break; case POWERPC_MMU_REAL: - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n"); break; case POWERPC_MMU_MPC8xx: /* XXX: TODO */ - cpu_abort(env, "MPC8xx MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE: /* XXX: TODO */ - cpu_abort(env, "BookE MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n"); break; case POWERPC_MMU_BOOKE206: /* XXX: TODO */ - cpu_abort(env, "BookE 2.06 MMU model is not implemented\n"); + cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n"); break; case POWERPC_MMU_32B: case POWERPC_MMU_601: @@ -2002,7 +2009,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) #endif /* defined(TARGET_PPC64) */ default: /* XXX: TODO */ - cpu_abort(env, "Unknown MMU model\n"); + cpu_abort(CPU(cpu), "Unknown MMU model\n"); break; } #else @@ -2317,6 +2324,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, target_ulong val) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); ppcemb_tlb_t *tlb; target_ulong page, end; @@ -2340,7 +2348,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, * of the ppc or ppc64 one */ if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) { - cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u " + cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u " "are not supported (%d)\n", tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7)); } @@ -2349,7 +2357,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot |= PAGE_VALID; if (val & PPC4XX_TLBHI_E) { /* XXX: TO BE FIXED */ - cpu_abort(env, + cpu_abort(CPU(cpu), "Little-endian TLB entries are not supported by now\n"); } } else { @@ -2545,6 +2553,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address) static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg = 0; int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT; int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK); @@ -2554,7 +2563,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb]; if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) { - cpu_abort(env, "we don't support HES yet\n"); + cpu_abort(CPU(cpu), "we don't support HES yet\n"); } return booke206_get_tlbm(env, tlb, ea, esel); @@ -2569,6 +2578,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) void helper_booke206_tlbwe(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; uint32_t size_tlb, size_ps; @@ -2622,7 +2632,7 @@ void helper_booke206_tlbwe(CPUPPCState *env) } if (msr_gs) { - cpu_abort(env, "missing HV implementation\n"); + cpu_abort(CPU(cpu), "missing HV implementation\n"); } tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) | env->spr[SPR_BOOKE_MAS3]; diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e22d82f604..267a3765b4 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4432,6 +4432,7 @@ enum fsl_e500_version { static void init_proc_e500 (CPUPPCState *env, int version) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); uint32_t tlbncfg[2]; uint64_t ivor_mask; uint64_t ivpr_mask = 0xFFFF0000ULL; @@ -4490,7 +4491,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } #endif /* Cache sizes */ @@ -4507,7 +4508,7 @@ static void init_proc_e500 (CPUPPCState *env, int version) l1cfg0 |= 0x1000000; /* 64 byte cache block size */ break; default: - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); } gen_spr_BookE206(env, 0x000000DF, tlbncfg); /* XXX : not implemented */ diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c index d845f20de5..9e676a5ca7 100644 --- a/target-s390x/cc_helper.c +++ b/target-s390x/cc_helper.c @@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst) static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst, uint64_t vr) { + S390CPU *cpu = s390_env_get_cpu(env); uint32_t r = 0; switch (cc_op) { @@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op, break; default: - cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op)); + cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op)); } HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__, diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c index 94375b6a63..3e9c7b2d68 100644 --- a/target-s390x/fpu_helper.c +++ b/target-s390x/fpu_helper.c @@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr) static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) { + S390CPU *cpu = s390_env_get_cpu(env); + switch (float_compare) { case float_relation_equal: return 0; @@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare) case float_relation_unordered: return 3; default: - cpu_abort(env, "unknown return value for float compare\n"); + cpu_abort(CPU(cpu), "unknown return value for float compare\n"); } } diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 6262f42762..d4ea7d56d1 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -116,6 +116,7 @@ static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, static int trans_bits(CPUS390XState *env, uint64_t mode) { + S390CPU *cpu = s390_env_get_cpu(env); int bits = 0; switch (mode) { @@ -129,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode) bits = 3; break; default: - cpu_abort(env, "unknown asc mode\n"); + cpu_abort(CPU(cpu), "unknown asc mode\n"); break; } @@ -479,13 +480,14 @@ static uint64_t get_psw_mask(CPUS390XState *env) static LowCore *cpu_map_lowcore(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; hwaddr len = sizeof(LowCore); lowcore = cpu_physical_memory_map(env->psa, &len, 1); if (len < sizeof(LowCore)) { - cpu_abort(env, "Could not map lowcore\n"); + cpu_abort(CPU(cpu), "Could not map lowcore\n"); } return lowcore; @@ -583,16 +585,17 @@ static void do_program_interrupt(CPUS390XState *env) static void do_ext_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; ExtQueue *q; if (!(env->psw.mask & PSW_MASK_EXT)) { - cpu_abort(env, "Ext int w/o ext mask\n"); + cpu_abort(CPU(cpu), "Ext int w/o ext mask\n"); } if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) { - cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index); + cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index); } q = &env->ext_queue[env->ext_index]; @@ -622,6 +625,7 @@ static void do_ext_interrupt(CPUS390XState *env) static void do_io_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); LowCore *lowcore; IOIntQueue *q; uint8_t isc; @@ -629,7 +633,7 @@ static void do_io_interrupt(CPUS390XState *env) int found = 0; if (!(env->psw.mask & PSW_MASK_IO)) { - cpu_abort(env, "I/O int w/o I/O mask\n"); + cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n"); } for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) { @@ -639,7 +643,7 @@ static void do_io_interrupt(CPUS390XState *env) continue; } if (env->io_index[isc] > MAX_IO_QUEUE) { - cpu_abort(env, "I/O queue overrun for isc %d: %d\n", + cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n", isc, env->io_index[isc]); } @@ -686,24 +690,25 @@ static void do_io_interrupt(CPUS390XState *env) static void do_mchk_interrupt(CPUS390XState *env) { + S390CPU *cpu = s390_env_get_cpu(env); uint64_t mask, addr; LowCore *lowcore; MchkQueue *q; int i; if (!(env->psw.mask & PSW_MASK_MCHECK)) { - cpu_abort(env, "Machine check w/o mchk mask\n"); + cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n"); } if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) { - cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index); + cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index); } q = &env->mchk_queue[env->mchk_index]; if (q->type != 1) { /* Don't know how to handle this... */ - cpu_abort(env, "Unknown machine check type %d\n", q->type); + cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type); } if (!(env->cregs[14] & (1 << 28))) { /* CRW machine checks disabled */ diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c index 85e49aafa6..6a929ca1f3 100644 --- a/target-s390x/int_helper.c +++ b/target-s390x/int_helper.c @@ -106,9 +106,10 @@ uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, runtime_exception(env, PGM_FIXPT_DIVIDE, GETPC()); } #else + S390CPU *cpu = s390_env_get_cpu(env); /* 32-bit hosts would need special wrapper functionality - just abort if we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env, "128 -> 64/64 division not implemented\n"); + cpu_abort(CPU(cpu), "128 -> 64/64 division not implemented\n"); #endif } return ret; diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index e1c2ac04d1..21632848ac 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -72,6 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, uint8_t byte) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr len = l; void *dest_p; @@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, byte); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; @@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest, static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, uint64_t src) { + S390CPU *cpu = s390_env_get_cpu(env); hwaddr dest_phys; hwaddr src_phys; hwaddr len = l; @@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest, if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) { cpu_stb_data(env, dest, 0); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } dest_phys |= dest & ~TARGET_PAGE_MASK; if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) { cpu_ldub_data(env, src); - cpu_abort(env, "should never reach here"); + cpu_abort(CPU(cpu), "should never reach here"); } src_phys |= src & ~TARGET_PAGE_MASK; @@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address, uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, uint64_t addr, uint64_t ret) { + S390CPU *cpu = s390_env_get_cpu(env); uint16_t insn = cpu_lduw_code(env, addr); HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr, @@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1, cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3); } else { abort: - cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n", + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemented\n", insn); } return cc; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 0357cebb81..ba0f269f52 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb) static int itlb_replacement(CPUSH4State * env) { - if ((env->mmucr & 0xe0000000) == 0xe0000000) + SuperHCPU *cpu = sh_env_get_cpu(env); + + if ((env->mmucr & 0xe0000000) == 0xe0000000) { return 0; - if ((env->mmucr & 0x98000000) == 0x18000000) + } + if ((env->mmucr & 0x98000000) == 0x18000000) { return 1; - if ((env->mmucr & 0x54000000) == 0x04000000) + } + if ((env->mmucr & 0x54000000) == 0x04000000) { return 2; - if ((env->mmucr & 0x2c000000) == 0x00000000) + } + if ((env->mmucr & 0x2c000000) == 0x00000000) { return 3; - cpu_abort(env, "Unhandled itlb_replacement"); + } + cpu_abort(CPU(cpu), "Unhandled itlb_replacement"); } /* Find the corresponding entry in the right TLB @@ -498,7 +504,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, cs->exception_index = 0x100; break; default: - cpu_abort(env, "Unhandled MMU fault"); + cpu_abort(cs, "Unhandled MMU fault"); } return 1; } @@ -522,6 +528,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) void cpu_load_tlb(CPUSH4State * env) { + SuperHCPU *cpu = sh_env_get_cpu(env); int n = cpu_mmucr_urc(env->mmucr); tlb_t * entry = &env->utlb[n]; @@ -551,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env) entry->size = 1024 * 1024; /* 1M */ break; default: - cpu_abort(env, "Unhandled load_tlb"); + cpu_abort(CPU(cpu), "Unhandled load_tlb"); break; } entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index b3ce7bad53..720a97b1d1 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -58,8 +58,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, void helper_ldtlb(CPUSH4State *env) { #ifdef CONFIG_USER_ONLY + SuperHCPU *cpu = sh_env_get_cpu(env); + /* XXXXX */ - cpu_abort(env, "Unhandled ldtlb"); + cpu_abort(CPU(cpu), "Unhandled ldtlb"); #else cpu_load_tlb(env); #endif diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index f350a903e0..7c380ba2a1 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -109,7 +109,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", + cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", cs->exception_index); } return; diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index 1744245f70..bf242323a4 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -111,7 +111,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #endif #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { - cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," + cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," " Error state", cs->exception_index, env->tl, env->maxtl); return; } diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index 29cf5755bc..195e1bfca9 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -229,26 +229,22 @@ void helper_cp1_putc(target_ulong x) #ifdef CONFIG_USER_ONLY void switch_mode(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (mode != ASR_MODE_USER) { - cpu_abort(env, "Tried to switch out of user mode\n"); + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } } void uc32_cpu_do_interrupt(CPUState *cs) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - - cpu_abort(env, "NO interrupt in user mode\n"); + cpu_abort(cs, "NO interrupt in user mode\n"); } int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int access_type, int mmu_idx) { - UniCore32CPU *cpu = UNICORE32_CPU(cs); - CPUUniCore32State *env = &cpu->env; - - cpu_abort(env, "NO mmu fault in user mode\n"); + cpu_abort(cs, "NO mmu fault in user mode\n"); return 1; } #endif diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index a55355ebe8..39ecd98907 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -33,6 +33,8 @@ /* Map CPU modes onto saved register banks. */ static inline int bank_number(CPUUniCore32State *env, int mode) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (mode) { case ASR_MODE_USER: case ASR_MODE_SUSR: @@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode) case ASR_MODE_INTR: return 4; } - cpu_abort(env, "Bad mode %x\n", mode); + cpu_abort(CPU(cpu), "Bad mode %x\n", mode); return -1; } @@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs) addr = 0x18; break; default: - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index); + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; } /* High vectors. */ @@ -121,7 +123,8 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, int access_type, int is_user, uint32_t *phys_ptr, int *prot, target_ulong *page_size) { - CPUState *cs = CPU(uc32_env_get_cpu(env)); + UniCore32CPU *cpu = uc32_env_get_cpu(env); + CPUState *cs = CPU(cpu); int code; uint32_t table; uint32_t desc; @@ -168,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address, *page_size = TARGET_PAGE_SIZE; break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } break; default: - cpu_abort(env, "wrong page type!"); + cpu_abort(CPU(cpu), "wrong page type!"); } *phys_ptr = phys_addr; @@ -268,6 +271,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { UniCore32CPU *cpu = UNICORE32_CPU(cs); - cpu_abort(&cpu->env, "%s not supported yet\n", __func__); + cpu_abort(CPU(cpu), "%s not supported yet\n", __func__); return addr; } diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 5032bbe2a0..c2402cf942 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -176,7 +176,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) #define UCOP_SET_L UCOP_SET(24) #define UCOP_SET_S UCOP_SET(24) -#define ILLEGAL cpu_abort(env, \ +#define ILLEGAL cpu_abort(CPU(cpu), \ "Illegal UniCore32 instruction %x at line %d!", \ insn, __LINE__) @@ -184,6 +184,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var) static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp, tmp2, tmp3; if ((insn & 0xfe000000) == 0xe0000000) { tmp2 = new_tmp(); @@ -209,6 +210,7 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s, static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xff003fff) == 0xe1000400) { @@ -689,6 +691,7 @@ static inline long ucf64_reg_offset(int reg) /* UniCore-F64 single load/store I_offset */ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int offset; TCGv tmp; TCGv addr; @@ -735,6 +738,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 load/store multiple words */ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int i; int j, n, freg; TCGv tmp; @@ -820,6 +824,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in /* UniCore-F64 mrc/mcr */ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; if ((insn & 0xfe0003ff) == 0xe2000000) { @@ -884,6 +889,8 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* UniCore-F64 convert instructions */ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -950,6 +957,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 compare instructions */ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_SET(25)) { ILLEGAL; } @@ -1028,6 +1037,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn /* UniCore-F64 data processing */ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (UCOP_UCF64_FMT == 3) { ILLEGAL; } @@ -1061,6 +1072,8 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins /* Disassemble an F64 instruction */ static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + if (!UCOP_SET(29)) { if (UCOP_SET(26)) { do_ucf64_ldst_m(env, s, insn); @@ -1167,6 +1180,8 @@ static void gen_exception_return(DisasContext *s, TCGv pc) static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); + switch (UCOP_CPNUM) { #ifndef CONFIG_USER_ONLY case 0: @@ -1181,13 +1196,14 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s, break; default: /* Unknown coprocessor. */ - cpu_abort(env, "Unknown coprocessor!"); + cpu_abort(CPU(cpu), "Unknown coprocessor!"); } } /* data processing instructions */ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv tmp; TCGv tmp2; int logic_cc; @@ -1421,6 +1437,7 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* miscellaneous instructions */ static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; TCGv tmp; @@ -1546,6 +1563,7 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* SWP instruction */ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; TCGv tmp2; @@ -1573,6 +1591,7 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store hw/sb */ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); TCGv addr; TCGv tmp; @@ -1625,6 +1644,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* load/store multiple words */ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val, i, mmu_idx; int j, n, reg, user, loaded_base; TCGv tmp; @@ -1766,6 +1786,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn) /* branch (and link) */ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int val; int32_t offset; TCGv tmp; @@ -1795,6 +1816,7 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn) static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); unsigned int insn; if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { @@ -1978,7 +2000,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu, if (dc->condjmp) { /* FIXME: This can theoretically happen with self-modifying code. */ - cpu_abort(env, "IO on conditional branch instruction"); + cpu_abort(cs, "IO on conditional branch instruction"); } gen_io_end(); } diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c index a516edd319..34fa2a5b40 100644 --- a/target-unicore32/ucf64_helper.c +++ b/target-unicore32/ucf64_helper.c @@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits) void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) { + UniCore32CPU *cpu = uc32_env_get_cpu(env); int i; uint32_t changed; @@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val) i = float_round_down; break; default: /* 100 and 101 not implement */ - cpu_abort(env, "Unsupported UniCore-F64 round mode"); + cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode"); } set_float_rounding_mode(i, &env->ucf64.fp_status); } diff --git a/translate-all.c b/translate-all.c index e35fcbe86a..f243c10094 100644 --- a/translate-all.c +++ b/translate-all.c @@ -688,7 +688,7 @@ static void page_flush_tb(void) /* XXX: tb_flush is currently not thread safe */ void tb_flush(CPUArchState *env1) { - CPUState *cpu; + CPUState *cpu = ENV_GET_CPU(env1); #if defined(DEBUG_FLUSH) printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", @@ -699,7 +699,7 @@ void tb_flush(CPUArchState *env1) #endif if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) > tcg_ctx.code_gen_buffer_size) { - cpu_abort(env1, "Internal error: code buffer overflow\n"); + cpu_abort(cpu, "Internal error: code buffer overflow\n"); } tcg_ctx.tb_ctx.nb_tbs = 0; @@ -1374,12 +1374,11 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) void tb_check_watchpoint(CPUState *cpu) { - CPUArchState *env = cpu->env_ptr; TranslationBlock *tb; tb = tb_find_pc(cpu->mem_io_pc); if (!tb) { - cpu_abort(env, "check_watchpoint: could not find TB for pc=%p", + cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p", (void *)cpu->mem_io_pc); } cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); @@ -1390,7 +1389,6 @@ void tb_check_watchpoint(CPUState *cpu) /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUState *cpu, int mask) { - CPUArchState *env = cpu->env_ptr; int old_mask; old_mask = cpu->interrupt_request; @@ -1409,7 +1407,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask) cpu->icount_decr.u16.high = 0xffff; if (!cpu_can_do_io(cpu) && (mask & ~old_mask) != 0) { - cpu_abort(env, "Raised interrupt while not in I/O function"); + cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } else { cpu->tcg_exit_req = 1; @@ -1422,7 +1420,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; must be at the end of the TB */ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) { +#if defined(TARGET_MIPS) || defined(TARGET_SH4) CPUArchState *env = cpu->env_ptr; +#endif TranslationBlock *tb; uint32_t n, cflags; target_ulong pc, cs_base; @@ -1430,7 +1430,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) tb = tb_find_pc(retaddr); if (!tb) { - cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", + cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", (void *)retaddr); } n = cpu->icount_decr.u16.low + tb->icount; @@ -1460,7 +1460,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) #endif /* This should never happen. */ if (n > CF_COUNT_MASK) { - cpu_abort(env, "TB too big during recompile"); + cpu_abort(cpu, "TB too big during recompile"); } cflags = n | CF_LAST_IO; -- cgit v1.2.3-55-g7522