From 3c820ddc1b92f17fea85fdaed2928feaa9c238d7 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 29 Apr 2022 13:59:52 -0700 Subject: semihosting: Split common_semi_flen_buf per target We already have some larger ifdef blocks for ARM and RISCV; split out common_semi_stack_bottom per target. Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- semihosting/arm-compat-semi.c | 44 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 23 deletions(-) (limited to 'semihosting') diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index d2ce214078..7550dce622 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -217,6 +217,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) { return is_a64(env); } + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + return is_a64(env) ? env->xregs[31] : env->regs[13]; +} #endif /* TARGET_ARM */ #ifdef TARGET_RISCV @@ -246,6 +253,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) != MXL_RV32; } + +static inline target_ulong common_semi_stack_bottom(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + return env->gpr[xSP]; +} #endif /* @@ -301,31 +315,15 @@ static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) common_semi_set_ret(cs, ret); } +/* + * Return an address in target memory of 64 bytes where the remote + * gdb should write its stat struct. (The format of this structure + * is defined by GDB's remote protocol and is not target-specific.) + * We put this on the guest's stack just below SP. + */ static target_ulong common_semi_flen_buf(CPUState *cs) { - target_ulong sp; -#ifdef TARGET_ARM - /* Return an address in target memory of 64 bytes where the remote - * gdb should write its stat struct. (The format of this structure - * is defined by GDB's remote protocol and is not target-specific.) - * We put this on the guest's stack just below SP. - */ - ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - - if (is_a64(env)) { - sp = env->xregs[31]; - } else { - sp = env->regs[13]; - } -#endif -#ifdef TARGET_RISCV - RISCVCPU *cpu = RISCV_CPU(cs); - CPURISCVState *env = &cpu->env; - - sp = env->gpr[xSP]; -#endif - + target_ulong sp = common_semi_stack_bottom(cs); return sp - 64; } -- cgit v1.2.3-55-g7522