From 52ff951b4f63a29593650a15efdf82f63d6d962d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 23 Feb 2016 15:36:44 +0000 Subject: target-arm: Add comment about not implementing NSACR.RFR QEMU doesn't implement the NSACR.RFR bit, which is a permitted IMPDEF in choice in ARMv7 and the only permitted choice in ARMv8. Add a comment to bad_mode_switch() to note that this is why FIQ is always a valid mode regardless of the CPU's Secure state. Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov Message-id: 1455556977-3644-7-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target-arm/helper.c') diff --git a/target-arm/helper.c b/target-arm/helper.c index b2d2440edd..57cc8790c8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5214,6 +5214,9 @@ static int bad_mode_switch(CPUARMState *env, int mode) case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: case ARM_CPU_MODE_FIQ: + /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + */ return 0; case ARM_CPU_MODE_MON: return !arm_is_secure(env); -- cgit v1.2.3-55-g7522