From 200bf596b96820186883953de9bda26cac8e6bd7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 20 Jun 2012 11:57:06 +0000 Subject: target-arm: Fix 11MPCore cache type register value Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-arm') diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7eb323ae4d..934894bf93 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -307,7 +307,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; + cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; cpu->id_dfr0 = 0; -- cgit v1.2.3-55-g7522