From 6b0407805d46bbeba70f4be426285d0a0e669750 Mon Sep 17 00:00:00 2001 From: Wei Huang Date: Fri, 10 Feb 2017 17:40:28 +0000 Subject: target-arm: Add support for PMU register PMSELR_EL0 This patch adds support for AArch64 register PMSELR_EL0. The existing PMSELR definition is revised accordingly. Signed-off-by: Wei Huang Reviewed-by: Peter Maydell [PMM: Moved #ifndef CONFIG_USER_ONLY to cover new regdefs] Message-id: 1486504171-26807-2-git-send-email-wei@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/arm/cpu.h') diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c0b3832d74..7e609f7a99 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -309,6 +309,7 @@ typedef struct CPUARMState { uint32_t c9_pmovsr; /* perf monitor overflow status */ uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ + uint64_t c9_pmselr; /* perf monitor counter selection register */ uint32_t c9_pminten; /* perf monitor interrupt enables */ union { /* Memory attribute redirection */ struct { -- cgit v1.2.3-55-g7522