From 85fc716732bc6e85a634335847999f411269f282 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 9 Mar 2018 17:09:43 +0000 Subject: linux-user: Implement aarch64 PR_SVE_SET/GET_VL As an implementation choice, widening VL has zeroed the previously inaccessible portion of the sve registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Acked-by: Alex Bennée Message-id: 20180303143823.27055-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'target/arm/cpu.h') diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3fa8fdad21..36711cdb50 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -866,6 +866,7 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); #endif target_ulong do_arm_semihosting(CPUARMState *env); -- cgit v1.2.3-55-g7522