From 0d935760346b7ea07cbf5f63667151198012c922 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 8 Jul 2022 20:45:12 +0530 Subject: target/arm: Implement SME RDSVL, ADDSVL, ADDSPL These SME instructions are nominally within the SVE decode space, so we add them to sve.decode and translate-sve.c. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220708151540.18136-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/sve.decode | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'target/arm/sve.decode') diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 908643d7d9..95af08c139 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -449,14 +449,17 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm -### SVE Stack Allocation Group +### SVE / Streaming SVE Stack Allocation Group # SVE stack frame adjustment ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 +ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 # SVE stack frame size RDVL 00000100 101 11111 01010 imm:s6 rd:5 +RDSVL 00000100 101 11111 01011 imm:s6 rd:5 ### SVE Bitwise Shift - Unpredicated Group -- cgit v1.2.3-55-g7522