From c648c9b7e1ccff94b51ecbebe86a206952c47e75 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 9 Mar 2021 07:53:05 -0800 Subject: target/arm: Update sve reduction vs simd_desc With the reduction operations, we intentionally increase maxsz to the next power of 2, so as to fill out the reduction tree correctly. Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small vectors, so this triggers an assertion for vector sizes > 32 that are not themselves a power of 2. Pass the power-of-two value in the simd_data field instead. Signed-off-by: Richard Henderson Message-id: 20210309155305.11301-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/sve_helper.c | 2 +- target/arm/translate-sve.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'target/arm') diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 6f4bc3a3cc..fd6c58f96a 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2896,7 +2896,7 @@ static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \ } \ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \ { \ - uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \ + uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \ TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \ for (i = 0; i < oprsz; ) { \ uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2420cd741b..0eefb61214 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3440,7 +3440,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, { unsigned vsz = vec_full_reg_size(s); unsigned p2vsz = pow2ceil(vsz); - TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, p2vsz, 0)); + TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz)); TCGv_ptr t_zn, t_pg, status; TCGv_i64 temp; -- cgit v1.2.3-55-g7522