From b35aec8597e86911d5553c94769f914a52a8b389 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 21 Feb 2019 15:29:39 -0800 Subject: target/hppa: Optimize blr r0,rn We can eliminate an extra TB in this case, which merely loads a "return address" into rn. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'target/hppa') diff --git a/target/hppa/translate.c b/target/hppa/translate.c index dad8ce563c..dc5636fe94 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3488,12 +3488,16 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { - TCGv_reg tmp = get_temp(ctx); - - tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); - /* The computation here never changes privilege level. */ - return do_ibranch(ctx, tmp, a->l, a->n); + if (a->x) { + TCGv_reg tmp = get_temp(ctx); + tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); + tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + /* The computation here never changes privilege level. */ + return do_ibranch(ctx, tmp, a->l, a->n); + } else { + /* BLR R0,RX is a good way to load PC+8 into RX. */ + return do_dbranch(ctx, ctx->iaoq_f + 8, a->l, a->n); + } } static bool trans_bv(DisasContext *ctx, arg_bv *a) -- cgit v1.2.3-55-g7522