From 9fedbbeeee6dead7e73b3a53e3c80dd37392b464 Mon Sep 17 00:00:00 2001 From: Cameron Esfahani Date: Sun, 24 Nov 2019 12:05:24 -0800 Subject: hvf: remove TSC synchronization code because it isn't fully complete The existing code in QEMU's HVF support to attempt to synchronize TSC across multiple cores is not sufficient. TSC value on other cores can go backwards. Until implementation is fixed, remove calls to hv_vm_sync_tsc(). Pass through TSC to guest OS. Signed-off-by: Cameron Esfahani Message-Id: <44c4afd2301b8bf99682b229b0796d84edd6d66f.1574625592.git.dirty@apple.com> Signed-off-by: Paolo Bonzini --- target/i386/hvf/hvf.c | 3 +-- target/i386/hvf/x86_emu.c | 3 --- target/i386/hvf/x86hvf.c | 4 ---- 3 files changed, 1 insertion(+), 9 deletions(-) (limited to 'target/i386') diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 0b50cfcbc6..90fd50acfc 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -518,7 +518,6 @@ void hvf_reset_vcpu(CPUState *cpu) { wreg(cpu->hvf_fd, HV_X86_R8 + i, 0x0); } - hv_vm_sync_tsc(0); hv_vcpu_invalidate_tlb(cpu->hvf_fd); hv_vcpu_flush(cpu->hvf_fd); } @@ -612,7 +611,7 @@ int hvf_init_vcpu(CPUState *cpu) hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1); - /*hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);*/ + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1); hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 1b04bd7e94..3df767209d 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -772,9 +772,6 @@ void simulate_wrmsr(struct CPUState *cpu) switch (msr) { case MSR_IA32_TSC: - /* if (!osx_is_sierra()) - wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp()); - hv_vm_sync_tsc(data);*/ break; case MSR_IA32_APICBASE: cpu_set_apic_base(X86_CPU(cpu)->apic_state, data); diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index e0ea02d631..1485b95776 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -152,10 +152,6 @@ void hvf_put_msrs(CPUState *cpu_state) hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base); hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base); - - /* if (!osx_is_sierra()) - wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());*/ - hv_vm_sync_tsc(env->tsc); } -- cgit v1.2.3-55-g7522