From 072f416a53ead5211c987cb2068ee9dbd7ba06cc Mon Sep 17 00:00:00 2001 From: Suraj Jitindar Singh Date: Tue, 12 Jun 2018 15:16:29 +1000 Subject: target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache For cap_ppc_safe_cache to be set to workaround, we require both a l1d cache flush instruction and private l1d cache. On POWER8 don't require private l1d cache. This means a guest on a POWER8 machine can make use of the cache flush workarounds. Signed-off-by: Suraj Jitindar Singh Signed-off-by: David Gibson --- target/ppc/kvm.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'target/ppc/kvm.c') diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 2c0c34e125..7fe9d0126b 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -2412,11 +2412,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void) return cap_mmu_hash_v3; } +static bool kvmppc_power8_host(void) +{ + bool ret = false; +#ifdef TARGET_PPC64 + { + uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr(); + ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) || + (base_pvr == CPU_POWERPC_POWER8NVL_BASE) || + (base_pvr == CPU_POWERPC_POWER8_BASE); + } +#endif /* TARGET_PPC64 */ + return ret; +} + static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c) { + bool l1d_thread_priv_req = !kvmppc_power8_host(); + if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) { return 2; - } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && + } else if ((!l1d_thread_priv_req || + c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) && (c.character & c.character_mask & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) { return 1; -- cgit v1.2.3-55-g7522