From ac12b601032e63aeb6c318e9cc9d8f2563854361 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Fri, 19 Mar 2021 12:45:29 -0700 Subject: target/riscv: Remove privilege v1.9 specific CSR related code Qemu doesn't support RISC-V privilege specification v1.9. Remove the remaining v1.9 specific references from the implementation. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com> [Changes by AF: - Rebase on latest patches - Bump the vmstate_riscv_cpu version_id and minimum_version_id ] Signed-off-by: Alistair Francis --- target/riscv/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/riscv/translate.c') diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2f9f5ccc62..26eccc5eb1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -116,7 +116,7 @@ static void generate_exception(DisasContext *ctx, int excp) ctx->base.is_jmp = DISAS_NORETURN; } -static void generate_exception_mbadaddr(DisasContext *ctx, int excp) +static void generate_exception_mtval(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); @@ -160,7 +160,7 @@ static void gen_exception_illegal(DisasContext *ctx) static void gen_exception_inst_addr_mis(DisasContext *ctx) { - generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); + generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); } static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) -- cgit v1.2.3-55-g7522