From 1e0d985fa9136a563168a3da66f3d17820404ee2 Mon Sep 17 00:00:00 2001 From: Jonathan Behrens Date: Wed, 8 May 2019 13:38:35 -0400 Subject: target/riscv: Only flush TLB if SATP.ASID changes There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target/riscv') diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0f51c7eae2..f9e2910643 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -723,7 +723,9 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val) if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { return -1; } else { - tlb_flush(CPU(riscv_env_get_cpu(env))); + if((val ^ env->satp) & SATP_ASID) { + tlb_flush(CPU(riscv_env_get_cpu(env))); + } env->satp = val; } } -- cgit v1.2.3-55-g7522