From 5da9514e965fcdccd3745d0e216feb507a0b9dd1 Mon Sep 17 00:00:00 2001 From: Hou Weiying Date: Mon, 19 Apr 2021 16:17:25 +1000 Subject: target/riscv: Add a config option for ePMP Add a config option to enable experimental support for ePMP. This is disabled by default and can be enabled with 'x-epmp=true'. Signed-off-by: Hongzheng-Li Signed-off-by: Hou Weiying Signed-off-by: Myriad-Dreamin Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 11 insertions(+) (limited to 'target/riscv') diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e530df9385..66787d019c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -412,6 +412,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.pmp) { set_feature(env, RISCV_FEATURE_PMP); + + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + if (cpu->cfg.epmp) { + set_feature(env, RISCV_FEATURE_EPMP); + } } set_resetvec(env, cpu->cfg.resetvec); @@ -554,6 +562,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 83b315e0b2..add734bbbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,7 @@ struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + bool epmp; uint64_t resetvec; } cfg; }; -- cgit v1.2.3-55-g7522