From b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea Mon Sep 17 00:00:00 2001 From: Artyom Tarasenko Date: Wed, 2 Mar 2016 14:45:19 +0100 Subject: target-sparc: implement UltraSPARC-T1 Strand status ASR Signed-off-by: Artyom Tarasenko Reviewed-by: Richard Henderson --- target/sparc/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'target/sparc') diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 729f4e27ee..8902e44ca2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3429,6 +3429,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x19: /* System tick compare */ gen_store_gpr(dc, rd, cpu_stick_cmpr); break; + case 0x1a: /* UltraSPARC-T1 Strand status */ + /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe + * this ASR as impl. dep + */ + CHECK_IU_FEATURE(dc, HYPV); + { + TCGv t = gen_dest_gpr(dc, rd); + tcg_gen_movi_tl(t, 1UL); + gen_store_gpr(dc, rd, t); + } + break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ -- cgit v1.2.3-55-g7522