From 308feb935249ad745ef763707e1db69bc10ba789 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Fri, 13 Jan 2017 19:36:31 +0100 Subject: target-m68k: manage pre-dec et post-inc in CAS In these cases we must update the address register after the operation. Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu> --- target/m68k/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'target') diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0e97900b2c..23e2b06205 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1963,6 +1963,15 @@ DISAS_INSN(cas) gen_partset_reg(opsize, DREG(ext, 0), load); tcg_temp_free(load); + + switch (extract32(insn, 3, 3)) { + case 3: /* Indirect postincrement. */ + tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize)); + break; + case 4: /* Indirect predecrememnt. */ + tcg_gen_mov_i32(AREG(insn, 0), addr); + break; + } } DISAS_INSN(cas2w) -- cgit v1.2.3-55-g7522