From 27e4661638c16e9f4f5941019ad5e0ebce8b7815 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 27 Jan 2021 23:42:53 +0100 Subject: target/tricore: Replace magic value by MMU_DATA_LOAD definition cpu_get_phys_page_debug() uses 'DATA LOAD' MMU access type. Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210127224255.3505711-2-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann --- target/tricore/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7715293263..81171db833 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -50,7 +50,8 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) int prot; int mmu_idx = cpu_mmu_index(&cpu->env, false); - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, + MMU_DATA_LOAD, mmu_idx)) { return -1; } return phys_addr; -- cgit v1.2.3-55-g7522 From 5513b7700c6cfa1beebcfcd20e9c7458d1ebd3ea Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 27 Jan 2021 23:42:54 +0100 Subject: target/tricore: Pass MMUAccessType to get_physical_address() 'int access_type' and ACCESS_INT are unused, drop them. Provide the mmu_idx argument to match other targets. 'int rw' is actually the MMUAccessType, rename it. Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210127224255.3505711-3-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann --- target/tricore/helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'target') diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 81171db833..c5e997f321 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -33,7 +33,7 @@ enum { #if defined(CONFIG_SOFTMMU) static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, int *prot, target_ulong address, - int rw, int access_type) + MMUAccessType access_type, int mmu_idx) { int ret = TLBRET_MATCH; @@ -72,13 +72,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, CPUTriCoreState *env = &cpu->env; hwaddr physical; int prot; - int access_type; int ret = 0; rw &= 1; - access_type = ACCESS_INT; ret = get_physical_address(env, &physical, &prot, - address, rw, access_type); + address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", -- cgit v1.2.3-55-g7522 From 4f293079402ad9cd1eae73c256d7adedc0b897b5 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 27 Jan 2021 23:42:55 +0100 Subject: target/tricore: Remove unused definitions Remove these confusing and unused definitions. Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210127224255.3505711-4-f4bug@amsat.org> Signed-off-by: Bastian Koppelmann --- target/tricore/cpu.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'target') diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index b82349d1b1..4b61a2c03f 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -375,18 +375,6 @@ typedef TriCoreCPU ArchCPU; #include "exec/cpu-all.h" -enum { - /* 1 bit to define user level / supervisor access */ - ACCESS_USER = 0x00, - ACCESS_SUPER = 0x01, - /* 1 bit to indicate direction */ - ACCESS_STORE = 0x02, - /* Type of instruction that generated the access */ - ACCESS_CODE = 0x10, /* Code fetch access */ - ACCESS_INT = 0x20, /* Integer load/store access */ - ACCESS_FLOAT = 0x30, /* floating point load/store access */ -}; - void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc); -- cgit v1.2.3-55-g7522 From 9b620609d79ca0e101af024435c5b38b80478969 Mon Sep 17 00:00:00 2001 From: Andreas Konopik Date: Thu, 11 Feb 2021 12:53:29 +0100 Subject: tricore: fixed faulty conditions for extr and imask According to the TC 1.3.1. Architecture Manual [1; page 174], results are undefined, if pos + width > 32 and not 31 or if width = 0. We found this error because of a different behavior between qemu-tricore and the real tricore processor. For pos + width = 32, qemu-tricore did not generate any intermediate code and ran into a different state compared to the real hardware. [1] https://www.infineon.com/dgdl/tc_v131_instructionset_v138.pdf?fileId=db3a304412b407950112b409b6dd0352 [BK: Add the why to the commit message] Reviewed-by: Bastian Koppelmann Signed-off-by: Andreas Konopik Signed-off-by: Georg Hofstetter Signed-off-by: David Brenken Message-Id: <20210211115329.8984-2-david.brenken@efs-auto.org> Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'target') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 7752630ac1..ebeddf8f4a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5777,8 +5777,8 @@ static void decode_rcpw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCPW_IMASK: CHECK_REG_PAIR(r2); - /* if pos + width > 31 undefined result */ - if (pos + width <= 31) { + /* if pos + width > 32 undefined result */ + if (pos + width <= 32) { tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); } @@ -6999,7 +6999,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RRPW_EXTR: - if (pos + width <= 31) { + if (pos + width <= 32) { /* optimize special cases */ if ((pos == 0) && (width == 8)) { tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -7021,7 +7021,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) break; case OPC2_32_RRPW_IMASK: CHECK_REG_PAIR(r3); - if (pos + width <= 31) { + if (pos + width <= 32) { tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); } -- cgit v1.2.3-55-g7522 From 007479842b27e03173a333b8c2e0dae14be64f8d Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 5 Mar 2021 14:03:51 +0100 Subject: target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 if r3+1 and r2 are the same then we would overwrite r2 with our first move and use the wrong result for the shift. Thus we store the result from the mov in a temp. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ebeddf8f4a..5b7ed70e39 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6989,6 +6989,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) uint32_t op2; int r1, r2, r3; int32_t pos, width; + TCGv temp; op2 = MASK_OP_RRPW_OP2(ctx->opcode); r1 = MASK_OP_RRPW_S1(ctx->opcode); @@ -7021,10 +7022,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) break; case OPC2_32_RRPW_IMASK: CHECK_REG_PAIR(r3); + if (pos + width <= 32) { - tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); + temp = tcg_temp_new(); + tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + tcg_temp_free(temp); } + break; case OPC2_32_RRPW_INSERT: if (pos + width <= 32) { -- cgit v1.2.3-55-g7522 From a21993c7f98862823280d1eb6d3e93cf6267896f Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 5 Mar 2021 14:06:38 +0100 Subject: target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 if width was 0 we would run into the assertion: qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o The instruction manual specifies undefined behaviour for this case. So we bring this in line with the golden Infineon simlator 'tsim', which simply writes 0 to the result in case of width=0. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 5b7ed70e39..2a814263de 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7000,6 +7000,11 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RRPW_EXTR: + if (width == 0) { + tcg_gen_movi_tl(cpu_gpr_d[r3], 0); + break; + } + if (pos + width <= 32) { /* optimize special cases */ if ((pos == 0) && (width == 8)) { -- cgit v1.2.3-55-g7522