From 53e047c2db0aba27e873c99bc789120157548203 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Wed, 27 Jan 2021 23:56:42 +0100 Subject: target/sh4: Replace magic value by MMUAccessType definitions Replace the 0/1/2 magic values by the corresponding MMUAccessType. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20210127232151.3523581-3-f4bug@amsat.org> --- target/sh4/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'target') diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fc81613776..4303ebf018 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -338,7 +338,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); - if (rw == 2) { + if (rw == MMU_INST_FETCH) { n = find_itlb_entry(env, address, use_asid); if (n >= 0) { matching = &env->itlb[n]; @@ -371,11 +371,11 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, if (n >= 0) { matching = &env->utlb[n]; if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { - n = (rw == 1) + n = (rw == MMU_DATA_STORE) ? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ; - } else if ((rw == 1) && !(matching->pr & 1)) { + } else if ((rw == MMU_DATA_STORE) && !(matching->pr & 1)) { n = MMU_DTLB_VIOLATION_WRITE; - } else if ((rw == 1) && !matching->d) { + } else if ((rw == MMU_DATA_STORE) && !matching->d) { n = MMU_DTLB_INITIAL_WRITE; } else { *prot = PAGE_READ; @@ -384,7 +384,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical, } } } else if (n == MMU_DTLB_MISS) { - n = (rw == 1) + n = (rw == MMU_DATA_STORE) ? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ; } } @@ -406,9 +406,9 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical, && (address < 0xe0000000 || address >= 0xe4000000)) { /* Unauthorized access in user mode (only store queues are available) */ qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n"); - if (rw == 0) { + if (rw == MMU_DATA_LOAD) { return MMU_DADDR_ERROR_READ; - } else if (rw == 1) { + } else if (rw == MMU_DATA_STORE) { return MMU_DADDR_ERROR_WRITE; } else { return MMU_IADDR_ERROR; @@ -441,7 +441,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) target_ulong physical; int prot; - get_physical_address(&cpu->env, &physical, &prot, addr, 0, 0); + get_physical_address(&cpu->env, &physical, &prot, addr, MMU_DATA_LOAD, 0); return physical; } -- cgit v1.2.3-55-g7522