From 71b3254dd227f4c5e0a1a4005175a98e0a2cdc19 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 27 Nov 2020 22:51:27 +0000 Subject: target/openrisc: Move pic_cpu code into CPU object proper The openrisc code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function openrisc_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. Create GPIO inputs to the OpenRISC CPU object, and make the only user of cpu_openrisc_pic_init() wire up directly to those instead. This allows us to delete the hw/openrisc/pic_cpu.c file entirely. This fixes a trivial memory leak reported by Coverity of the IRQs allocated in cpu_openrisc_pic_init(). Fixes: Coverity CID 1421934 Signed-off-by: Peter Maydell Reviewed-by: Stafford Horne Message-id: 20201127225127.14770-4-peter.maydell@linaro.org --- target/openrisc/cpu.c | 32 ++++++++++++++++++++++++++++++++ target/openrisc/cpu.h | 1 - 2 files changed, 32 insertions(+), 1 deletion(-) (limited to 'target') diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 5528c0918f..b0bdfbe4fe 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -65,6 +65,34 @@ static void openrisc_cpu_reset(DeviceState *dev) #endif } +#ifndef CONFIG_USER_ONLY +static void openrisc_cpu_set_irq(void *opaque, int irq, int level) +{ + OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; + CPUState *cs = CPU(cpu); + uint32_t irq_bit; + + if (irq > 31 || irq < 0) { + return; + } + + irq_bit = 1U << irq; + + if (level) { + cpu->env.picsr |= irq_bit; + } else { + cpu->env.picsr &= ~irq_bit; + } + + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr = 0; + } +} +#endif + static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -88,6 +116,10 @@ static void openrisc_cpu_initfn(Object *obj) OpenRISCCPU *cpu = OPENRISC_CPU(obj); cpu_set_cpustate_pointers(cpu); + +#ifndef CONFIG_USER_ONLY + qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); +#endif } /* CPU models */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144..82cbaeb4f8 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -293,7 +293,6 @@ typedef struct CPUOpenRISCState { uint32_t picmr; /* Interrupt mask register */ uint32_t picsr; /* Interrupt contrl register*/ #endif - void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; /** -- cgit v1.2.3-55-g7522 From cd2528de2cd07d790949c1b5532ae2ab11255e1b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 29 Nov 2020 17:40:20 +0000 Subject: target/nios2: Move IIC code into CPU object proper The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by: Wentong Wu Tested-by: Wentong Wu --- MAINTAINERS | 1 - hw/intc/meson.build | 1 - hw/intc/nios2_iic.c | 95 ----------------------------------------------- hw/nios2/10m50_devboard.c | 13 +------ hw/nios2/cpu_pic.c | 31 ---------------- target/nios2/cpu.c | 30 +++++++++++++++ target/nios2/cpu.h | 1 - 7 files changed, 32 insertions(+), 140 deletions(-) delete mode 100644 hw/intc/nios2_iic.c (limited to 'target') diff --git a/MAINTAINERS b/MAINTAINERS index 062074e47c..99293a5e02 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -259,7 +259,6 @@ M: Marek Vasut S: Maintained F: target/nios2/ F: hw/nios2/ -F: hw/intc/nios2_iic.c F: disas/nios2.c F: default-configs/nios2-softmmu.mak diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 3f82cc230a..7c3e9daf58 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -37,7 +37,6 @@ specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c')) specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c')) specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c')) specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) -specific_ss.add(when: 'CONFIG_NIOS2', if_true: files('nios2_iic.c')) specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c')) diff --git a/hw/intc/nios2_iic.c b/hw/intc/nios2_iic.c deleted file mode 100644 index 216db67059..0000000000 --- a/hw/intc/nios2_iic.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * QEMU Altera Internal Interrupt Controller. - * - * Copyright (c) 2012 Chris Wulff - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - */ - -#include "qemu/osdep.h" -#include "qemu/module.h" -#include "qapi/error.h" - -#include "hw/irq.h" -#include "hw/sysbus.h" -#include "cpu.h" -#include "qom/object.h" - -#define TYPE_ALTERA_IIC "altera,iic" -OBJECT_DECLARE_SIMPLE_TYPE(AlteraIIC, ALTERA_IIC) - -struct AlteraIIC { - SysBusDevice parent_obj; - void *cpu; - qemu_irq parent_irq; -}; - -static void update_irq(AlteraIIC *pv) -{ - CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env; - - qemu_set_irq(pv->parent_irq, - env->regs[CR_IPENDING] & env->regs[CR_IENABLE]); -} - -static void irq_handler(void *opaque, int irq, int level) -{ - AlteraIIC *pv = opaque; - CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env; - - env->regs[CR_IPENDING] &= ~(1 << irq); - env->regs[CR_IPENDING] |= !!level << irq; - - update_irq(pv); -} - -static void altera_iic_init(Object *obj) -{ - AlteraIIC *pv = ALTERA_IIC(obj); - - qdev_init_gpio_in(DEVICE(pv), irq_handler, 32); - sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq); -} - -static void altera_iic_realize(DeviceState *dev, Error **errp) -{ - struct AlteraIIC *pv = ALTERA_IIC(dev); - - pv->cpu = object_property_get_link(OBJECT(dev), "cpu", &error_abort); -} - -static void altera_iic_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - /* Reason: needs to be wired up, e.g. by nios2_10m50_ghrd_init() */ - dc->user_creatable = false; - dc->realize = altera_iic_realize; -} - -static TypeInfo altera_iic_info = { - .name = TYPE_ALTERA_IIC, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(AlteraIIC), - .instance_init = altera_iic_init, - .class_init = altera_iic_class_init, -}; - -static void altera_iic_register(void) -{ - type_register_static(&altera_iic_info); -} - -type_init(altera_iic_register) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 5c13b74306..a14fc31e86 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -52,7 +52,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine) ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base = 0x08000000; ram_addr_t ram_size = 0x08000000; - qemu_irq *cpu_irq, irq[32]; + qemu_irq irq[32]; int i; /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ @@ -75,17 +75,8 @@ static void nios2_10m50_ghrd_init(MachineState *machine) /* Create CPU -- FIXME */ cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - - /* Register: CPU interrupt controller (PIC) */ - cpu_irq = nios2_cpu_pic_init(cpu); - - /* Register: Internal Interrupt Controller (IIC) */ - dev = qdev_new("altera,iic"); - object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); for (i = 0; i < 32; i++) { - irq[i] = qdev_get_gpio_in(dev, i); + irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); } /* Register: Altera 16550 UART */ diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c index 5ea7e52ab8..3fb621c5c8 100644 --- a/hw/nios2/cpu_pic.c +++ b/hw/nios2/cpu_pic.c @@ -26,32 +26,6 @@ #include "boot.h" -static void nios2_pic_cpu_handler(void *opaque, int irq, int level) -{ - Nios2CPU *cpu = opaque; - CPUNios2State *env = &cpu->env; - CPUState *cs = CPU(cpu); - int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; - - if (type == CPU_INTERRUPT_HARD) { - env->irq_pending = level; - - if (level && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; - cpu_interrupt(cs, type); - } else if (!level) { - env->irq_pending = 0; - cpu_reset_interrupt(cs, type); - } - } else { - if (level) { - cpu_interrupt(cs, type); - } else { - cpu_reset_interrupt(cs, type); - } - } -} - void nios2_check_interrupts(CPUNios2State *env) { if (env->irq_pending && @@ -60,8 +34,3 @@ void nios2_check_interrupts(CPUNios2State *env) cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); } } - -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu) -{ - return qemu_allocate_irqs(nios2_pic_cpu_handler, cpu, 2); -} diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 8f7011fcb9..52ebda89ca 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -64,6 +64,27 @@ static void nios2_cpu_reset(DeviceState *dev) #endif } +#ifndef CONFIG_USER_ONLY +static void nios2_cpu_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu = opaque; + CPUNios2State *env = &cpu->env; + CPUState *cs = CPU(cpu); + + env->regs[CR_IPENDING] &= ~(1 << irq); + env->regs[CR_IPENDING] |= !!level << irq; + + env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; + + if (env->irq_pending && (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending = 0; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else if (!env->irq_pending) { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} +#endif + static void nios2_cpu_initfn(Object *obj) { Nios2CPU *cpu = NIOS2_CPU(obj); @@ -72,6 +93,15 @@ static void nios2_cpu_initfn(Object *obj) #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); + + /* + * These interrupt lines model the IIC (internal interrupt + * controller). QEMU does not currently support the EIC + * (external interrupt controller) -- if we did it would be + * a separate device in hw/intc with a custom interface to + * the CPU, and boards using it would not wire up these IRQ lines. + */ + qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 86bbe1d867..b7efb54ba7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,7 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -qemu_irq *nios2_cpu_pic_init(Nios2CPU *cpu); void nios2_check_interrupts(CPUNios2State *env); void do_nios2_semihosting(CPUNios2State *env); -- cgit v1.2.3-55-g7522 From 2c87548ef46040d0577cc362cab94561c1d98b8d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 29 Nov 2020 17:40:21 +0000 Subject: target/nios2: Move nios2_check_interrupts() into target/nios2 The function nios2_check_interrupts)() looks only at CPU-internal state; it belongs in target/nios2, not hw/nios2. Move it into the same file as its only caller, so it can just be local to that file. This removes the only remaining code from cpu_pic.c, so we can delete that file entirely. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20201129174022.26530-3-peter.maydell@linaro.org Reviewed-by: Wentong Wu Tested-by: Wentong Wu --- hw/nios2/cpu_pic.c | 36 ------------------------------------ hw/nios2/meson.build | 2 +- target/nios2/cpu.h | 2 -- target/nios2/op_helper.c | 9 +++++++++ 4 files changed, 10 insertions(+), 39 deletions(-) delete mode 100644 hw/nios2/cpu_pic.c (limited to 'target') diff --git a/hw/nios2/cpu_pic.c b/hw/nios2/cpu_pic.c deleted file mode 100644 index 3fb621c5c8..0000000000 --- a/hw/nios2/cpu_pic.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Altera Nios2 CPU PIC - * - * Copyright (c) 2016 Marek Vasut - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hw/irq.h" - -#include "qemu/config-file.h" - -#include "boot.h" - -void nios2_check_interrupts(CPUNios2State *env) -{ - if (env->irq_pending && - (env->regs[CR_STATUS] & CR_STATUS_PIE)) { - env->irq_pending = 0; - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); - } -} diff --git a/hw/nios2/meson.build b/hw/nios2/meson.build index dd66ebb32f..6c58e8082b 100644 --- a/hw/nios2/meson.build +++ b/hw/nios2/meson.build @@ -1,5 +1,5 @@ nios2_ss = ss.source_set() -nios2_ss.add(files('boot.c', 'cpu_pic.c')) +nios2_ss.add(files('boot.c')) nios2_ss.add(when: 'CONFIG_NIOS2_10M50', if_true: files('10m50_devboard.c')) nios2_ss.add(when: 'CONFIG_NIOS2_GENERIC_NOMMU', if_true: files('generic_nommu.c')) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index b7efb54ba7..2ab82fdc71 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -201,8 +201,6 @@ void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); -void nios2_check_interrupts(CPUNios2State *env); - void do_nios2_semihosting(CPUNios2State *env); #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a60730faac..a59003855a 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -36,6 +36,15 @@ void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v) mmu_write(env, rn, v); } +static void nios2_check_interrupts(CPUNios2State *env) +{ + if (env->irq_pending && + (env->regs[CR_STATUS] & CR_STATUS_PIE)) { + env->irq_pending = 0; + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HARD); + } +} + void helper_check_interrupts(CPUNios2State *env) { qemu_mutex_lock_iothread(); -- cgit v1.2.3-55-g7522 From 05bcbcf27954e664d85627f026970f62556fefa5 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 29 Nov 2020 17:40:22 +0000 Subject: target/nios2: Use deposit32() to update ipending register In nios2_cpu_set_irq(), use deposit32() rather than raw shift-and-mask operations to set the appropriate bit in the ipending register. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20201129174022.26530-4-peter.maydell@linaro.org --- target/nios2/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'target') diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 52ebda89ca..58688e1623 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -71,8 +71,7 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int level) CPUNios2State *env = &cpu->env; CPUState *cs = CPU(cpu); - env->regs[CR_IPENDING] &= ~(1 << irq); - env->regs[CR_IPENDING] |= !!level << irq; + env->regs[CR_IPENDING] = deposit32(env->regs[CR_IPENDING], irq, 1, !!level); env->irq_pending = env->regs[CR_IPENDING] & env->regs[CR_IENABLE]; -- cgit v1.2.3-55-g7522