From 7d6f01a12be534ce2ffaf0aa8741e5f5efca2362 Mon Sep 17 00:00:00 2001 From: Philippe Mathieu-Daudé Date: Mon, 30 Nov 2020 11:13:01 +0100 Subject: target/mips: Allow executing MSA instructions on Loongson-3A4000 The Loongson-3A4000 is a GS464V-based processor with MIPS MSA ASE: https://www.mail-archive.com/qemu-devel@nongnu.org/msg763059.html Commit af868995e1b correctly set the 'MSA present' bit of Config3 register, but forgot to allow the MSA instructions decoding in insn_flags, so executing them triggers a 'Reserved Instruction'. Fix by adding the ASE_MSA mask to insn_flags. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Huacai Chen Message-Id: <20201130102228.2395100-1-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index ea85d5c6a7..79f75ed863 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -832,7 +832,7 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { - .name = "Loongson-3A4000", + .name = "Loongson-3A4000", /* GS464V-based */ .CP0_PRid = 0x14C000, /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | @@ -885,7 +885,7 @@ const mips_def_t mips_defs[] = .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 48, .PABITS = 48, - .insn_flags = CPU_LOONGSON3A, + .insn_flags = CPU_LOONGSON3A | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, { -- cgit v1.2.3-55-g7522