From d70080c4e37fc533fa10904b286f29449decc6f8 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:13 +0800 Subject: target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- tests/tcg/mips/mips64-dspr2/addu_s_qh.c | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 tests/tcg/mips/mips64-dspr2/addu_s_qh.c (limited to 'tests/tcg/mips/mips64-dspr2/addu_s_qh.c') diff --git a/tests/tcg/mips/mips64-dspr2/addu_s_qh.c b/tests/tcg/mips/mips64-dspr2/addu_s_qh.c new file mode 100644 index 0000000000..b0c1626251 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addu_s_qh.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg; + long long result, dspresult; + + rs = 0x123456787FFF0000; + rt = 0x1111111180000000; + result = 0x23456789FFFF0000; + dspresult = 0x0; + + __asm("addu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("1 addu_s.qh error\n"); + return -1; + } + + rs = 0x12345678FFFF0000; + rt = 0x11111111000F0000; + result = 0x23456789FFFF0000; + dspresult = 0x01; + + __asm("addu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("2 addu_s.qh error\n"); + return -1; + } + + return 0; +} -- cgit v1.2.3-55-g7522