openslx-ng/ipxe.git/src/arch/riscv/include/bits, branch openslx

[riscv] Add optimised TCP/IP checksumming

2025-07-10T12:32:45+00:00

Add a RISC-V assembly language implementation of TCP/IP checksumming, which is around 50x faster than the generic algorithm. The main loop checksums aligned xlen-bit words, using almost entirely compressible instructions and accumulating carries in a separate register to allow folding to be deferred until after all loops have completed. Experimentation on a C910 CPU suggests that this achieves around four bytes per clock cycle, which is comparable to the x86 implementation. Signed-off-by: Michael Brown

[riscv] Provide a DMA API implementation for RISC-V bare-metal systems

2025-07-09T10:07:37+00:00

Provide an implementation of dma_map() that performs cache clean or invalidation as required, and an implementation of dma_alloc() that returns virtual addresses within the coherent mapping of the 32-bit physical address space. Signed-off-by: Michael Brown

[riscv] Support mapping I/O devices outside of the identity map

2025-05-26T16:56:27+00:00

With the 64-bit paging schemes (Sv39, Sv48, and Sv57), we identity-map as much of the physical address space as is possible. Experimentation shows that this is not sufficient to provide access to all I/O devices. For example: the Sipeed Lichee Pi 4A includes a CPU that supports only Sv39, but places I/O devices at the top of a 40-bit address space. Add support for creating I/O page table entries on demand to map I/O devices, based on the existing design used for x86_64 BIOS. Signed-off-by: Michael Brown

[riscv] Speed up memmove() when copying in forwards direction

2025-05-21T15:12:56+00:00

Use the word-at-a-time variable-length memcpy() implementation when performing an overlapping copy in the forwards direction, since this is guaranteed to be safe and likely to be substantially faster than the existing bytewise copy. Signed-off-by: Michael Brown

[lkrn] Add basic support for the RISC-V Linux kernel image format

2025-05-20T12:08:38+00:00

The RISC-V and AArch64 bare-metal kernel images share a common header format, and require essentially the same execution environment: loaded close to the start of RAM, entered with paging disabled, and passed a pointer to a flattened device tree that describes the hardware and any boot arguments. Implement basic support for executing bare-metal RISC-V and AArch64 kernel images. The (trivial) AArch64-specific code path is untested since we do not yet have the ability to build for any bare-metal AArch64 platforms. Constructing and passing an initramfs image is not yet supported. Rename the IMAGE_BZIMAGE build configuration option to IMAGE_LKRN, since "bzImage" is specific to x86. To retain backwards compatibility with existing local build configurations, we leave IMAGE_BZIMAGE as the enabled option in config/default/pcbios.h and treat IMAGE_LKRN as a synonym for IMAGE_BZIMAGE when building for x86 BIOS. Signed-off-by: Michael Brown

[riscv] Use generic external heap based on the system memory map

2025-05-19T18:36:25+00:00

Signed-off-by: Michael Brown

[riscv] Hold virtual address offset in the thread pointer register

2025-05-11T12:46:21+00:00

iPXE does not make use of any thread-local storage. Use the otherwise unused thread pointer register ("tp") to hold the current value of the virtual address offset, rather than using a global variable. This ensures that virt_offset can be made valid even during very early initialisation (when iPXE may be executing directly from read-only memory and so cannot update a global variable). Signed-off-by: Michael Brown

[crypto] Expose shifted out bit from big integer shifts

2025-02-13T15:25:35+00:00

Expose the bit shifted out as a result of shifting a big integer left or right. Signed-off-by: Michael Brown

[crypto] Expose carry flag from big integer addition and subtraction

2024-11-26T12:55:13+00:00

Expose the effective carry (or borrow) out flag from big integer addition and subtraction, and use this to elide an explicit bit test when performing x25519 reduction. Signed-off-by: Michael Brown

[sbi] Add support for running as a RISC-V SBI payload

2024-10-28T19:20:50+00:00

Add basic support for running directly on top of SBI, with no UEFI firmware present. Build as e.g.: make CROSS=riscv64-linux-gnu- bin-riscv64/ipxe.sbi The resulting binary can be tested in QEMU using e.g.: qemu-system-riscv64 -M virt -cpu max -serial stdio \ -kernel bin-riscv64/ipxe.sbi No drivers or executable binary formats are supported yet, but the unit test suite may be run successfully. Signed-off-by: Michael Brown