<feed xmlns='http://www.w3.org/2005/Atom'>
<title>openslx-ng/ipxe.git/src/arch/riscv64, branch openslx</title>
<subtitle>Fork of ipxe; additional commands and features</subtitle>
<id>https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/riscv64?h=openslx</id>
<link rel='self' href='https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/riscv64?h=openslx'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/'/>
<updated>2025-05-06T11:11:02+00:00</updated>
<entry>
<title>[build] Allow for 32-bit and 64-bit versions of util/zbin</title>
<updated>2025-05-06T11:11:02+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-06T11:07:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=98646b9f016d9bff91a5c89f402aeb452ee7f84b'/>
<id>urn:sha1:98646b9f016d9bff91a5c89f402aeb452ee7f84b</id>
<content type='text'>
Parsing ELF data is simpler if we don't have to build a single binary
to handle both 32-bit and 64-bit ELF formats.

Allow for separate 32-bit and 64-bit binaries built from util/zbin.c
(as is already done for util/elf2efi.c).

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[riscv] Allow for a non-zero link-time address</title>
<updated>2025-05-01T13:49:53+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-01T13:24:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=dad20602609438e72f2fe8d9dd49b9a92b8490fa'/>
<id>urn:sha1:dad20602609438e72f2fe8d9dd49b9a92b8490fa</id>
<content type='text'>
Using paging (rather than relocation records) will be easier on 64-bit
RISC-V if we place iPXE within the negative (kernel) virtual address
space.

Allow the link-time address to be non-zero and to vary between 32-bit
and 64-bit builds.  Choose addresses that are expected to be amenable
to the use of paging.

There is no particular need to use a non-zero address in the 32-bit
builds, but doing so allows us to validate that the relocation code is
handling this case correctly.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[sbi] Add support for running as a RISC-V SBI payload</title>
<updated>2024-10-28T19:20:50+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2024-10-28T14:40:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=e0e102ee24bdab68b0318b505402f60cfb88a5f0'/>
<id>urn:sha1:e0e102ee24bdab68b0318b505402f60cfb88a5f0</id>
<content type='text'>
Add basic support for running directly on top of SBI, with no UEFI
firmware present.  Build as e.g.:

  make CROSS=riscv64-linux-gnu- bin-riscv64/ipxe.sbi

The resulting binary can be tested in QEMU using e.g.:

  qemu-system-riscv64 -M virt -cpu max -serial stdio \
                      -kernel bin-riscv64/ipxe.sbi

No drivers or executable binary formats are supported yet, but the
unit test suite may be run successfully.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[profile] Standardise return type of profile_timestamp()</title>
<updated>2024-09-24T14:40:45+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2024-09-24T13:49:32+00:00</published>
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<id>urn:sha1:5f7c6bd95bd6089473db3ba4f033584f5de0ee8a</id>
<content type='text'>
All consumers of profile_timestamp() currently treat the value as an
unsigned long.  Only the elapsed number of ticks is ever relevant: the
absolute value of the timestamp is not used.  Profiling is used to
measure short durations that are generally fewer than a million CPU
cycles, for which an unsigned long is easily large enough.

Standardise the return type of profile_timestamp() as unsigned long
across all CPU architectures.  This allows 32-bit architectures such
as i386 and riscv32 to omit all logic associated with retrieving the
upper 32 bits of the 64-bit hardware counter, which simplifies the
code and allows riscv32 and riscv64 to share the same implementation.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[efi] Remove redundant EFI_BOOT_FILE definitions</title>
<updated>2024-09-16T10:04:52+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2024-09-16T10:01:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=9bb20686369abf5166161804c16554d491f53a62'/>
<id>urn:sha1:9bb20686369abf5166161804c16554d491f53a62</id>
<content type='text'>
As of commit 79c0173 ("[build] Create util/genfsimg for building
filesystem-based images"), the EFI boot file name for each CPU
architecture is defined within the genfsimg script itself, rather than
being passed in as a Makefile parameter.

Remove the now-redundant Makefile definitions for EFI_BOOT_FILE.

Reported-by: Christian I. Nilsson &lt;nikize@gmail.com&gt;
Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[riscv] Add support for the RISC-V CPU architecture</title>
<updated>2024-09-15T21:34:10+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2024-09-15T09:54:04+00:00</published>
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<id>urn:sha1:c215048ddaac75969c22c018871295a5748a47e8</id>
<content type='text'>
Add support for building iPXE as a 64-bit or 32-bit RISC-V binary, for
either UEFI or Linux userspace platforms.  For example:

  # RISC-V 64-bit UEFI
  make CROSS=riscv64-linux-gnu- bin-riscv64-efi/ipxe.efi

  # RISC-V 32-bit UEFI
  make CROSS=riscv64-linux-gnu- bin-riscv32-efi/ipxe.efi

  # RISC-V 64-bit Linux
  make CROSS=riscv64-linux-gnu- bin-riscv64-linux/tests.linux
  qemu-riscv64 -L /usr/riscv64-linux-gnu/sys-root \
               ./bin-riscv64-linux/tests.linux

  # RISC-V 32-bit Linux
  make CROSS=riscv64-linux-gnu- SYSROOT=/usr/riscv32-linux-gnu/sys-root \
       bin-riscv32-linux/tests.linux
  qemu-riscv32 -L /usr/riscv32-linux-gnu/sys-root \
               ./bin-riscv32-linux/tests.linux

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
</feed>
