openslx-ng/ipxe.git/src/arch/riscv, branch openslx

[ioapi] Allow iounmap() to be called for port I/O addresses

2025-11-05T19:33:53+00:00

Allow code using the combined MMIO and port I/O accessors to safely call iounmap() to unmap the MMIO or port I/O region. In the virtual offset I/O mapping API as used for UEFI, 32-bit BIOS, and 32-bit RISC-V SBI, iounmap() is a no-op anyway. In 64-bit RISC-V SBI, we have no concept of port I/O and so the issue is moot. This leaves only 64-bit BIOS, where it suffices to simply do nothing for any pages outside of the chosen MMIO virtual address range. For symmetry, we implement the equivalent change in the very closely related RISC-V page management code. Signed-off-by: Michael Brown

[riscv] Correct page table stride calculation

2025-10-27T14:22:16+00:00

Signed-off-by: Michael Brown

[riscv] Place explicitly zero-initialised variables in the .data section

2025-07-30T12:15:11+00:00

Variables in the .bss section cannot be relied upon to have zero values during early initialisation, before we have relocated ourselves to somewhere suitable in RAM and zeroed the .bss section. Place any explicitly zero-initialised variables in the .data section rather than in .bss, so that we can rely on their values even during this early initialisation stage. Signed-off-by: Michael Brown

[riscv] Allow for poisoning .bss section before early initialisation

2025-07-30T11:31:15+00:00

On startup, we may be running from read-only memory, and therefore cannot zero the .bss section (or write to the .data section) until we have parsed the system memory map and relocated ourselves to somewhere suitable in RAM. The code that runs during this early initialisation stage must be carefully written to avoid writing to the .data section and to avoid reading from or writing to the .bss section. Detecting code that erroneously writes to the .data or .bss sections is relatively easy since running from read-only memory (e.g. via QEMU's -pflash option) will immediately reveal the bug. Detecting code that erroneously reads from the .bss section is harder, since in a freshly powered-on machine (or in a virtual machine) there is a high probability that the contents of the memory will be zero even before we explicitly zero out the section. Add the ability to fill the .bss section with an invalid non-zero value to expose bugs in early initialisation code that erroneously relies upon variables in .bss before the section has been zeroed. We use the value 0xeb55eb55eb55eb55 ("EBSS") since this is immediately recognisable as a value in a crash dump, and will trigger a page fault if dereferenced since the address is in a non-canonical form. Poisoning the .bss can be done only when the image is known to already reside in writable memory. It will overwrite the relocation records, and so can be done only on a system where relocation is known to be unnecessary (e.g. because paging is supported). We therefore do not enable this behaviour by default, but leave it as a configurable option via the config/fault.h header. Signed-off-by: Michael Brown

[riscv] Ensure coherent DMA allocations do not cross cacheline boundaries

2025-07-11T12:50:41+00:00

Signed-off-by: Michael Brown

[riscv] Support the standard Svpbmt extension for page-based memory types

2025-07-11T11:24:02+00:00

Set the appropriate Svpbmt type bits within page table entries if the extension is supported. Tested only in QEMU so far, due to the lack of availability of real hardware supporting Svpbmt. Signed-off-by: Michael Brown

[riscv] Create coherent DMA mapping of 32-bit address space on demand

2025-07-11T11:23:51+00:00

Reuse the code that creates I/O device page mappings to create the coherent DMA mapping of the 32-bit address space on demand, instead of constructing this mapping as part of the initial page table. Signed-off-by: Michael Brown

[riscv] Use 1GB pages for I/O device mappings

2025-07-11T11:05:52+00:00

All 64-bit paging schemes support at least 1GB "gigapages". Use these to map I/O devices instead of 2MB "megapages". This reduces the number of consumed page table entries, increases the visual similarity of I/O remapped addresses to the underlying physical addresses, and opens up the possibility of reusing the code to create the coherent DMA map of the 32-bit address space. Signed-off-by: Michael Brown

[riscv] Invalidate data cache on completed RX DMA buffers

2025-07-10T13:39:07+00:00

The data cache must be invalidated twice for RX DMA buffers: once before passing ownership to the DMA device (in case the cache happens to contain dirty data that will be written back at an undefined future point), and once after receiving ownership from the DMA device (in case the CPU happens to have speculatively accessed data in the buffer while it was owned by the hardware). Only the used portion of the buffer needs to be invalidated after completion, since we do not care about data within the unused portion. Update the DMA API to include the used length as an additional parameter to dma_unmap(), and add the necessary second cache invalidation pass to the RISC-V DMA API implementation. Signed-off-by: Michael Brown

[riscv] Add optimised TCP/IP checksumming

2025-07-10T12:32:45+00:00

Add a RISC-V assembly language implementation of TCP/IP checksumming, which is around 50x faster than the generic algorithm. The main loop checksums aligned xlen-bit words, using almost entirely compressible instructions and accumulating carries in a separate register to allow folding to be deferred until after all loops have completed. Experimentation on a C910 CPU suggests that this achieves around four bytes per clock cycle, which is comparable to the x86 implementation. Signed-off-by: Michael Brown