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<title>openslx-ng/ipxe.git/src/arch/x86/core, branch openslx</title>
<subtitle>Fork of ipxe; additional commands and features</subtitle>
<id>https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/core?h=openslx</id>
<link rel='self' href='https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/core?h=openslx'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/'/>
<updated>2026-01-14T16:10:29+00:00</updated>
<entry>
<title>[build] Mark known reviewed files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T16:10:29+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T14:36:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=adcaaf9b93f9de14ba93bea54aecef103fe16b5f'/>
<id>urn:sha1:adcaaf9b93f9de14ba93bea54aecef103fe16b5f</id>
<content type='text'>
Some past security reviews carried out for UEFI Secure Boot signing
submissions have covered specific drivers or functional areas of iPXE.
Mark all of the files comprising these areas as permitted for UEFI
Secure Boot.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[build] Mark core files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T13:25:34+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T13:25:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6cccb3bdc00359068c07125258d71ce24db5118a'/>
<id>urn:sha1:6cccb3bdc00359068c07125258d71ce24db5118a</id>
<content type='text'>
Mark all files used in a standard build of bin-x86_64-efi/snponly.efi
as permitted for UEFI Secure Boot.  These files represent the core
functionality of iPXE that is guaranteed to have been included in
every binary that was previously subject to a security review and
signed by Microsoft.  It is therefore legitimate to assume that at
least these files have already been reviewed to the required standard
multiple times.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Use linker tables for runtime selectable PCI APIs</title>
<updated>2025-11-24T20:54:01+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T20:18:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=ff1a17dc7e5d764b905559fdc623249741d173dd'/>
<id>urn:sha1:ff1a17dc7e5d764b905559fdc623249741d173dd</id>
<content type='text'>
Use the linker table mechanism to enumerate the underlying PCI I/O
APIs, to allow PCIAPI_CLOUD to become architecture-independent code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[ioapi] Provide combined MMIO and port I/O accessors</title>
<updated>2025-11-04T21:14:41+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-04T16:19:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=f7de1b53dc60ed3262181841e8cd845a50e72863'/>
<id>urn:sha1:f7de1b53dc60ed3262181841e8cd845a50e72863</id>
<content type='text'>
Some devices (such as a 16550 UART) may be accessed via either MMIO or
port I/O.  This is currently forced to be a compile-time decision.
For example: we currently access a 16550 UART via port I/O on x86 and
via MMIO on any other platform.

PCI UARTs with MMIO BARs do exist but are not currently supported in
an x86 build of iPXE.  Some AWS EC2 systems (observed on a c6i.metal
instance in eu-west-2) provide only a PCI MMIO UART, and it is
therefore currently impossible to get serial output from iPXE on these
instance types.

Add ioread8(), ioread16(), etc accessors that will select between MMIO
and port I/O at the point of use.  For non-x86 platforms where we
currently have no port I/O support, these simply become wrappers
around the corresponding readb(), readw(), etc MMIO accessors.  On
x86, we use the fairly well-known trick of treating any 16-bit address
(below 64kB) as a port I/O address.

This trick works even in the i386 BIOS build of iPXE (where virtual
addresses are offset from physical addresses by a runtime constant),
since the first 64kB of the virtual address space will correspond to
the iPXE binary itself (along with its uninitialised-data space), and
so must be RAM rather than a valid MMIO address range.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[init] Show initialisation function names in debug messages</title>
<updated>2025-07-15T13:10:33+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-07-15T13:08:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=1e3fb1b37e16cd7cd30f6b20b9eee929568f35a9'/>
<id>urn:sha1:1e3fb1b37e16cd7cd30f6b20b9eee929568f35a9</id>
<content type='text'>
Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[dwuart] Read input clock frequency from the device tree</title>
<updated>2025-06-23T21:56:38+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-23T21:40:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=9ada09c91966c42b49393307b326ff9b078ed448'/>
<id>urn:sha1:9ada09c91966c42b49393307b326ff9b078ed448</id>
<content type='text'>
The 16550 design includes a programmable 16-bit clock divider for an
arbitrary input clock, requiring knowledge of the input clock
frequency in order to calculate the divider value for a given baud
rate.  The 16550 UARTs in an x86 PC will always have a 1.8432 MHz
input clock.  Non-x86 systems may have other input clock frequencies.

Define the input clock frequency as a property of a 16550 UART, and
read the value from the device tree "clock-frequency" property.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for dynamically registered 16550 UARTs</title>
<updated>2025-06-21T22:34:32+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-21T22:11:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=cca1cfd49ec3ac0ada90197d11118a99d16aed5b'/>
<id>urn:sha1:cca1cfd49ec3ac0ada90197d11118a99d16aed5b</id>
<content type='text'>
Use the generic UART driver-private data pointer, rather than
embedding the generic UART within the 16550 UART structure.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for the existence of non-16550 UARTs</title>
<updated>2025-06-20T11:52:04+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-17T13:28:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6c8fb4b89d49c40339fe61b7ec549d90f1ce9480'/>
<id>urn:sha1:6c8fb4b89d49c40339fe61b7ec549d90f1ce9480</id>
<content type='text'>
Remove the assumption that all platforms use a fixed number of 16550
UARTs identifiable by a simple numeric index.  Create an abstraction
allowing for dynamic instantiation and registration of any number of
arbitrary UART models.

The common case of the serial console on x86 uses a single fixed UART
specified at compile time.  Avoid unnecessarily dragging in the
dynamic instantiation code in this use case by allowing COMCONSOLE to
refer to a single static UART object representing the relevant port.

When selecting a UART by command-line argument (as used in the
"gdbstub serial &lt;port&gt;" command), allow the UART to be specified as
either a numeric index (to retain backwards compatiblity) or a
case-insensitive port name such as "COM2".

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[memmap] Allow explicit colour selection for memory map debug messages</title>
<updated>2025-05-25T11:06:53+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-25T11:06:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=09140ab2c1a14b77d1e8beb407e500cb4deeb0ae'/>
<id>urn:sha1:09140ab2c1a14b77d1e8beb407e500cb4deeb0ae</id>
<content type='text'>
Provide DBGC_MEMMAP() as a replacement for memmap_dump(), allowing the
colour used to match other messages within the same message group.

Retain a dedicated colour for output from memmap_dump_all(), on the
basis that it is generally most useful to visually compare full memory
dumps against previous full memory dumps.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[memmap] Rename addr/last fields to min/max for clarity</title>
<updated>2025-05-23T15:55:42+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-23T15:55:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=036e43334ad94125dfe212480957fd397e51a053'/>
<id>urn:sha1:036e43334ad94125dfe212480957fd397e51a053</id>
<content type='text'>
Use the terminology "min" and "max" for addresses covered by a memory
region descriptor, since this is sufficiently intuitive to generally
not require further explanation.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
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