<feed xmlns='http://www.w3.org/2005/Atom'>
<title>openslx-ng/ipxe.git/src/arch/x86/include, branch openslx</title>
<subtitle>Fork of ipxe; additional commands and features</subtitle>
<id>https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/include?h=openslx</id>
<link rel='self' href='https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/include?h=openslx'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/'/>
<updated>2026-01-14T16:10:29+00:00</updated>
<entry>
<title>[build] Mark known reviewed files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T16:10:29+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T14:36:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=adcaaf9b93f9de14ba93bea54aecef103fe16b5f'/>
<id>urn:sha1:adcaaf9b93f9de14ba93bea54aecef103fe16b5f</id>
<content type='text'>
Some past security reviews carried out for UEFI Secure Boot signing
submissions have covered specific drivers or functional areas of iPXE.
Mark all of the files comprising these areas as permitted for UEFI
Secure Boot.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[build] Mark core files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T13:25:34+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T13:25:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6cccb3bdc00359068c07125258d71ce24db5118a'/>
<id>urn:sha1:6cccb3bdc00359068c07125258d71ce24db5118a</id>
<content type='text'>
Mark all files used in a standard build of bin-x86_64-efi/snponly.efi
as permitted for UEFI Secure Boot.  These files represent the core
functionality of iPXE that is guaranteed to have been included in
every binary that was previously subject to a security review and
signed by Microsoft.  It is therefore legitimate to assume that at
least these files have already been reviewed to the required standard
multiple times.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[crypto] Allow for zero-length big integer literals</title>
<updated>2025-12-29T14:01:46+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-12-29T14:01:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=7c39c04a537ce29dccc6f2bae9749d1d371429c1'/>
<id>urn:sha1:7c39c04a537ce29dccc6f2bae9749d1d371429c1</id>
<content type='text'>
Ensure that zero-length big integer literals are treated as containing
a zero value.  Avoid tests on every big integer arithmetic operation
by ensuring that bigint_required_size() always returns a non-zero
value: the zero-length tests can therefore be restricted to only
bigint_init() and bigint_done().

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Allow probing permission to vary by range</title>
<updated>2025-11-24T23:16:32+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T23:09:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=9c1ac48bcff1a623cc5422fb57c540d910ac9734'/>
<id>urn:sha1:9c1ac48bcff1a623cc5422fb57c540d910ac9734</id>
<content type='text'>
Make pci_can_probe() part of the runtime selectable PCI I/O API, and
defer this check to the per-range API.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Use linker tables for runtime selectable PCI APIs</title>
<updated>2025-11-24T20:54:01+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T20:18:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=ff1a17dc7e5d764b905559fdc623249741d173dd'/>
<id>urn:sha1:ff1a17dc7e5d764b905559fdc623249741d173dd</id>
<content type='text'>
Use the linker table mechanism to enumerate the underlying PCI I/O
APIs, to allow PCIAPI_CLOUD to become architecture-independent code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[ioapi] Allow iounmap() to be called for port I/O addresses</title>
<updated>2025-11-05T19:33:53+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-05T17:29:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=bd3982b63064590497d39d63e96d0a3f63149b73'/>
<id>urn:sha1:bd3982b63064590497d39d63e96d0a3f63149b73</id>
<content type='text'>
Allow code using the combined MMIO and port I/O accessors to safely
call iounmap() to unmap the MMIO or port I/O region.

In the virtual offset I/O mapping API as used for UEFI, 32-bit BIOS,
and 32-bit RISC-V SBI, iounmap() is a no-op anyway.  In 64-bit RISC-V
SBI, we have no concept of port I/O and so the issue is moot.

This leaves only 64-bit BIOS, where it suffices to simply do nothing
for any pages outside of the chosen MMIO virtual address range.

For symmetry, we implement the equivalent change in the very closely
related RISC-V page management code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Support 16550 UARTs accessed via either MMIO or port I/O</title>
<updated>2025-11-04T21:14:41+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-04T16:43:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=a786c8d2313ebe973ace0cbbe4f8f3825251062a'/>
<id>urn:sha1:a786c8d2313ebe973ace0cbbe4f8f3825251062a</id>
<content type='text'>
Use the combined accessors ioread8() and iowrite8() to read and write
16550 UART registers, to allow the decision between using MMIO and
port I/O to be made at runtime.

Minimise the increase in code size for x86 by ignoring the register
shift, since this is essentially used only for non-x86 SoCs.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for dynamically registered 16550 UARTs</title>
<updated>2025-06-21T22:34:32+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-21T22:11:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=cca1cfd49ec3ac0ada90197d11118a99d16aed5b'/>
<id>urn:sha1:cca1cfd49ec3ac0ada90197d11118a99d16aed5b</id>
<content type='text'>
Use the generic UART driver-private data pointer, rather than
embedding the generic UART within the 16550 UART structure.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for the existence of non-16550 UARTs</title>
<updated>2025-06-20T11:52:04+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-17T13:28:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6c8fb4b89d49c40339fe61b7ec549d90f1ce9480'/>
<id>urn:sha1:6c8fb4b89d49c40339fe61b7ec549d90f1ce9480</id>
<content type='text'>
Remove the assumption that all platforms use a fixed number of 16550
UARTs identifiable by a simple numeric index.  Create an abstraction
allowing for dynamic instantiation and registration of any number of
arbitrary UART models.

The common case of the serial console on x86 uses a single fixed UART
specified at compile time.  Avoid unnecessarily dragging in the
dynamic instantiation code in this use case by allowing COMCONSOLE to
refer to a single static UART object representing the relevant port.

When selecting a UART by command-line argument (as used in the
"gdbstub serial &lt;port&gt;" command), allow the UART to be specified as
either a numeric index (to retain backwards compatiblity) or a
case-insensitive port name such as "COM2".

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[initrd] Move initrd reshuffling to be architecture-independent code</title>
<updated>2025-05-21T11:12:16+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-21T11:07:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=c1cd54ad74200a132aff5b3d0cfce8662dec5fe4'/>
<id>urn:sha1:c1cd54ad74200a132aff5b3d0cfce8662dec5fe4</id>
<content type='text'>
There is nothing x86-specific in initrd.c, and a variant of the
reshuffling logic will be required for executing bare-metal kernels on
RISC-V and AArch64.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
</feed>
