<feed xmlns='http://www.w3.org/2005/Atom'>
<title>openslx-ng/ipxe.git/src/arch/x86/interface, branch openslx</title>
<subtitle>Fork of ipxe; additional commands and features</subtitle>
<id>https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/interface?h=openslx</id>
<link rel='self' href='https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch/x86/interface?h=openslx'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/'/>
<updated>2026-01-28T11:53:53+00:00</updated>
<entry>
<title>Merge branch 'master' into openslx</title>
<updated>2026-01-28T11:53:53+00:00</updated>
<author>
<name>Simon Rettberg</name>
</author>
<published>2026-01-28T11:53:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=8e82785c584dc13e20f9229decb95bd17bbe9cd1'/>
<id>urn:sha1:8e82785c584dc13e20f9229decb95bd17bbe9cd1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[pci] Use linker tables for runtime selectable PCI APIs</title>
<updated>2025-11-24T20:54:01+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T20:18:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=ff1a17dc7e5d764b905559fdc623249741d173dd'/>
<id>urn:sha1:ff1a17dc7e5d764b905559fdc623249741d173dd</id>
<content type='text'>
Use the linker table mechanism to enumerate the underlying PCI I/O
APIs, to allow PCIAPI_CLOUD to become architecture-independent code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Allow PCI configuration space access mechanism to vary by range</title>
<updated>2025-11-24T19:10:49+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T14:44:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=0cf2f8028c5468303f6f8ec7f639fdfd31d70e74'/>
<id>urn:sha1:0cf2f8028c5468303f6f8ec7f639fdfd31d70e74</id>
<content type='text'>
On some systems (observed on an AWS EC2 c7a.medium instance in
eu-west-2), there is no single PCI configuration space access
mechanism that covers all PCI devices.  For example: the ECAM may
provide access only to bus 01 and above, with type 1 accesses required
to access bus 00.

Allow the choice of PCI configuration space access mechanism to be
made on a per-range basis, rather than being made just once in an
initialisation function.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[init] Show initialisation function names in debug messages</title>
<updated>2025-07-15T13:10:33+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-07-15T13:08:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=1e3fb1b37e16cd7cd30f6b20b9eee929568f35a9'/>
<id>urn:sha1:1e3fb1b37e16cd7cd30f6b20b9eee929568f35a9</id>
<content type='text'>
Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pxe] Use a weak symbol for isapnp_read_port</title>
<updated>2025-06-24T12:34:41+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-24T12:26:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=97f40c5fcc4baa4ac9e69073db464fa62296855c'/>
<id>urn:sha1:97f40c5fcc4baa4ac9e69073db464fa62296855c</id>
<content type='text'>
Use a weak symbol for isapnp_read_port used in pxe_preboot.c, rather
than relying on a common symbol.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for dynamically registered 16550 UARTs</title>
<updated>2025-06-21T22:34:32+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-21T22:11:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=cca1cfd49ec3ac0ada90197d11118a99d16aed5b'/>
<id>urn:sha1:cca1cfd49ec3ac0ada90197d11118a99d16aed5b</id>
<content type='text'>
Use the generic UART driver-private data pointer, rather than
embedding the generic UART within the 16550 UART structure.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uart] Allow for the existence of non-16550 UARTs</title>
<updated>2025-06-20T11:52:04+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-06-17T13:28:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6c8fb4b89d49c40339fe61b7ec549d90f1ce9480'/>
<id>urn:sha1:6c8fb4b89d49c40339fe61b7ec549d90f1ce9480</id>
<content type='text'>
Remove the assumption that all platforms use a fixed number of 16550
UARTs identifiable by a simple numeric index.  Create an abstraction
allowing for dynamic instantiation and registration of any number of
arbitrary UART models.

The common case of the serial console on x86 uses a single fixed UART
specified at compile time.  Avoid unnecessarily dragging in the
dynamic instantiation code in this use case by allowing COMCONSOLE to
refer to a single static UART object representing the relevant port.

When selecting a UART by command-line argument (as used in the
"gdbstub serial &lt;port&gt;" command), allow the UART to be specified as
either a numeric index (to retain backwards compatiblity) or a
case-insensitive port name such as "COM2".

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[memmap] Rename addr/last fields to min/max for clarity</title>
<updated>2025-05-23T15:55:42+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-23T15:55:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=036e43334ad94125dfe212480957fd397e51a053'/>
<id>urn:sha1:036e43334ad94125dfe212480957fd397e51a053</id>
<content type='text'>
Use the terminology "min" and "max" for addresses covered by a memory
region descriptor, since this is sufficiently intuitive to generally
not require further explanation.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[uheap] Expose external heap region directly</title>
<updated>2025-05-22T15:28:15+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-22T10:58:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=11e01f0652daaf198317e2e13c8bb1d19f664ce9'/>
<id>urn:sha1:11e01f0652daaf198317e2e13c8bb1d19f664ce9</id>
<content type='text'>
We currently rely on implicit detection of the external heap region.
The INT 15 memory map mangler relies on examining the corresponding
in-use memory region, and the initrd reshuffler relies on performing a
separate detection of the largest free memory block after startup has
completed.

Replace these with explicit public symbols to describe the external
heap region.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[bios] Use generic external heap based on the system memory map</title>
<updated>2025-05-19T19:47:21+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-05-19T17:55:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=d0c35b6823db973eb20f0bfdc3e4944f16952ad7'/>
<id>urn:sha1:d0c35b6823db973eb20f0bfdc3e4944f16952ad7</id>
<content type='text'>
Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
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