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<title>openslx-ng/ipxe.git/src/arch, branch openslx</title>
<subtitle>Fork of ipxe; additional commands and features</subtitle>
<id>https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch?h=openslx</id>
<link rel='self' href='https://git.openslx.org/openslx-ng/ipxe.git/atom/src/arch?h=openslx'/>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/'/>
<updated>2026-01-28T11:53:53+00:00</updated>
<entry>
<title>Merge branch 'master' into openslx</title>
<updated>2026-01-28T11:53:53+00:00</updated>
<author>
<name>Simon Rettberg</name>
</author>
<published>2026-01-28T11:53:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=8e82785c584dc13e20f9229decb95bd17bbe9cd1'/>
<id>urn:sha1:8e82785c584dc13e20f9229decb95bd17bbe9cd1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>[prefix] Make unlzma.S compatible with 386 class CPUs</title>
<updated>2026-01-25T16:15:32+00:00</updated>
<author>
<name>Jaromir Capik</name>
</author>
<published>2026-01-12T01:40:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=641ea020f1b10a4317f758a0b73e3c8fc00f8914'/>
<id>urn:sha1:641ea020f1b10a4317f758a0b73e3c8fc00f8914</id>
<content type='text'>
Replace the bswap instruction with xchgb and roll and change the
module architecture from i486 to i386 to be consistent with the rest
of the project.

Modified-by: Michael Brown &lt;mcb30@ipxe.org&gt;
Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[build] Mark known reviewed files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T16:10:29+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T14:36:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=adcaaf9b93f9de14ba93bea54aecef103fe16b5f'/>
<id>urn:sha1:adcaaf9b93f9de14ba93bea54aecef103fe16b5f</id>
<content type='text'>
Some past security reviews carried out for UEFI Secure Boot signing
submissions have covered specific drivers or functional areas of iPXE.
Mark all of the files comprising these areas as permitted for UEFI
Secure Boot.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[build] Mark core files as permitted for UEFI Secure Boot</title>
<updated>2026-01-14T13:25:34+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2026-01-14T13:25:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=6cccb3bdc00359068c07125258d71ce24db5118a'/>
<id>urn:sha1:6cccb3bdc00359068c07125258d71ce24db5118a</id>
<content type='text'>
Mark all files used in a standard build of bin-x86_64-efi/snponly.efi
as permitted for UEFI Secure Boot.  These files represent the core
functionality of iPXE that is guaranteed to have been included in
every binary that was previously subject to a security review and
signed by Microsoft.  It is therefore legitimate to assume that at
least these files have already been reviewed to the required standard
multiple times.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[crypto] Allow for zero-length big integer literals</title>
<updated>2025-12-29T14:01:46+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-12-29T14:01:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=7c39c04a537ce29dccc6f2bae9749d1d371429c1'/>
<id>urn:sha1:7c39c04a537ce29dccc6f2bae9749d1d371429c1</id>
<content type='text'>
Ensure that zero-length big integer literals are treated as containing
a zero value.  Avoid tests on every big integer arithmetic operation
by ensuring that bigint_required_size() always returns a non-zero
value: the zero-length tests can therefore be restricted to only
bigint_init() and bigint_done().

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Allow probing permission to vary by range</title>
<updated>2025-11-24T23:16:32+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T23:09:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=9c1ac48bcff1a623cc5422fb57c540d910ac9734'/>
<id>urn:sha1:9c1ac48bcff1a623cc5422fb57c540d910ac9734</id>
<content type='text'>
Make pci_can_probe() part of the runtime selectable PCI I/O API, and
defer this check to the per-range API.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Use linker tables for runtime selectable PCI APIs</title>
<updated>2025-11-24T20:54:01+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T20:18:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=ff1a17dc7e5d764b905559fdc623249741d173dd'/>
<id>urn:sha1:ff1a17dc7e5d764b905559fdc623249741d173dd</id>
<content type='text'>
Use the linker table mechanism to enumerate the underlying PCI I/O
APIs, to allow PCIAPI_CLOUD to become architecture-independent code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[pci] Allow PCI configuration space access mechanism to vary by range</title>
<updated>2025-11-24T19:10:49+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-24T14:44:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=0cf2f8028c5468303f6f8ec7f639fdfd31d70e74'/>
<id>urn:sha1:0cf2f8028c5468303f6f8ec7f639fdfd31d70e74</id>
<content type='text'>
On some systems (observed on an AWS EC2 c7a.medium instance in
eu-west-2), there is no single PCI configuration space access
mechanism that covers all PCI devices.  For example: the ECAM may
provide access only to bus 01 and above, with type 1 accesses required
to access bus 00.

Allow the choice of PCI configuration space access mechanism to be
made on a per-range basis, rather than being made just once in an
initialisation function.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[arm] Avoid unaligned accesses for memcpy() and memset()</title>
<updated>2025-11-19T22:20:38+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-19T22:17:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=81496315f22f5ab90eddf8788fc8526eab1852f9'/>
<id>urn:sha1:81496315f22f5ab90eddf8788fc8526eab1852f9</id>
<content type='text'>
iPXE runs only in environments that support unaligned accesses to RAM.
However, memcpy() and memset() are also used to write to graphical
framebuffer memory, which may support only aligned accesses on some
CPU architectures such as ARM.

Restructure the 64-bit ARM memcpy() and memset() routines along the
lines of the RISC-V implementations, which split the region into
pre-aligned, aligned, and post-aligned sections.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
<entry>
<title>[ioapi] Allow iounmap() to be called for port I/O addresses</title>
<updated>2025-11-05T19:33:53+00:00</updated>
<author>
<name>Michael Brown</name>
</author>
<published>2025-11-05T17:29:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.openslx.org/openslx-ng/ipxe.git/commit/?id=bd3982b63064590497d39d63e96d0a3f63149b73'/>
<id>urn:sha1:bd3982b63064590497d39d63e96d0a3f63149b73</id>
<content type='text'>
Allow code using the combined MMIO and port I/O accessors to safely
call iounmap() to unmap the MMIO or port I/O region.

In the virtual offset I/O mapping API as used for UEFI, 32-bit BIOS,
and 32-bit RISC-V SBI, iounmap() is a no-op anyway.  In 64-bit RISC-V
SBI, we have no concept of port I/O and so the issue is moot.

This leaves only 64-bit BIOS, where it suffices to simply do nothing
for any pages outside of the chosen MMIO virtual address range.

For symmetry, we implement the equivalent change in the very closely
related RISC-V page management code.

Signed-off-by: Michael Brown &lt;mcb30@ipxe.org&gt;
</content>
</entry>
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