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| author | Michael Brown | 2024-10-28 14:48:11 +0100 |
|---|---|---|
| committer | Michael Brown | 2024-10-28 14:55:36 +0100 |
| commit | cd54e7c844e2148b46c960d72ed853f8f75bf400 (patch) | |
| tree | 4cf62782e85314f142695eb4792cb756d5f35a07 /src/arch/riscv/include/bits | |
| parent | [riscv] Add support for checking CPU extensions reported via device tree (diff) | |
| download | ipxe-cd54e7c844e2148b46c960d72ed853f8f75bf400.tar.gz ipxe-cd54e7c844e2148b46c960d72ed853f8f75bf400.tar.xz ipxe-cd54e7c844e2148b46c960d72ed853f8f75bf400.zip | |
[riscv] Add support for RDTIME as a timer source
The Zicntr extension defines an unprivileged wall-clock time CSR that
roughly matches the behaviour of an invariant TSC on x86. The nominal
frequency of this timer may be read from the "timebase-frequency"
property of the CPU node in the device tree.
Add a timer source using RDTIME to provide implementations of udelay()
and currticks(), modelled on the existing RDTSC-based timer for x86.
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/arch/riscv/include/bits')
| -rw-r--r-- | src/arch/riscv/include/bits/errfile.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/include/bits/errfile.h b/src/arch/riscv/include/bits/errfile.h index 03f98c206..62288ad9c 100644 --- a/src/arch/riscv/include/bits/errfile.h +++ b/src/arch/riscv/include/bits/errfile.h @@ -16,6 +16,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL ); #define ERRFILE_sbi_reboot ( ERRFILE_ARCH | ERRFILE_CORE | 0x00000000 ) #define ERRFILE_hart ( ERRFILE_ARCH | ERRFILE_CORE | 0x00010000 ) +#define ERRFILE_zicntr ( ERRFILE_ARCH | ERRFILE_CORE | 0x00020000 ) /** @} */ |